{"id":811261,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811261/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-19-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907224051.21518-19-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T22:40:46","name":"[PULL,18/23] tcg/arm: Extract INSN_NOP","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"e86a10c85598165ae15523ecff7b664317ffc2ad","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-19-richard.henderson@linaro.org/mbox/","series":[{"id":2073,"url":"http://patchwork.ozlabs.org/api/1.2/series/2073/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073","date":"2017-09-07T22:40:28","name":"[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h","version":1,"mbox":"http://patchwork.ozlabs.org/series/2073/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811261/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811261/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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This is an MSR (imm) 0,0,0 insn. Anyone know if this\n+ also Just So Happened to do nothing on pre-v6k so that we\n+ don't need to conditionalize it? */\n+ INSN_NOP_v6k = 0xe320f000,\n+ /* Otherwise the assembler uses mov r0,r0 */\n+ INSN_NOP_v4 = (COND_AL << 28) | ARITH_MOV,\n } ARMInsn;\n \n+#define INSN_NOP (use_armv7_instructions ? INSN_NOP_v6k : INSN_NOP_v4)\n+\n static const uint8_t tcg_cond_to_arm_cond[] = {\n [TCG_COND_EQ] = COND_EQ,\n [TCG_COND_NE] = COND_NE,\n@@ -375,16 +385,7 @@ static inline void tcg_out_dat_reg(TCGContext *s,\n \n static inline void tcg_out_nop(TCGContext *s)\n {\n- if (use_armv7_instructions) {\n- /* Architected nop introduced in v6k. */\n- /* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this\n- also Just So Happened to do nothing on pre-v6k so that we\n- don't need to conditionalize it? */\n- tcg_out32(s, 0xe320f000);\n- } else {\n- /* Prior to that the assembler uses mov r0, r0. */\n- tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 0, 0, 0, SHIFT_IMM_LSL(0));\n- }\n+ tcg_out32(s, INSN_NOP);\n }\n \n static inline void tcg_out_mov_reg(TCGContext *s, int cond, int rd, int rm)\n","prefixes":["PULL","18/23"]}