{"id":811256,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811256/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-10-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907224051.21518-10-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T22:40:37","name":"[PULL,09/23] tcg/s390: Use constant pool for ori","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1b064a5c85c877b4da94548eaba1f91589734f39","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-10-richard.henderson@linaro.org/mbox/","series":[{"id":2073,"url":"http://patchwork.ozlabs.org/api/1.2/series/2073/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073","date":"2017-09-07T22:40:28","name":"[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h","version":1,"mbox":"http://patchwork.ozlabs.org/series/2073/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811256/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811256/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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i < 4; i++) {\n- tcg_target_ulong mask = (0xffffull << i*16);\n- if ((val & mask) != 0 && (val & ~mask) == 0) {\n- tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);\n- return;\n- }\n+ /* Try all 32-bit insns that can perform it in one go. */\n+ for (i = 0; i < 4; i++) {\n+ tcg_target_ulong mask = (0xffffull << i*16);\n+ if ((val & mask) != 0 && (val & ~mask) == 0) {\n+ tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);\n+ return;\n }\n+ }\n \n- /* Try all 48-bit insns that can perform it in one go. */\n+ /* Try all 48-bit insns that can perform it in one go. */\n+ if (s390_facilities & FACILITY_EXT_IMM) {\n for (i = 0; i < 2; i++) {\n tcg_target_ulong mask = (0xffffffffull << i*32);\n if ((val & mask) != 0 && (val & ~mask) == 0) {\n- tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32);\n+ tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32);\n return;\n }\n }\n+ }\n \n+ /* Use the constant pool if USE_REG_TB, but not for small constants. */\n+ if (maybe_out_small_movi(s, type, TCG_TMP0, val)) {\n+ if (type == TCG_TYPE_I32) {\n+ tcg_out_insn(s, RR, OR, dest, TCG_TMP0);\n+ } else {\n+ tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0);\n+ }\n+ } else if (USE_REG_TB) {\n+ tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0);\n+ new_pool_label(s, val, R_390_20, s->code_ptr - 2,\n+ -(intptr_t)s->code_gen_ptr);\n+ } else {\n /* Perform the OR via sequential modifications to the high and\n low parts. Do this via recursion to handle 16-bit vs 32-bit\n masks in each half. */\n- tgen64_ori(s, dest, val & 0x00000000ffffffffull);\n- tgen64_ori(s, dest, val & 0xffffffff00000000ull);\n- } else {\n- /* With no extended-immediate facility, we don't need to be so\n- clever. Just iterate over the insns and mask in the constant. */\n- for (i = 0; i < 4; i++) {\n- tcg_target_ulong mask = (0xffffull << i*16);\n- if ((val & mask) != 0) {\n- tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16);\n- }\n- }\n+ tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM);\n+ tgen_ori(s, type, dest, val & 0x00000000ffffffffull);\n+ tgen_ori(s, type, dest, val & 0xffffffff00000000ull);\n }\n }\n \n@@ -1872,7 +1878,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2];\n if (const_args[2]) {\n tcg_out_mov(s, TCG_TYPE_I32, a0, a1);\n- tgen64_ori(s, a0, a2);\n+ tgen_ori(s, TCG_TYPE_I32, a0, a2);\n } else if (a0 == a1) {\n tcg_out_insn(s, RR, OR, a0, a2);\n } else {\n@@ -2104,7 +2110,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n a0 = args[0], a1 = args[1], a2 = args[2];\n if (const_args[2]) {\n tcg_out_mov(s, TCG_TYPE_I64, a0, a1);\n- tgen64_ori(s, a0, a2);\n+ tgen_ori(s, TCG_TYPE_I64, a0, a2);\n } else if (a0 == a1) {\n tcg_out_insn(s, RRE, OGR, a0, a2);\n } else {\n@@ -2312,7 +2318,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { \"r\", \"0\", \"rJ\" } };\n- static const TCGTargetOpDef r_0_rN = { .args_ct_str = { \"r\", \"0\", \"rN\" } };\n static const TCGTargetOpDef r_0_rM = { .args_ct_str = { \"r\", \"0\", \"rM\" } };\n static const TCGTargetOpDef a2_r\n = { .args_ct_str = { \"r\", \"r\", \"0\", \"1\", \"r\", \"r\" } };\n@@ -2353,6 +2358,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_sub_i64:\n case INDEX_op_and_i32:\n case INDEX_op_and_i64:\n+ case INDEX_op_or_i32:\n+ case INDEX_op_or_i64:\n return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri);\n \n case INDEX_op_mul_i32:\n@@ -2363,19 +2370,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n case INDEX_op_mul_i64:\n return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI);\n \n- case INDEX_op_or_i32:\n- /* The use of [iNM] constraints are optimization only, since a full\n- 64-bit immediate OR can always be performed with 4 sequential\n- OI[LH][LH] instructions. By rejecting certain negative ranges,\n- the immediate load plus the reg-reg OR is smaller. */\n- return (s390_facilities & FACILITY_EXT_IMM\n- ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri)\n- : &r_0_rN);\n- case INDEX_op_or_i64:\n- return (s390_facilities & FACILITY_EXT_IMM\n- ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM)\n- : &r_0_rN);\n-\n case INDEX_op_xor_i32:\n /* Without EXT_IMM, no immediates are supported. Otherwise,\n rejecting certain negative ranges leads to smaller code. */\n","prefixes":["PULL","09/23"]}