{"id":811253,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811253/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-14-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907224051.21518-14-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T22:40:41","name":"[PULL,13/23] tcg/sparc: Introduce TCG_REG_TB","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"1054817e558a091c4734ff608473dc6fca977942","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-14-richard.henderson@linaro.org/mbox/","series":[{"id":2073,"url":"http://patchwork.ozlabs.org/api/1.2/series/2073/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073","date":"2017-09-07T22:40:28","name":"[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h","version":1,"mbox":"http://patchwork.ozlabs.org/series/2073/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811253/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811253/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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-0700","Message-Id":"<20170907224051.21518-14-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170907224051.21518-1-richard.henderson@linaro.org>","References":"<20170907224051.21518-1-richard.henderson@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::232","Subject":"[Qemu-devel] [PULL 13/23] tcg/sparc: Introduce TCG_REG_TB","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Richard Henderson \n\nSigned-off-by: Richard Henderson \n---\n tcg/sparc/tcg-target.inc.c | 170 +++++++++++++++++++++++++++++++++++++--------\n 1 file changed, 140 insertions(+), 30 deletions(-)","diff":"diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c\nindex bb7f7e8906..7d73c25347 100644\n--- a/tcg/sparc/tcg-target.inc.c\n+++ b/tcg/sparc/tcg-target.inc.c\n@@ -85,6 +85,9 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {\n # define TCG_GUEST_BASE_REG TCG_REG_I5\n #endif\n \n+#define TCG_REG_TB TCG_REG_I1\n+#define USE_REG_TB (sizeof(void *) > 4)\n+\n static const int tcg_target_reg_alloc_order[] = {\n TCG_REG_L0,\n TCG_REG_L1,\n@@ -249,6 +252,8 @@ static const int tcg_target_call_oarg_regs[] = {\n \n #define MEMBAR (INSN_OP(2) | INSN_OP3(0x28) | INSN_RS1(15) | (1 << 13))\n \n+#define NOP (SETHI | INSN_RD(TCG_REG_G0) | 0)\n+\n #ifndef ASI_PRIMARY_LITTLE\n #define ASI_PRIMARY_LITTLE 0x88\n #endif\n@@ -423,10 +428,11 @@ static inline void tcg_out_movi_imm13(TCGContext *s, TCGReg ret, int32_t arg)\n tcg_out_arithi(s, ret, TCG_REG_G0, arg, ARITH_OR);\n }\n \n-static void tcg_out_movi(TCGContext *s, TCGType type,\n- TCGReg ret, tcg_target_long arg)\n+static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,\n+ tcg_target_long arg, bool in_prologue)\n {\n tcg_target_long hi, lo = (int32_t)arg;\n+ tcg_target_long test, lsb;\n \n /* Make sure we test 32-bit constants for imm13 properly. */\n if (type == TCG_TYPE_I32) {\n@@ -455,6 +461,27 @@ static void tcg_out_movi(TCGContext *s, TCGType type,\n return;\n }\n \n+ /* A 21-bit constant, shifted. */\n+ lsb = ctz64(arg);\n+ test = (tcg_target_long)arg >> lsb;\n+ if (check_fit_tl(test, 13)) {\n+ tcg_out_movi_imm13(s, ret, test);\n+ tcg_out_arithi(s, ret, ret, lsb, SHIFT_SLLX);\n+ return;\n+ } else if (lsb > 10 && test == extract64(test, 0, 21)) {\n+ tcg_out_sethi(s, ret, test << 10);\n+ tcg_out_arithi(s, ret, ret, lsb - 10, SHIFT_SLLX);\n+ return;\n+ }\n+\n+ if (USE_REG_TB && !in_prologue) {\n+ intptr_t diff = arg - (uintptr_t)s->code_gen_ptr;\n+ if (check_fit_ptr(diff, 13)) {\n+ tcg_out_arithi(s, ret, TCG_REG_TB, diff, ARITH_ADD);\n+ return;\n+ }\n+ }\n+\n /* A 64-bit constant decomposed into 2 32-bit pieces. */\n if (check_fit_i32(lo, 13)) {\n hi = (arg - lo) >> 32;\n@@ -470,6 +497,12 @@ static void tcg_out_movi(TCGContext *s, TCGType type,\n }\n }\n \n+static inline void tcg_out_movi(TCGContext *s, TCGType type,\n+ TCGReg ret, tcg_target_long arg)\n+{\n+ tcg_out_movi_int(s, type, ret, arg, false);\n+}\n+\n static inline void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1,\n TCGReg a2, int op)\n {\n@@ -512,6 +545,11 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,\n \n static void tcg_out_ld_ptr(TCGContext *s, TCGReg ret, uintptr_t arg)\n {\n+ intptr_t diff = arg - (uintptr_t)s->code_gen_ptr;\n+ if (USE_REG_TB && check_fit_ptr(diff, 13)) {\n+ tcg_out_ld(s, TCG_TYPE_PTR, ret, TCG_REG_TB, diff);\n+ return;\n+ }\n tcg_out_movi(s, TCG_TYPE_PTR, ret, arg & ~0x3ff);\n tcg_out_ld(s, TCG_TYPE_PTR, ret, ret, arg & 0x3ff);\n }\n@@ -543,7 +581,7 @@ static void tcg_out_div32(TCGContext *s, TCGReg rd, TCGReg rs1,\n \n static inline void tcg_out_nop(TCGContext *s)\n {\n- tcg_out_sethi(s, TCG_REG_G0, 0);\n+ tcg_out32(s, NOP);\n }\n \n static const uint8_t tcg_cond_to_bcond[] = {\n@@ -812,7 +850,8 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,\n tcg_out_mov(s, TCG_TYPE_I64, rl, tmp);\n }\n \n-static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest)\n+static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest,\n+ bool in_prologue)\n {\n ptrdiff_t disp = tcg_pcrel_diff(s, dest);\n \n@@ -820,14 +859,15 @@ static void tcg_out_call_nodelay(TCGContext *s, tcg_insn_unit *dest)\n tcg_out32(s, CALL | (uint32_t)disp >> 2);\n } else {\n uintptr_t desti = (uintptr_t)dest;\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, desti & ~0xfff);\n+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_REG_T1,\n+ desti & ~0xfff, in_prologue);\n tcg_out_arithi(s, TCG_REG_O7, TCG_REG_T1, desti & 0xfff, JMPL);\n }\n }\n \n static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)\n {\n- tcg_out_call_nodelay(s, dest);\n+ tcg_out_call_nodelay(s, dest, false);\n tcg_out_nop(s);\n }\n \n@@ -915,7 +955,7 @@ static void build_trampolines(TCGContext *s)\n /* Set the env operand. */\n tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);\n /* Tail call. */\n- tcg_out_call_nodelay(s, qemu_ld_helpers[i]);\n+ tcg_out_call_nodelay(s, qemu_ld_helpers[i], true);\n tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);\n }\n \n@@ -964,7 +1004,7 @@ static void build_trampolines(TCGContext *s)\n /* Set the env operand. */\n tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O0, TCG_AREG0);\n /* Tail call. */\n- tcg_out_call_nodelay(s, qemu_st_helpers[i]);\n+ tcg_out_call_nodelay(s, qemu_st_helpers[i], true);\n tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_O7, ra);\n }\n }\n@@ -992,11 +1032,17 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n \n #ifndef CONFIG_SOFTMMU\n if (guest_base != 0) {\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);\n+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);\n tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);\n }\n #endif\n \n+ /* We choose TCG_REG_TB such that no move is required. */\n+ if (USE_REG_TB) {\n+ QEMU_BUILD_BUG_ON(TCG_REG_TB != TCG_REG_I1);\n+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);\n+ }\n+\n tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I1, 0, JMPL);\n /* delay slot */\n tcg_out_nop(s);\n@@ -1156,7 +1202,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,\n func = qemu_ld_trampoline[memop & (MO_BSWAP | MO_SSIZE)];\n }\n tcg_debug_assert(func != NULL);\n- tcg_out_call_nodelay(s, func);\n+ tcg_out_call_nodelay(s, func, false);\n /* delay slot */\n tcg_out_movi(s, TCG_TYPE_I32, param, oi);\n \n@@ -1235,7 +1281,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,\n \n func = qemu_st_trampoline[memop & (MO_BSWAP | MO_SIZE)];\n tcg_debug_assert(func != NULL);\n- tcg_out_call_nodelay(s, func);\n+ tcg_out_call_nodelay(s, func, false);\n /* delay slot */\n tcg_out_movi(s, TCG_TYPE_I32, param, oi);\n \n@@ -1269,30 +1315,67 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,\n if (check_fit_ptr(a0, 13)) {\n tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);\n tcg_out_movi_imm13(s, TCG_REG_O0, a0);\n- } else {\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff);\n- tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);\n- tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR);\n+ break;\n+ } else if (USE_REG_TB) {\n+ intptr_t tb_diff = a0 - (uintptr_t)s->code_gen_ptr;\n+ if (check_fit_ptr(tb_diff, 13)) {\n+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);\n+ /* Note that TCG_REG_TB has been unwound to O1. */\n+ tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O1, tb_diff, ARITH_ADD);\n+ break;\n+ }\n }\n+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_I0, a0 & ~0x3ff);\n+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_I7, 8, RETURN);\n+ tcg_out_arithi(s, TCG_REG_O0, TCG_REG_O0, a0 & 0x3ff, ARITH_OR);\n break;\n case INDEX_op_goto_tb:\n if (s->tb_jmp_insn_offset) {\n /* direct jump method */\n- s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);\n- /* Make sure to preserve links during retranslation. */\n- tcg_out32(s, CALL | (*s->code_ptr & ~INSN_OP(-1)));\n+ if (USE_REG_TB) {\n+ /* make sure the patch is 8-byte aligned. */\n+ if ((intptr_t)s->code_ptr & 4) {\n+ tcg_out_nop(s);\n+ }\n+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);\n+ tcg_out_sethi(s, TCG_REG_T1, 0);\n+ tcg_out_arithi(s, TCG_REG_T1, TCG_REG_T1, 0, ARITH_OR);\n+ tcg_out_arith(s, TCG_REG_G0, TCG_REG_TB, TCG_REG_T1, JMPL);\n+ tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB, TCG_REG_T1, ARITH_ADD);\n+ } else {\n+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);\n+ tcg_out32(s, CALL);\n+ tcg_out_nop(s);\n+ }\n } else {\n /* indirect jump method */\n- tcg_out_ld_ptr(s, TCG_REG_T1,\n+ tcg_out_ld_ptr(s, TCG_REG_TB,\n (uintptr_t)(s->tb_jmp_target_addr + a0));\n- tcg_out_arithi(s, TCG_REG_G0, TCG_REG_T1, 0, JMPL);\n+ tcg_out_arithi(s, TCG_REG_G0, TCG_REG_TB, 0, JMPL);\n+ tcg_out_nop(s);\n+ }\n+ s->tb_jmp_reset_offset[a0] = c = tcg_current_code_size(s);\n+\n+ /* For the unlinked path of goto_tb, we need to reset\n+ TCG_REG_TB to the beginning of this TB. */\n+ if (USE_REG_TB) {\n+ c = -c;\n+ if (check_fit_i32(c, 13)) {\n+ tcg_out_arithi(s, TCG_REG_TB, TCG_REG_TB, c, ARITH_ADD);\n+ } else {\n+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T1, c);\n+ tcg_out_arith(s, TCG_REG_TB, TCG_REG_TB,\n+ TCG_REG_T1, ARITH_ADD);\n+ }\n }\n- tcg_out_nop(s);\n- s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s);\n break;\n case INDEX_op_goto_ptr:\n tcg_out_arithi(s, TCG_REG_G0, a0, 0, JMPL);\n- tcg_out_nop(s);\n+ if (USE_REG_TB) {\n+ tcg_out_arith(s, TCG_REG_TB, a0, TCG_REG_G0, ARITH_OR);\n+ } else {\n+ tcg_out_nop(s);\n+ }\n break;\n case INDEX_op_br:\n tcg_out_bpcc(s, COND_A, BPCC_PT, arg_label(a0));\n@@ -1709,13 +1792,40 @@ void tcg_register_jit(void *buf, size_t buf_size)\n void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,\n uintptr_t addr)\n {\n- uint32_t *ptr = (uint32_t *)jmp_addr;\n- uintptr_t disp = addr - jmp_addr;\n+ intptr_t tb_disp = addr - tc_ptr;\n+ intptr_t br_disp = addr - jmp_addr;\n+ tcg_insn_unit i1, i2;\n+\n+ /* We can reach the entire address space for ILP32.\n+ For LP64, the code_gen_buffer can't be larger than 2GB. */\n+ tcg_debug_assert(tb_disp == (int32_t)tb_disp);\n+ tcg_debug_assert(br_disp == (int32_t)br_disp);\n+\n+ if (!USE_REG_TB) {\n+ atomic_set((uint32_t *)jmp_addr, deposit32(CALL, 0, 30, br_disp >> 2));\n+ flush_icache_range(jmp_addr, jmp_addr + 4);\n+ return;\n+ }\n \n- /* We can reach the entire address space for 32-bit. For 64-bit\n- the code_gen_buffer can't be larger than 2GB. */\n- tcg_debug_assert(disp == (int32_t)disp);\n+ /* This does not exercise the range of the branch, but we do\n+ still need to be able to load the new value of TCG_REG_TB.\n+ But this does still happen quite often. */\n+ if (check_fit_ptr(tb_disp, 13)) {\n+ /* ba,pt %icc, addr */\n+ i1 = (INSN_OP(0) | INSN_OP2(1) | INSN_COND(COND_A)\n+ | BPCC_ICC | BPCC_PT | INSN_OFF19(br_disp));\n+ i2 = (ARITH_ADD | INSN_RD(TCG_REG_TB) | INSN_RS1(TCG_REG_TB)\n+ | INSN_IMM13(tb_disp));\n+ } else if (tb_disp >= 0) {\n+ i1 = SETHI | INSN_RD(TCG_REG_T1) | ((tb_disp & 0xfffffc00) >> 10);\n+ i2 = (ARITH_OR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1)\n+ | INSN_IMM13(tb_disp & 0x3ff));\n+ } else {\n+ i1 = SETHI | INSN_RD(TCG_REG_T1) | ((~tb_disp & 0xfffffc00) >> 10);\n+ i2 = (ARITH_XOR | INSN_RD(TCG_REG_T1) | INSN_RS1(TCG_REG_T1)\n+ | INSN_IMM13((tb_disp & 0x3ff) | -0x400));\n+ }\n \n- atomic_set(ptr, deposit32(CALL, 0, 30, disp >> 2));\n- flush_icache_range(jmp_addr, jmp_addr + 4);\n+ atomic_set((uint64_t *)jmp_addr, deposit64(i2, 32, 32, i1));\n+ flush_icache_range(jmp_addr, jmp_addr + 8);\n }\n","prefixes":["PULL","13/23"]}