{"id":811225,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811225/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-12-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907224051.21518-12-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T22:40:39","name":"[PULL,11/23] tcg/s390: Use constant pool for cmpi","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ef0b6a3c7b37134b3645c155669abf6145416c8d","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-12-richard.henderson@linaro.org/mbox/","series":[{"id":2073,"url":"http://patchwork.ozlabs.org/api/1.2/series/2073/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073","date":"2017-09-07T22:40:28","name":"[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h","version":1,"mbox":"http://patchwork.ozlabs.org/series/2073/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811225/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811225/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=UqbemKBcSAFRk6ka+QSoQnu16oHX7Q4v8g2SbdNvrNg=;\n\tb=DVs7GjtYDhGtrUP35qnRH94w0rKTjLvrZJsF/7zsro1hjNkjTfiktKoVOpHdBm9ugb\n\ttNN7/0ZsBxie28lkejZo8Co5Gk6aqQ8+zVmTQFJKwj/+xmJnuqnLYd+JHSy3g44baF/i\n\tbr9xOi/HUhU7WzJjMfudcNYtyL2SeH0xv2HeN+8XjCq3iZfFWAZ30LH+YohI6DqPh12W\n\th1fcExcoahJp3iGus2+2eRBwT9GEsneH9EM6OPtwkV1WzI/B/meZO3tXgEVgzQQO4cyz\n\t4NtpXpAKzO603rPbg2fp2RZJRDIvPLlasWec8cbNjk2hN4pqTwB17ssJer4uqKEQ5btM\n\t9f3A==","X-Gm-Message-State":"AHPjjUj0R0Q87ZBKmoL/qHpsDr0hJwNU1OtCCxgI6dCczBDVGRNRfAHl\n\tdsvSEjKibn4L+xcKRwKUEQ==","X-Google-Smtp-Source":"ADKCNb5+ckXCrF6q6YJFifvsgY+QZqxirFKKvIQepWd4NC/tI2knqNyVlnDGx7t+VUXo5hZUcCqETw==","X-Received":"by 10.99.116.21 with SMTP id p21mr944350pgc.93.1504824070414;\n\tThu, 07 Sep 2017 15:41:10 -0700 (PDT)","From":"Richard Henderson ","To":"qemu-devel@nongnu.org","Date":"Thu, 7 Sep 2017 15:40:39 -0700","Message-Id":"<20170907224051.21518-12-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170907224051.21518-1-richard.henderson@linaro.org>","References":"<20170907224051.21518-1-richard.henderson@linaro.org>","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c05::22e","Subject":"[Qemu-devel] [PULL 11/23] tcg/s390: Use constant pool for cmpi","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, Richard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Richard Henderson \n\nAlso use CHI/CGHI for 16-bit signed constants.\n\nSigned-off-by: Richard Henderson \n---\n tcg/s390/tcg-target.inc.c | 136 +++++++++++++++++++++++-----------------------\n 1 file changed, 67 insertions(+), 69 deletions(-)","diff":"diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c\nindex b0b34fa5ab..e7ab8e4df3 100644\n--- a/tcg/s390/tcg-target.inc.c\n+++ b/tcg/s390/tcg-target.inc.c\n@@ -39,9 +39,8 @@\n \n #define TCG_CT_CONST_S16 0x100\n #define TCG_CT_CONST_S32 0x200\n-#define TCG_CT_CONST_U31 0x400\n-#define TCG_CT_CONST_S33 0x800\n-#define TCG_CT_CONST_ZERO 0x1000\n+#define TCG_CT_CONST_S33 0x400\n+#define TCG_CT_CONST_ZERO 0x800\n \n /* Several places within the instruction set 0 means \"no register\"\n rather than TCG_REG_R0. */\n@@ -75,6 +74,10 @@ typedef enum S390Opcode {\n RIL_CGFI = 0xc20c,\n RIL_CLFI = 0xc20f,\n RIL_CLGFI = 0xc20e,\n+ RIL_CLRL = 0xc60f,\n+ RIL_CLGRL = 0xc60a,\n+ RIL_CRL = 0xc60d,\n+ RIL_CGRL = 0xc608,\n RIL_IIHF = 0xc008,\n RIL_IILF = 0xc009,\n RIL_LARL = 0xc000,\n@@ -97,6 +100,8 @@ typedef enum S390Opcode {\n RI_AGHI = 0xa70b,\n RI_AHI = 0xa70a,\n RI_BRC = 0xa704,\n+ RI_CHI = 0xa70e,\n+ RI_CGHI = 0xa70f,\n RI_IIHH = 0xa500,\n RI_IIHL = 0xa501,\n RI_IILH = 0xa502,\n@@ -206,6 +211,8 @@ typedef enum S390Opcode {\n RXY_AG = 0xe308,\n RXY_AY = 0xe35a,\n RXY_CG = 0xe320,\n+ RXY_CLG = 0xe321,\n+ RXY_CLY = 0xe355,\n RXY_CY = 0xe359,\n RXY_LAY = 0xe371,\n RXY_LB = 0xe376,\n@@ -423,20 +430,6 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,\n case 'J':\n ct->ct |= TCG_CT_CONST_S32;\n break;\n- case 'C':\n- /* ??? We have no insight here into whether the comparison is\n- signed or unsigned. The COMPARE IMMEDIATE insn uses a 32-bit\n- signed immediate, and the COMPARE LOGICAL IMMEDIATE insn uses\n- a 32-bit unsigned immediate. If we were to use the (semi)\n- obvious \"val == (int32_t)val\" we would be enabling unsigned\n- comparisons vs very large numbers. The only solution is to\n- take the intersection of the ranges. */\n- /* ??? Another possible solution is to simply lie and allow all\n- constants here and force the out-of-range values into a temp\n- register in tgen_cmp when we have knowledge of the actual\n- comparison code in use. */\n- ct->ct |= TCG_CT_CONST_U31;\n- break;\n case 'Z':\n ct->ct |= TCG_CT_CONST_ZERO;\n break;\n@@ -467,8 +460,6 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,\n return val == (int32_t)val;\n } else if (ct & TCG_CT_CONST_S33) {\n return val >= -0xffffffffll && val <= 0xffffffffll;\n- } else if (ct & TCG_CT_CONST_U31) {\n- return val >= 0 && val <= 0x7fffffff;\n } else if (ct & TCG_CT_CONST_ZERO) {\n return val == 0;\n }\n@@ -1092,6 +1083,8 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,\n TCGArg c2, bool c2const, bool need_carry)\n {\n bool is_unsigned = is_unsigned_cond(c);\n+ S390Opcode op;\n+\n if (c2const) {\n if (c2 == 0) {\n if (!(is_unsigned && need_carry)) {\n@@ -1102,44 +1095,67 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,\n }\n return tcg_cond_to_ltr_cond[c];\n }\n- /* If we only got here because of load-and-test,\n- and we couldn't use that, then we need to load\n- the constant into a register. */\n- if (!(s390_facilities & FACILITY_EXT_IMM)) {\n- c2 = TCG_TMP0;\n- tcg_out_movi(s, type, c2, 0);\n- goto do_reg;\n- }\n }\n- if (is_unsigned) {\n- if (type == TCG_TYPE_I32) {\n- tcg_out_insn(s, RIL, CLFI, r1, c2);\n- } else {\n- tcg_out_insn(s, RIL, CLGFI, r1, c2);\n- }\n- } else {\n+\n+ if (!is_unsigned && c2 == (int16_t)c2) {\n+ op = (type == TCG_TYPE_I32 ? RI_CHI : RI_CGHI);\n+ tcg_out_insn_RI(s, op, r1, c2);\n+ goto exit;\n+ }\n+\n+ if (s390_facilities & FACILITY_EXT_IMM) {\n if (type == TCG_TYPE_I32) {\n- tcg_out_insn(s, RIL, CFI, r1, c2);\n- } else {\n- tcg_out_insn(s, RIL, CGFI, r1, c2);\n+ op = (is_unsigned ? RIL_CLFI : RIL_CFI);\n+ tcg_out_insn_RIL(s, op, r1, c2);\n+ goto exit;\n+ } else if (c2 == (is_unsigned ? (uint32_t)c2 : (int32_t)c2)) {\n+ op = (is_unsigned ? RIL_CLGFI : RIL_CGFI);\n+ tcg_out_insn_RIL(s, op, r1, c2);\n+ goto exit;\n }\n }\n- } else {\n- do_reg:\n- if (is_unsigned) {\n+\n+ /* Use the constant pool, but not for small constants. */\n+ if (maybe_out_small_movi(s, type, TCG_TMP0, c2)) {\n+ c2 = TCG_TMP0;\n+ /* fall through to reg-reg */\n+ } else if (USE_REG_TB) {\n if (type == TCG_TYPE_I32) {\n- tcg_out_insn(s, RR, CLR, r1, c2);\n+ op = (is_unsigned ? RXY_CLY : RXY_CY);\n+ tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);\n+ new_pool_label(s, (uint32_t)c2, R_390_20, s->code_ptr - 2,\n+ 4 - (intptr_t)s->code_gen_ptr);\n } else {\n- tcg_out_insn(s, RRE, CLGR, r1, c2);\n+ op = (is_unsigned ? RXY_CLG : RXY_CG);\n+ tcg_out_insn_RXY(s, op, r1, TCG_REG_TB, TCG_REG_NONE, 0);\n+ new_pool_label(s, c2, R_390_20, s->code_ptr - 2,\n+ -(intptr_t)s->code_gen_ptr);\n }\n+ goto exit;\n } else {\n if (type == TCG_TYPE_I32) {\n- tcg_out_insn(s, RR, CR, r1, c2);\n+ op = (is_unsigned ? RIL_CLRL : RIL_CRL);\n+ tcg_out_insn_RIL(s, op, r1, 0);\n+ new_pool_label(s, (uint32_t)c2, R_390_PC32DBL,\n+ s->code_ptr - 2, 2 + 4);\n } else {\n- tcg_out_insn(s, RRE, CGR, r1, c2);\n+ op = (is_unsigned ? RIL_CLGRL : RIL_CGRL);\n+ tcg_out_insn_RIL(s, op, r1, 0);\n+ new_pool_label(s, c2, R_390_PC32DBL, s->code_ptr - 2, 2);\n }\n+ goto exit;\n }\n }\n+\n+ if (type == TCG_TYPE_I32) {\n+ op = (is_unsigned ? RR_CLR : RR_CR);\n+ tcg_out_insn_RR(s, op, r1, c2);\n+ } else {\n+ op = (is_unsigned ? RRE_CLGR : RRE_CGR);\n+ tcg_out_insn_RRE(s, op, r1, c2);\n+ }\n+\n+ exit:\n return tcg_cond_to_s390_cond[c];\n }\n \n@@ -2325,8 +2341,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n static const TCGTargetOpDef r_L = { .args_ct_str = { \"r\", \"L\" } };\n static const TCGTargetOpDef L_L = { .args_ct_str = { \"L\", \"L\" } };\n static const TCGTargetOpDef r_ri = { .args_ct_str = { \"r\", \"ri\" } };\n- static const TCGTargetOpDef r_rC = { .args_ct_str = { \"r\", \"rC\" } };\n- static const TCGTargetOpDef r_rZ = { .args_ct_str = { \"r\", \"rZ\" } };\n static const TCGTargetOpDef r_r_ri = { .args_ct_str = { \"r\", \"r\", \"ri\" } };\n static const TCGTargetOpDef r_0_ri = { .args_ct_str = { \"r\", \"0\", \"ri\" } };\n static const TCGTargetOpDef r_0_rI = { .args_ct_str = { \"r\", \"0\", \"rI\" } };\n@@ -2401,10 +2415,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n return &r_r_ri;\n \n case INDEX_op_brcond_i32:\n- /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n- return (s390_facilities & FACILITY_EXT_IMM ? &r_ri : &r_rZ);\n case INDEX_op_brcond_i64:\n- return (s390_facilities & FACILITY_EXT_IMM ? &r_rC : &r_rZ);\n+ return &r_ri;\n \n case INDEX_op_bswap16_i32:\n case INDEX_op_bswap16_i64:\n@@ -2430,6 +2442,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n return &r_r;\n \n case INDEX_op_clz_i64:\n+ case INDEX_op_setcond_i32:\n+ case INDEX_op_setcond_i64:\n return &r_r_ri;\n \n case INDEX_op_qemu_ld_i32:\n@@ -2446,30 +2460,14 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)\n = { .args_ct_str = { \"r\", \"rZ\", \"r\" } };\n return &dep;\n }\n- case INDEX_op_setcond_i32:\n- case INDEX_op_setcond_i64:\n- {\n- /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n- static const TCGTargetOpDef setc_z\n- = { .args_ct_str = { \"r\", \"r\", \"rZ\" } };\n- static const TCGTargetOpDef setc_c\n- = { .args_ct_str = { \"r\", \"r\", \"rC\" } };\n- return (s390_facilities & FACILITY_EXT_IMM ? &setc_c : &setc_z);\n- }\n case INDEX_op_movcond_i32:\n case INDEX_op_movcond_i64:\n {\n- /* Without EXT_IMM, only the LOAD AND TEST insn is available. */\n- static const TCGTargetOpDef movc_z\n- = { .args_ct_str = { \"r\", \"r\", \"rZ\", \"r\", \"0\" } };\n- static const TCGTargetOpDef movc_c\n- = { .args_ct_str = { \"r\", \"r\", \"rC\", \"r\", \"0\" } };\n+ static const TCGTargetOpDef movc\n+ = { .args_ct_str = { \"r\", \"r\", \"ri\", \"r\", \"0\" } };\n static const TCGTargetOpDef movc_l\n- = { .args_ct_str = { \"r\", \"r\", \"rC\", \"rI\", \"0\" } };\n- return (s390_facilities & FACILITY_EXT_IMM\n- ? (s390_facilities & FACILITY_LOAD_ON_COND2\n- ? &movc_l : &movc_c)\n- : &movc_z);\n+ = { .args_ct_str = { \"r\", \"r\", \"ri\", \"rI\", \"0\" } };\n+ return (s390_facilities & FACILITY_LOAD_ON_COND2 ? &movc_l : &movc);\n }\n case INDEX_op_div2_i32:\n case INDEX_op_div2_i64:\n","prefixes":["PULL","11/23"]}