{"id":811210,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811210/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-20-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907224051.21518-20-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T22:40:47","name":"[PULL,19/23] tcg/arm: Use constant pool for movi","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"a04ca0577906eadbe8dde9caa8ffb2dce617f3de","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-20-richard.henderson@linaro.org/mbox/","series":[{"id":2073,"url":"http://patchwork.ozlabs.org/api/1.2/series/2073/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073","date":"2017-09-07T22:40:28","name":"[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h","version":1,"mbox":"http://patchwork.ozlabs.org/series/2073/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811210/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811210/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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TCG_REG_TMP : rd;\n+ assert(diff >= 0x1000 && diff < 0x100000);\n+ /* add rt, pc, #high */\n+ *code_ptr++ = ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD\n+ | (TCG_REG_PC << 16) | (rt << 12)\n+ | (20 << 7) | (diff >> 12));\n+ /* ldr rd, [rt, #low] */\n+ insn = deposit32(insn, 12, 4, rt);\n+ diff &= 0xfff;\n+ u = 1;\n+ }\n+ insn = deposit32(insn, 23, 1, u);\n+ insn = deposit32(insn, 0, 12, diff);\n+ *code_ptr = insn;\n+ } else {\n+ g_assert_not_reached();\n+ }\n }\n \n #define TCG_CT_CONST_ARM 0x100\n@@ -581,9 +612,20 @@ static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,\n tcg_out_memop_r(s, cond, INSN_LDRSB_REG, rt, rn, rm, 1, 1, 0);\n }\n \n+static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg)\n+{\n+ /* The 12-bit range on the ldr insn is sometimes a bit too small.\n+ In order to get around that we require two insns, one of which\n+ will usually be a nop, but may be replaced in patch_reloc. */\n+ new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0);\n+ tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0);\n+ tcg_out_nop(s);\n+}\n+\n static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)\n {\n- int rot, opc, rn, diff;\n+ int rot, diff, opc, sh1, sh2;\n+ uint32_t tt0, tt1, tt2;\n \n /* Check a single MOV/MVN before anything else. */\n rot = encode_imm(arg);\n@@ -631,24 +673,30 @@ static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)\n return;\n }\n \n- /* TODO: This is very suboptimal, we can easily have a constant\n- pool somewhere after all the instructions. */\n+ /* Look for sequences of two insns. If we have lots of 1's, we can\n+ shorten the sequence by beginning with mvn and then clearing\n+ higher bits with eor. */\n+ tt0 = arg;\n opc = ARITH_MOV;\n- rn = 0;\n- /* If we have lots of leading 1's, we can shorten the sequence by\n- beginning with mvn and then clearing higher bits with eor. */\n- if (clz32(~arg) > clz32(arg)) {\n- opc = ARITH_MVN, arg = ~arg;\n+ if (ctpop32(arg) > 16) {\n+ tt0 = ~arg;\n+ opc = ARITH_MVN;\n+ }\n+ sh1 = ctz32(tt0) & ~1;\n+ tt1 = tt0 & ~(0xff << sh1);\n+ sh2 = ctz32(tt1) & ~1;\n+ tt2 = tt1 & ~(0xff << sh2);\n+ if (tt2 == 0) {\n+ rot = ((32 - sh1) << 7) & 0xf00;\n+ tcg_out_dat_imm(s, cond, opc, rd, 0, ((tt0 >> sh1) & 0xff) | rot);\n+ rot = ((32 - sh2) << 7) & 0xf00;\n+ tcg_out_dat_imm(s, cond, ARITH_EOR, rd, rd,\n+ ((tt0 >> sh2) & 0xff) | rot);\n+ return;\n }\n- do {\n- int i = ctz32(arg) & ~1;\n- rot = ((32 - i) << 7) & 0xf00;\n- tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot);\n- arg &= ~(0xff << i);\n \n- opc = ARITH_EOR;\n- rn = rd;\n- } while (arg);\n+ /* Otherwise, drop it into the constant pool. */\n+ tcg_out_movi_pool(s, cond, rd, arg);\n }\n \n static inline void tcg_out_dat_rI(TCGContext *s, int cond, int opc, TCGArg dst,\n@@ -2164,6 +2212,14 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type,\n tcg_out_movi32(s, COND_AL, ret, arg);\n }\n \n+static void tcg_out_nop_fill(tcg_insn_unit *p, int count)\n+{\n+ int i;\n+ for (i = 0; i < count; ++i) {\n+ p[i] = INSN_NOP;\n+ }\n+}\n+\n /* Compute frame size via macros, to share between tcg_target_qemu_prologue\n and tcg_register_jit. */\n \n","prefixes":["PULL","19/23"]}