{"id":811192,"url":"http://patchwork.ozlabs.org/api/1.2/patches/811192/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-6-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170907224051.21518-6-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-07T22:40:33","name":"[PULL,05/23] tcg/s390: Introduce TCG_REG_TB","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8b6ff4d20ab6803d4cd8b3928a3b20f84731beb5","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170907224051.21518-6-richard.henderson@linaro.org/mbox/","series":[{"id":2073,"url":"http://patchwork.ozlabs.org/api/1.2/series/2073/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2073","date":"2017-09-07T22:40:28","name":"[PULL,01/23] tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h","version":1,"mbox":"http://patchwork.ozlabs.org/series/2073/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/811192/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/811192/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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For odd addresses,\n+ attempt to use an offset from the start of the TB. */\n if ((sval & 1) == 0) {\n ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1;\n if (off == (int32_t)off) {\n tcg_out_insn(s, RIL, LARL, ret, off);\n return;\n }\n+ } else if (USE_REG_TB && !in_prologue) {\n+ ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr;\n+ if (off == sextract64(off, 0, 20)) {\n+ /* This is certain to be an address within TB, and therefore\n+ OFF will be negative; don't try RX_LA. */\n+ tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off);\n+ return;\n+ }\n }\n \n /* If extended immediates are not present, then we may have to issue\n@@ -663,6 +678,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type,\n }\n }\n \n+static void tcg_out_movi(TCGContext *s, TCGType type,\n+ TCGReg ret, tcg_target_long sval)\n+{\n+ tcg_out_movi_int(s, type, ret, sval, false);\n+}\n \n /* Emit a load/store type instruction. Inputs are:\n DATA: The register to be loaded or stored.\n@@ -739,6 +759,13 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs)\n return;\n }\n }\n+ if (USE_REG_TB) {\n+ ptrdiff_t disp = abs - (void *)s->code_gen_ptr;\n+ if (disp == sextract64(disp, 0, 20)) {\n+ tcg_out_ld(s, type, dest, TCG_REG_TB, disp);\n+ return;\n+ }\n+ }\n \n tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff);\n tcg_out_ld(s, type, dest, dest, addr & 0xffff);\n@@ -1690,6 +1717,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n break;\n \n case INDEX_op_goto_tb:\n+ a0 = args[0];\n if (s->tb_jmp_insn_offset) {\n /* branch displacement must be aligned for atomic patching;\n * see if we need to add extra nop before branch\n@@ -1697,21 +1725,34 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,\n if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {\n tcg_out16(s, NOP);\n }\n+ tcg_debug_assert(!USE_REG_TB);\n tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));\n- s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);\n+ s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);\n s->code_ptr += 2;\n } else {\n- /* load address stored at s->tb_jmp_target_addr + args[0] */\n- tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0,\n- s->tb_jmp_target_addr + args[0]);\n+ /* load address stored at s->tb_jmp_target_addr + a0 */\n+ tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB,\n+ s->tb_jmp_target_addr + a0);\n /* and go there */\n- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0);\n+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB);\n+ }\n+ s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s);\n+\n+ /* For the unlinked path of goto_tb, we need to reset\n+ TCG_REG_TB to the beginning of this TB. */\n+ if (USE_REG_TB) {\n+ int ofs = -tcg_current_code_size(s);\n+ assert(ofs == (int16_t)ofs);\n+ tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs);\n }\n- s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s);\n break;\n \n case INDEX_op_goto_ptr:\n- tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, args[0]);\n+ a0 = args[0];\n+ if (USE_REG_TB) {\n+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);\n+ }\n+ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0);\n break;\n \n OP_32_64(ld8u):\n@@ -2476,6 +2517,9 @@ static void tcg_target_init(TCGContext *s)\n /* XXX many insns can't be used with R0, so we better avoid it for now */\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0);\n tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);\n+ if (USE_REG_TB) {\n+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB);\n+ }\n }\n \n #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \\\n@@ -2496,12 +2540,17 @@ static void tcg_target_qemu_prologue(TCGContext *s)\n \n #ifndef CONFIG_SOFTMMU\n if (guest_base >= 0x80000) {\n- tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);\n+ tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true);\n tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);\n }\n #endif\n \n tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);\n+ if (USE_REG_TB) {\n+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB,\n+ tcg_target_call_iarg_regs[1]);\n+ }\n+\n /* br %r3 (go to TB) */\n tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);\n \n","prefixes":["PULL","05/23"]}