{"id":810716,"url":"http://patchwork.ozlabs.org/api/1.2/patches/810716/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-33-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-33-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:06:12","name":"[PULL,32/32] target/arm: Perform per-insn cross-page check only for Thumb","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"6bb1f8c249900826b1f93011aa3f4b8c5efe455f","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-33-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/1.2/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810716/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810716/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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Cota \nSigned-off-by: Richard Henderson \n---\n target/arm/translate.c | 58 ++++++++++++++++++++++++++++----------------------\n 1 file changed, 33 insertions(+), 25 deletions(-)","diff":"diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 9e7bfbcf0c..6946e56a3a 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11888,6 +11888,13 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,\n max_insns = 1;\n }\n \n+ /* ARM is a fixed-length ISA. Bound the number of insns to execute\n+ to those left on the page. */\n+ if (!dc->thumb) {\n+ int bound = (dc->next_page_start - dc->base.pc_first) / 4;\n+ max_insns = MIN(max_insns, bound);\n+ }\n+\n cpu_F0s = tcg_temp_new_i32();\n cpu_F1s = tcg_temp_new_i32();\n cpu_F0d = tcg_temp_new_i64();\n@@ -12015,34 +12022,12 @@ static bool arm_pre_translate_insn(DisasContext *dc)\n return false;\n }\n \n-static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc)\n+static void arm_post_translate_insn(DisasContext *dc)\n {\n if (dc->condjmp && !dc->base.is_jmp) {\n gen_set_label(dc->condlabel);\n dc->condjmp = 0;\n }\n-\n- /* Translation stops when a conditional branch is encountered.\n- * Otherwise the subsequent code could get translated several times.\n- * Also stop translation when a page boundary is reached. This\n- * ensures prefetch aborts occur at the right place.\n- *\n- * We want to stop the TB if the next insn starts in a new page,\n- * or if it spans between this page and the next. This means that\n- * if we're looking at the last halfword in the page we need to\n- * see if it's a 16-bit Thumb insn (which will fit in this TB)\n- * or a 32-bit Thumb insn (which won't).\n- * This is to avoid generating a silly TB with a single 16-bit insn\n- * in it at the end of this page (which would execute correctly\n- * but isn't very efficient).\n- */\n- if (dc->base.is_jmp == DISAS_NEXT\n- && (dc->pc >= dc->next_page_start\n- || (dc->pc >= dc->next_page_start - 3\n- && insn_crosses_page(env, dc)))) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- }\n-\n dc->base.pc_next = dc->pc;\n translator_loop_temp_check(&dc->base);\n }\n@@ -12061,7 +12046,10 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n dc->pc += 4;\n disas_arm_insn(dc, insn);\n \n- arm_post_translate_insn(env, dc);\n+ arm_post_translate_insn(dc);\n+\n+ /* ARM is a fixed-length ISA. We performed the cross-page check\n+ in init_disas_context by adjusting max_insns. */\n }\n \n static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n@@ -12085,7 +12073,27 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n }\n }\n \n- arm_post_translate_insn(env, dc);\n+ arm_post_translate_insn(dc);\n+\n+ /* Thumb is a variable-length ISA. Stop translation when the next insn\n+ * will touch a new page. This ensures that prefetch aborts occur at\n+ * the right place.\n+ *\n+ * We want to stop the TB if the next insn starts in a new page,\n+ * or if it spans between this page and the next. This means that\n+ * if we're looking at the last halfword in the page we need to\n+ * see if it's a 16-bit Thumb insn (which will fit in this TB)\n+ * or a 32-bit Thumb insn (which won't).\n+ * This is to avoid generating a silly TB with a single 16-bit insn\n+ * in it at the end of this page (which would execute correctly\n+ * but isn't very efficient).\n+ */\n+ if (dc->base.is_jmp == DISAS_NEXT\n+ && (dc->pc >= dc->next_page_start\n+ || (dc->pc >= dc->next_page_start - 3\n+ && insn_crosses_page(env, dc)))) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n }\n \n static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n","prefixes":["PULL","32/32"]}