{"id":810715,"url":"http://patchwork.ozlabs.org/api/1.2/patches/810715/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-20-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-20-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:05:59","name":"[PULL,19/32] target/arm: [tcg] Port to insn_start","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"4cd062887067a4add69775d46c0d21ba63469655","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-20-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/1.2/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810715/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810715/checks/","tags":{},"related":[],"headers":{"Return-Path":"<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::229","Subject":"[Qemu-devel] [PULL 19/32] target/arm: [tcg] Port to insn_start","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"<qemu-devel.nongnu.org>","List-Unsubscribe":"<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>","List-Archive":"<http://lists.nongnu.org/archive/html/qemu-devel/>","List-Post":"<mailto:qemu-devel@nongnu.org>","List-Help":"<mailto:qemu-devel-request@nongnu.org?subject=help>","List-Subscribe":"<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t<vilanova@ac.upc.edu>, \tRichard Henderson <rth@twiddle.net>","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>"},"content":"From: Lluís Vilanova <vilanova@ac.upc.edu>\n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova <vilanova@ac.upc.edu>\nReviewed-by: Richard Henderson <rth@twiddle.net>\nReviewed-by: Alex Benneé <alex.benee@linaro.org>\nMessage-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.c | 15 +++++++++++----\n 1 file changed, 11 insertions(+), 4 deletions(-)","diff":"diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 3138a23e0c..005157225c 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11936,6 +11936,16 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)\n     }\n }\n \n+static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n+{\n+    DisasContext *dc = container_of(dcbase, DisasContext, base);\n+\n+    dc->insn_start_idx = tcg_op_buf_count();\n+    tcg_gen_insn_start(dc->pc,\n+                       (dc->condexec_cond << 4) | (dc->condexec_mask >> 1),\n+                       0);\n+}\n+\n /* generate intermediate code for basic block 'tb'.  */\n void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n {\n@@ -11979,10 +11989,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n \n     do {\n         dc->base.num_insns++;\n-        dc->insn_start_idx = tcg_op_buf_count();\n-        tcg_gen_insn_start(dc->pc,\n-                           (dc->condexec_cond << 4) | (dc->condexec_mask >> 1),\n-                           0);\n+        arm_tr_insn_start(&dc->base, cs);\n \n         if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n             CPUBreakpoint *bp;\n","prefixes":["PULL","19/32"]}