{"id":810708,"url":"http://patchwork.ozlabs.org/api/1.2/patches/810708/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-29-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-29-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:06:08","name":"[PULL,28/32] target/arm: [tcg] Port to generic translation framework","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9c56ba5499e22dc19429f78fdb7753f90b208c82","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-29-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/1.2/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810708/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810708/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::231","Subject":"[Qemu-devel] [PULL 28/32] target/arm: [tcg] Port to generic\n\ttranslation framework","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t, \tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Lluís Vilanova \n\nTested-by: Emilio G. Cota \nReviewed-by: Emilio G. Cota \nSigned-off-by: Lluís Vilanova \nMessage-Id: <150002631325.22386.10348327185029496649.stgit@frigg.lan>\nSigned-off-by: Richard Henderson \n---\n target/arm/translate.h | 8 +---\n target/arm/translate-a64.c | 107 ++++++++------------------------------------\n target/arm/translate.c | 109 +++++++++------------------------------------\n 3 files changed, 41 insertions(+), 183 deletions(-)","diff":"diff --git a/target/arm/translate.h b/target/arm/translate.h\nindex e8dcec51ac..55d691db40 100644\n--- a/target/arm/translate.h\n+++ b/target/arm/translate.h\n@@ -150,21 +150,15 @@ static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)\n \n #ifdef TARGET_AARCH64\n void a64_translate_init(void);\n-void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu,\n- TranslationBlock *tb);\n void gen_a64_set_pc_im(uint64_t val);\n void aarch64_cpu_dump_state(CPUState *cs, FILE *f,\n fprintf_function cpu_fprintf, int flags);\n+extern const TranslatorOps aarch64_translator_ops;\n #else\n static inline void a64_translate_init(void)\n {\n }\n \n-static inline void gen_intermediate_code_a64(DisasContextBase *db, CPUState *cpu,\n- TranslationBlock *tb)\n-{\n-}\n-\n static inline void gen_a64_set_pc_im(uint64_t val)\n {\n }\ndiff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c\nindex 1973a36462..25c6622825 100644\n--- a/target/arm/translate-a64.c\n+++ b/target/arm/translate-a64.c\n@@ -11262,6 +11262,11 @@ static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,\n return max_insns;\n }\n \n+static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)\n+{\n+ tcg_clear_temp_count();\n+}\n+\n static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n {\n DisasContext *dc = container_of(dcbase, DisasContext, base);\n@@ -11325,6 +11330,7 @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n }\n \n dc->base.pc_next = dc->pc;\n+ translator_loop_temp_check(&dc->base);\n }\n \n static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n@@ -11391,6 +11397,9 @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n break;\n }\n }\n+\n+ /* Functions above can change dc->pc, so re-align db->pc_next */\n+ dc->base.pc_next = dc->pc;\n }\n \n static void aarch64_tr_disas_log(const DisasContextBase *dcbase,\n@@ -11403,92 +11412,12 @@ static void aarch64_tr_disas_log(const DisasContextBase *dcbase,\n 4 | (bswap_code(dc->sctlr_b) ? 2 : 0));\n }\n \n-void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,\n- TranslationBlock *tb)\n-{\n- DisasContext *dc = container_of(dcbase, DisasContext, base);\n- int max_insns;\n-\n- dc->base.tb = tb;\n- dc->base.pc_first = dc->base.tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.num_insns = 0;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n-\n- max_insns = dc->base.tb->cflags & CF_COUNT_MASK;\n- if (max_insns == 0) {\n- max_insns = CF_COUNT_MASK;\n- }\n- if (max_insns > TCG_MAX_INSNS) {\n- max_insns = TCG_MAX_INSNS;\n- }\n- max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);\n-\n- gen_tb_start(tb);\n-\n- tcg_clear_temp_count();\n-\n- do {\n- dc->base.num_insns++;\n- aarch64_tr_insn_start(&dc->base, cs);\n-\n- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n- CPUBreakpoint *bp;\n- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->base.pc_next) {\n- if (aarch64_tr_breakpoint_check(&dc->base, cs, bp)) {\n- break;\n- }\n- }\n- }\n- if (dc->base.is_jmp > DISAS_TOO_MANY) {\n- break;\n- }\n- }\n-\n- if (dc->base.num_insns == max_insns && (dc->base.tb->cflags & CF_LAST_IO)) {\n- gen_io_start();\n- }\n-\n- aarch64_tr_translate_insn(&dc->base, cs);\n-\n- if (tcg_check_temp_count()) {\n- fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n- dc->pc);\n- }\n-\n- if (!dc->base.is_jmp && (tcg_op_buf_full() || cs->singlestep_enabled ||\n- singlestep || dc->base.num_insns >= max_insns)) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- }\n-\n- /* Translation stops when a conditional branch is encountered.\n- * Otherwise the subsequent code could get translated several times.\n- * Also stop translation when a page boundary is reached. This\n- * ensures prefetch aborts occur at the right place.\n- */\n- } while (!dc->base.is_jmp);\n-\n- if (dc->base.tb->cflags & CF_LAST_IO) {\n- gen_io_end();\n- }\n-\n- aarch64_tr_tb_stop(&dc->base, cs);\n-\n- gen_tb_end(tb, dc->base.num_insns);\n-\n- dc->base.tb->size = dc->pc - dc->base.pc_first;\n- dc->base.tb->icount = dc->base.num_insns;\n-\n-#ifdef DEBUG_DISAS\n- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&\n- qemu_log_in_addr_range(dc->base.pc_first)) {\n- qemu_log_lock();\n- qemu_log(\"----------------\\n\");\n- aarch64_tr_disas_log(&dc->base, cs);\n- qemu_log(\"\\n\");\n- qemu_log_unlock();\n- }\n-#endif\n-}\n+const TranslatorOps aarch64_translator_ops = {\n+ .init_disas_context = aarch64_tr_init_disas_context,\n+ .tb_start = aarch64_tr_tb_start,\n+ .insn_start = aarch64_tr_insn_start,\n+ .breakpoint_check = aarch64_tr_breakpoint_check,\n+ .translate_insn = aarch64_tr_translate_insn,\n+ .tb_stop = aarch64_tr_tb_stop,\n+ .disas_log = aarch64_tr_disas_log,\n+};\ndiff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 2dca196e17..dabd5eb89a 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11936,6 +11936,7 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)\n tcg_gen_movi_i32(tmp, 0);\n store_cpu_field(tmp, condexec_bits);\n }\n+ tcg_clear_temp_count();\n }\n \n static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n@@ -12055,6 +12056,7 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n }\n \n dc->base.pc_next = dc->pc;\n+ translator_loop_temp_check(&dc->base);\n }\n \n static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n@@ -12169,6 +12171,9 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n gen_goto_tb(dc, 1, dc->pc);\n }\n }\n+\n+ /* Functions above can change dc->pc, so re-align db->pc_next */\n+ dc->base.pc_next = dc->pc;\n }\n \n static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)\n@@ -12180,99 +12185,29 @@ static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)\n dc->thumb | (dc->sctlr_b << 1));\n }\n \n+static const TranslatorOps arm_translator_ops = {\n+ .init_disas_context = arm_tr_init_disas_context,\n+ .tb_start = arm_tr_tb_start,\n+ .insn_start = arm_tr_insn_start,\n+ .breakpoint_check = arm_tr_breakpoint_check,\n+ .translate_insn = arm_tr_translate_insn,\n+ .tb_stop = arm_tr_tb_stop,\n+ .disas_log = arm_tr_disas_log,\n+};\n+\n /* generate intermediate code for basic block 'tb'. */\n-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)\n {\n- DisasContext dc1, *dc = &dc1;\n- int max_insns;\n-\n- /* generate intermediate code */\n+ DisasContext dc;\n+ const TranslatorOps *ops = &arm_translator_ops;\n \n- /* The A64 decoder has its own top level loop, because it doesn't need\n- * the A32/T32 complexity to do with conditional execution/IT blocks/etc.\n- */\n+#ifdef TARGET_AARCH64\n if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {\n- gen_intermediate_code_a64(&dc->base, cs, tb);\n- return;\n- }\n-\n- dc->base.tb = tb;\n- dc->base.pc_first = dc->base.tb->pc;\n- dc->base.pc_next = dc->base.pc_first;\n- dc->base.is_jmp = DISAS_NEXT;\n- dc->base.num_insns = 0;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n-\n- max_insns = tb->cflags & CF_COUNT_MASK;\n- if (max_insns == 0) {\n- max_insns = CF_COUNT_MASK;\n- }\n- if (max_insns > TCG_MAX_INSNS) {\n- max_insns = TCG_MAX_INSNS;\n- }\n- max_insns = arm_tr_init_disas_context(&dc->base, cs, max_insns);\n-\n- gen_tb_start(tb);\n-\n- tcg_clear_temp_count();\n- arm_tr_tb_start(&dc->base, cs);\n-\n- do {\n- dc->base.num_insns++;\n- arm_tr_insn_start(&dc->base, cs);\n-\n- if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n- CPUBreakpoint *bp;\n- QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n- if (bp->pc == dc->base.pc_next) {\n- if (arm_tr_breakpoint_check(&dc->base, cs, bp)) {\n- break;\n- }\n- }\n- }\n- if (dc->base.is_jmp > DISAS_TOO_MANY) {\n- break;\n- }\n- }\n-\n- if (dc->base.num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n- gen_io_start();\n- }\n-\n- arm_tr_translate_insn(&dc->base, cs);\n-\n- if (tcg_check_temp_count()) {\n- fprintf(stderr, \"TCG temporary leak before \"TARGET_FMT_lx\"\\n\",\n- dc->pc);\n- }\n-\n- if (!dc->base.is_jmp && (tcg_op_buf_full() || singlestep ||\n- dc->base.num_insns >= max_insns)) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- }\n- } while (!dc->base.is_jmp);\n-\n- if (dc->base.tb->cflags & CF_LAST_IO) {\n- gen_io_end();\n- }\n-\n- arm_tr_tb_stop(&dc->base, cs);\n-\n- gen_tb_end(tb, dc->base.num_insns);\n-\n- tb->size = dc->pc - dc->base.pc_first;\n- tb->icount = dc->base.num_insns;\n-\n-#ifdef DEBUG_DISAS\n- if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&\n- qemu_log_in_addr_range(dc->base.pc_first)) {\n- qemu_log_lock();\n- qemu_log(\"----------------\\n\");\n- arm_tr_disas_log(&dc->base, cs);\n- qemu_log(\"\\n\");\n- qemu_log_unlock();\n+ ops = &aarch64_translator_ops;\n }\n #endif\n+\n+ translator_loop(ops, &dc.base, cpu, tb);\n }\n \n static const char *cpu_mode_names[16] = {\n","prefixes":["PULL","28/32"]}