{"id":810701,"url":"http://patchwork.ozlabs.org/api/1.2/patches/810701/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-11-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-11-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:05:50","name":"[PULL,10/32] target/i386: [tcg] Port to breakpoint_check","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"82e777e63cca3e2160bca77c02282a0635959ff5","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-11-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/1.2/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810701/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810701/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c00::233","Subject":"[Qemu-devel] [PULL 10/32] target/i386: [tcg] Port to\n\tbreakpoint_check","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t, \tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Lluís Vilanova \n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nSigned-off-by: Lluís Vilanova \nReviewed-by: Richard Henderson \nReviewed-by: Emilio G. Cota \nMessage-Id: <150002170871.22386.2172835658104140576.stgit@frigg.lan>\nSigned-off-by: Richard Henderson \n---\n target/i386/translate.c | 46 ++++++++++++++++++++++++++++++++++------------\n 1 file changed, 34 insertions(+), 12 deletions(-)","diff":"diff --git a/target/i386/translate.c b/target/i386/translate.c\nindex b7e5854513..4d4083fe30 100644\n--- a/target/i386/translate.c\n+++ b/target/i386/translate.c\n@@ -8456,6 +8456,26 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)\n tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);\n }\n \n+static bool i386_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,\n+ const CPUBreakpoint *bp)\n+{\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ /* If RF is set, suppress an internally generated breakpoint. */\n+ int flags = dc->base.tb->flags & HF_RF_MASK ? BP_GDB : BP_ANY;\n+ if (bp->flags & flags) {\n+ gen_debug(dc, dc->base.pc_next - dc->cs_base);\n+ dc->base.is_jmp = DISAS_NORETURN;\n+ /* The address covered by the breakpoint must be included in\n+ [tb->pc, tb->pc + tb->size) in order to for it to be\n+ properly cleared -- thus we increment the PC here so that\n+ the logic setting tb->size below does the right thing. */\n+ dc->base.pc_next += 1;\n+ return true;\n+ } else {\n+ return false;\n+ }\n+}\n+\n /* generate intermediate code for basic block 'tb'. */\n void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n {\n@@ -8486,18 +8506,21 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n i386_tr_insn_start(&dc->base, cs);\n num_insns++;\n \n- /* If RF is set, suppress an internally generated breakpoint. */\n- if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next,\n- tb->flags & HF_RF_MASK\n- ? BP_GDB : BP_ANY))) {\n- gen_debug(dc, dc->base.pc_next - dc->cs_base);\n- /* The address covered by the breakpoint must be included in\n- [tb->pc, tb->pc + tb->size) in order to for it to be\n- properly cleared -- thus we increment the PC here so that\n- the logic setting tb->size below does the right thing. */\n- dc->base.pc_next += 1;\n- goto done_generating;\n+ if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {\n+ CPUBreakpoint *bp;\n+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {\n+ if (bp->pc == dc->base.pc_next) {\n+ if (i386_tr_breakpoint_check(&dc->base, cs, bp)) {\n+ break;\n+ }\n+ }\n+ }\n+\n+ if (dc->base.is_jmp == DISAS_NORETURN) {\n+ break;\n+ }\n }\n+\n if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {\n gen_io_start();\n }\n@@ -8548,7 +8571,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n }\n if (tb->cflags & CF_LAST_IO)\n gen_io_end();\n-done_generating:\n gen_tb_end(tb, num_insns);\n \n #ifdef DEBUG_DISAS\n","prefixes":["PULL","10/32"]}