{"id":810696,"url":"http://patchwork.ozlabs.org/api/1.2/patches/810696/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-9-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170906160612.22769-9-richard.henderson@linaro.org>","list_archive_url":null,"date":"2017-09-06T16:05:48","name":"[PULL,08/32] target/i386: [tcg] Port to init_disas_context","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ebf711f4fbc986d112e92535d3b9a6516b6e8085","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-9-richard.henderson@linaro.org/mbox/","series":[{"id":1847,"url":"http://patchwork.ozlabs.org/api/1.2/series/1847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847","date":"2017-09-06T16:05:41","name":"[PULL,01/32] tcg: Add generic DISAS_NORETURN","version":1,"mbox":"http://patchwork.ozlabs.org/series/1847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/810696/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/810696/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400e:c05::231","Subject":"[Qemu-devel] [PULL 08/32] target/i386: [tcg] Port to\n\tinit_disas_context","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?=\n\t, \tRichard Henderson ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Lluís Vilanova \n\nIncrementally paves the way towards using the generic instruction translation\nloop.\n\nReviewed-by: Emilio G. Cota \nReviewed-by: Richard Henderson \nReviewed-by: Alex Benneé \nSigned-off-by: Lluís Vilanova \nMessage-Id: <150002122448.22386.16854673576827449259.stgit@frigg.lan>\n[rth: Adjust for max_insns interface change.]\nSigned-off-by: Richard Henderson \n---\n target/i386/translate.c | 46 +++++++++++++++++++++++++++-------------------\n 1 file changed, 27 insertions(+), 19 deletions(-)","diff":"diff --git a/target/i386/translate.c b/target/i386/translate.c\nindex 3a3d91c4d7..4281e9bc56 100644\n--- a/target/i386/translate.c\n+++ b/target/i386/translate.c\n@@ -8377,20 +8377,13 @@ void tcg_x86_init(void)\n }\n }\n \n-/* generate intermediate code for basic block 'tb'. */\n-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+static int i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu,\n+ int max_insns)\n {\n- CPUX86State *env = cs->env_ptr;\n- DisasContext dc1, *dc = &dc1;\n- uint32_t flags;\n- target_ulong cs_base;\n- int num_insns;\n- int max_insns;\n-\n- /* generate intermediate code */\n- dc->base.pc_first = tb->pc;\n- cs_base = tb->cs_base;\n- flags = tb->flags;\n+ DisasContext *dc = container_of(dcbase, DisasContext, base);\n+ CPUX86State *env = cpu->env_ptr;\n+ uint32_t flags = dc->base.tb->flags;\n+ target_ulong cs_base = dc->base.tb->cs_base;\n \n dc->pe = (flags >> HF_PE_SHIFT) & 1;\n dc->code32 = (flags >> HF_CS32_SHIFT) & 1;\n@@ -8401,11 +8394,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n dc->cpl = (flags >> HF_CPL_SHIFT) & 3;\n dc->iopl = (flags >> IOPL_SHIFT) & 3;\n dc->tf = (flags >> TF_SHIFT) & 1;\n- dc->base.singlestep_enabled = cs->singlestep_enabled;\n dc->cc_op = CC_OP_DYNAMIC;\n dc->cc_op_dirty = false;\n dc->cs_base = cs_base;\n- dc->base.tb = tb;\n dc->popl_esp_hack = 0;\n /* select memory access functions */\n dc->mem_index = 0;\n@@ -8423,7 +8414,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n dc->code64 = (flags >> HF_CS64_SHIFT) & 1;\n #endif\n dc->flags = flags;\n- dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||\n+ dc->jmp_opt = !(dc->tf || dc->base.singlestep_enabled ||\n (flags & HF_INHIBIT_IRQ_MASK));\n /* Do not optimize repz jumps at all in icount mode, because\n rep movsS instructions are execured with different paths\n@@ -8435,7 +8426,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n record/replay modes and there will always be an\n additional step for ecx=0 when icount is enabled.\n */\n- dc->repz_opt = !dc->jmp_opt && !(tb->cflags & CF_USE_ICOUNT);\n+ dc->repz_opt = !dc->jmp_opt && !(dc->base.tb->cflags & CF_USE_ICOUNT);\n #if 0\n /* check addseg logic */\n if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))\n@@ -8455,9 +8446,24 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n cpu_ptr1 = tcg_temp_new_ptr();\n cpu_cc_srcT = tcg_temp_local_new();\n \n+ return max_insns;\n+}\n+\n+/* generate intermediate code for basic block 'tb'. */\n+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n+{\n+ CPUX86State *env = cs->env_ptr;\n+ DisasContext dc1, *dc = &dc1;\n+ int num_insns;\n+ int max_insns;\n+\n+ /* generate intermediate code */\n+ dc->base.singlestep_enabled = cs->singlestep_enabled;\n+ dc->base.tb = tb;\n dc->base.is_jmp = DISAS_NEXT;\n+ dc->base.pc_first = tb->pc;\n dc->base.pc_next = dc->base.pc_first;\n- num_insns = 0;\n+\n max_insns = tb->cflags & CF_COUNT_MASK;\n if (max_insns == 0) {\n max_insns = CF_COUNT_MASK;\n@@ -8465,7 +8471,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n if (max_insns > TCG_MAX_INSNS) {\n max_insns = TCG_MAX_INSNS;\n }\n+ max_insns = i386_tr_init_disas_context(&dc->base, cs, max_insns);\n \n+ num_insns = 0;\n gen_tb_start(tb);\n for(;;) {\n tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);\n@@ -8498,7 +8506,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)\n the flag and abort the translation to give the irqs a\n change to be happen */\n if (dc->tf || dc->base.singlestep_enabled ||\n- (flags & HF_INHIBIT_IRQ_MASK)) {\n+ (dc->base.tb->flags & HF_INHIBIT_IRQ_MASK)) {\n gen_jmp_im(dc->base.pc_next - dc->cs_base);\n gen_eob(dc);\n break;\n","prefixes":["PULL","08/32"]}