{"id":809915,"url":"http://patchwork.ozlabs.org/api/1.2/patches/809915/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504583864-8169-2-git-send-email-alistair@popple.id.au/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.2/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<1504583864-8169-2-git-send-email-alistair@popple.id.au>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/1504583864-8169-2-git-send-email-alistair@popple.id.au/","date":"2017-09-05T03:57:44","name":"[2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"22637e638e9dc3cb8388614f6f74df4bbbfcf46b","submitter":{"id":24781,"url":"http://patchwork.ozlabs.org/api/1.2/people/24781/?format=json","name":"Alistair Popple","email":"alistair@popple.id.au"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1504583864-8169-2-git-send-email-alistair@popple.id.au/mbox/","series":[{"id":1483,"url":"http://patchwork.ozlabs.org/api/1.2/series/1483/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=1483","date":"2017-09-05T03:57:43","name":"[1/2] powerpc/npu: Use flush_all_mm() instead of flush_tlb_mm()","version":1,"mbox":"http://patchwork.ozlabs.org/series/1483/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809915/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809915/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xmY1104XCz9sNq\n\tfor ;\n\tTue, 5 Sep 2017 14:01:09 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xmY10612QzDrJW\n\tfor ;\n\tTue, 5 Sep 2017 14:01:08 +1000 (AEST)","from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xmXxP3N92zDqYK\n\tfor ;\n\tTue, 5 Sep 2017 13:58:01 +1000 (AEST)","from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xmXxN6g9Gz9sP3;\n\tTue, 5 Sep 2017 13:58:00 +1000 (AEST)"],"From":"Alistair Popple ","To":"linuxppc-dev@lists.ozlabs.org","Subject":"[PATCH 2/2] powerpc/powernv/npu: Don't explicitly flush nmmu tlb","Date":"Tue, 5 Sep 2017 13:57:44 +1000","Message-Id":"<1504583864-8169-2-git-send-email-alistair@popple.id.au>","X-Mailer":"git-send-email 2.1.4","In-Reply-To":"<1504583864-8169-1-git-send-email-alistair@popple.id.au>","References":"<1504583864-8169-1-git-send-email-alistair@popple.id.au>","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"andrew.donnellan@au1.ibm.com, arbab@linux.vnet.ibm.com,\n\tfbarrat@linux.vnet.ibm.com, Alistair Popple ","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"The nest mmu required an explicit flush as a tlbi would not flush it in the\nsame way as the core. However an alternate firmware fix exists which should\neliminate the need for this flush, so instead add a device-tree property\n(ibm,nmmu-flush) on the NVLink2 PHB to enable it only if required.\n\nSigned-off-by: Alistair Popple \n---\n arch/powerpc/platforms/powernv/npu-dma.c | 28 +++++++++++++++++++++++-----\n arch/powerpc/platforms/powernv/pci.h | 3 +++\n 2 files changed, 26 insertions(+), 5 deletions(-)","diff":"diff --git a/arch/powerpc/platforms/powernv/npu-dma.c b/arch/powerpc/platforms/powernv/npu-dma.c\nindex 2fff9a65..4b4fcac 100644\n--- a/arch/powerpc/platforms/powernv/npu-dma.c\n+++ b/arch/powerpc/platforms/powernv/npu-dma.c\n@@ -395,6 +395,7 @@ struct npu_context {\n \tstruct pci_dev *npdev[NV_MAX_NPUS][NV_MAX_LINKS];\n \tstruct mmu_notifier mn;\n \tstruct kref kref;\n+\tbool nmmu_flush;\n \n \t/* Callback to stop translation requests on a given GPU */\n \tstruct npu_context *(*release_cb)(struct npu_context *, void *);\n@@ -545,11 +546,13 @@ static void mmio_invalidate(struct npu_context *npu_context, int va,\n \tstruct mmio_atsd_reg mmio_atsd_reg[NV_MAX_NPUS];\n \tunsigned long pid = npu_context->mm->context.id;\n \n-\t/*\n-\t * Unfortunately the nest mmu does not support flushing specific\n-\t * addresses so we have to flush the whole mm.\n-\t */\n-\tflush_all_mm(npu_context->mm);\n+\tif (npu_context->nmmu_flush)\n+\t\t/*\n+\t\t * Unfortunately the nest mmu does not support flushing specific\n+\t\t * addresses so we have to flush the whole mm once before\n+\t\t * shooting down the GPU translation.\n+\t\t */\n+\t\tflush_all_mm(npu_context->mm);\n \n \t/*\n \t * Loop over all the NPUs this process is active on and launch\n@@ -722,6 +725,16 @@ struct npu_context *pnv_npu2_init_context(struct pci_dev *gpdev,\n \t\treturn ERR_PTR(-ENODEV);\n \tnpu_context->npdev[npu->index][nvlink_index] = npdev;\n \n+\tif (!nphb->npu.nmmu_flush) {\n+\t\t/*\n+\t\t * If we're not explicitly flushing ourselves we need to mark\n+\t\t * the thread for global flushes\n+\t\t */\n+\t\tnpu_context->nmmu_flush = false;\n+\t\tinc_mm_active_cpus(mm);\n+\t} else\n+\t\tnpu_context->nmmu_flush = true;\n+\n \treturn npu_context;\n }\n EXPORT_SYMBOL(pnv_npu2_init_context);\n@@ -731,6 +744,9 @@ static void pnv_npu2_release_context(struct kref *kref)\n \tstruct npu_context *npu_context =\n \t\tcontainer_of(kref, struct npu_context, kref);\n \n+\tif (!npu_context->nmmu_flush)\n+\t\tdec_mm_active_cpus(npu_context->mm);\n+\n \tnpu_context->mm->context.npu_context = NULL;\n \tmmu_notifier_unregister(&npu_context->mn,\n \t\t\t\tnpu_context->mm);\n@@ -819,6 +835,8 @@ int pnv_npu2_init(struct pnv_phb *phb)\n \tstatic int npu_index;\n \tuint64_t rc = 0;\n \n+\tphb->npu.nmmu_flush =\n+\t\tof_property_read_bool(phb->hose->dn, \"ibm,nmmu-flush\");\n \tfor_each_child_of_node(phb->hose->dn, dn) {\n \t\tgpdev = pnv_pci_get_gpu_dev(get_pci_dev(dn));\n \t\tif (gpdev) {\ndiff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h\nindex a95273c..22025c6 100644\n--- a/arch/powerpc/platforms/powernv/pci.h\n+++ b/arch/powerpc/platforms/powernv/pci.h\n@@ -187,6 +187,9 @@ struct pnv_phb {\n \n \t\t/* Bitmask for MMIO register usage */\n \t\tunsigned long mmio_atsd_usage;\n+\n+\t\t/* Do we need to explicitly flush the nest mmu? */\n+\t\tbool nmmu_flush;\n \t} npu;\n \n #ifdef CONFIG_CXL_BASE\n","prefixes":["2/2"]}