{"id":809597,"url":"http://patchwork.ozlabs.org/api/1.2/patches/809597/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/20170904104655.29103-2-ran.wang_1@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170904104655.29103-2-ran.wang_1@nxp.com>","list_archive_url":null,"date":"2017-09-04T10:46:48","name":"[U-Boot,v5,2/9] armv8: Add workaround for USB erratum A-009008","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"70fc6714acbc7ab65a35857363e089e6b8c6d71d","submitter":{"id":71939,"url":"http://patchwork.ozlabs.org/api/1.2/people/71939/?format=json","name":"Ran Wang","email":"ran.wang_1@nxp.com"},"delegate":{"id":2666,"url":"http://patchwork.ozlabs.org/api/1.2/users/2666/?format=json","username":"yorksun","first_name":"York","last_name":"Sun","email":"yorksun@freescale.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/20170904104655.29103-2-ran.wang_1@nxp.com/mbox/","series":[{"id":1355,"url":"http://patchwork.ozlabs.org/api/1.2/series/1355/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=1355","date":"2017-09-04T10:46:47","name":"[U-Boot,v5,1/9] armv8: Add scfg_clrsetbits_32(), scfg_clrbits_32()","version":5,"mbox":"http://patchwork.ozlabs.org/series/1355/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809597/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809597/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","spf=fail (sender IP is 192.88.158.2)\n\tsmtp.mailfrom=nxp.com; nxp.com; dkim=none (message not signed)\n\theader.d=none;nxp.com; dmarc=fail action=none header.from=nxp.com;"],"Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xm6SW3ffNz9s8J\n\tfor ;\n\tMon, 4 Sep 2017 21:04:59 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid 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\n\tclient-ip=192.88.158.2; helo=az84smr01.freescale.net;","From":"Ran Wang ","To":"open list , York Sun ","Date":"Mon, 4 Sep 2017 18:46:48 +0800","Message-ID":"<20170904104655.29103-2-ran.wang_1@nxp.com>","X-Mailer":"git-send-email 2.14.1","In-Reply-To":"<20170904104655.29103-1-ran.wang_1@nxp.com>","References":"<20170904104655.29103-1-ran.wang_1@nxp.com>","X-EOPAttributedMessage":"0","X-Matching-Connectors":"131489966547922317;\n\t(91ab9b29-cfa4-454e-5278-08d120cd25b8); ()","X-Forefront-Antispam-Report":"CIP:192.88.158.2; IPV:NLI; CTRY:US; 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BN3PR03MB2259;\n\t3:grypfy/jxUGb5px/4xFbeiSiMKZ05NQYMsBPch5YVnezwlBi2re4QzPFXZwQYBYW3DpRbwuuZuvjeCYUeMamNo8uqwb5daZBe6/L7wIg+OTqziA2D4XH4pYHsB2YNkuRghHtv0KHiHVfZpQSO1iA3q3lmwmfPMQYvB26cqqBNQ3NyD+QUIdpGxwx23IsgIPd6nV8Bzfe1CsKK9YzENDUEqkeaKwoTUMeSDZ+JG9pRQqLM8l/q+3EehiTZGbWkAUDlNEILTq94ryv0OqTTjauKu2Ai0meRrIdpxV4XOQcG04+Nhxosf6MfqVW5KFl+5EAkibJP6JBva0Nx+86laLIRQ==;\n\t25:+CVoSIlimiTFbfjzAljx1iM0tx57e2QPlRGxhi3PCqPvH+evJIpybGF00XDJ/6WvwjExd1CQTjHfqD+aEwsUcjwDh0m6tu5O7Dc+vJ5NJTJndaC0RjZKaDVvaIl+tvPDSZ6nu4rHfvjpoUrE4XSo2FSBvwlqSNhl9xlF+zh66rw+FUKzJCaIuOxnOLZa3YbEaYkiRwP+A+p/beJ2GE2kcfpIS8biHuJWEggPYhcuoVNuHZD00cWxeL0QI7JiNx91t9jvwQxVF107kXA2Orc2MRbBRdbGjZNare5PP7rzKIEF0id33ImSvY1n7Dl2avc8uWfj6d5CVJNjuNzlJHnzNw==;\n\t31:VNrVPR0OA26RrEuMp1FZg3vVVDF5DgQA1cQKKC95h36GeiRkYXkEooJwbRKv1oP0TO6Z6z8SCLEpyVxYP0xl9b8O8virgbntUid1AJjOTmI1fAsmmN5x2O6RTmL5xVje3geiWLiLNCvE1+BDYGGzxZBQAy1XYXQS9sz7t8YZT0kOv1uLMge+Fgc/R2FrkkSL95vYLmpUKLvI1fNEFMH/C542zP75/8OPmmYdUAaz+Ig=","1; BN3PR03MB2259;\n\t4:x3eAqwckd1BK7cl0CjfgsLrwI4YSgbCHd3ksRcXNqv576oOfZN1hgWS7fTwBQWDhCvedSYuCdFchYS/2D8zxqFb1scBZUC/rTbGaHT0YkW/K/EiuueXQznygvuiunZ5tVbPcNmBWHX7jsYwQM+rvJMZHVbnzMIFJnJmTZ2wTeFV3VBimyMsrTuEFhO11RcJHxfXV22ww9Y9K/J0u8jR5m6dJnZfH1lVvmY0bd+R2ZOkTiyd6WSsd2XebL44VLf3z3TUDAHOEzOGHnrGcMBCBIqbRB2gs5cl5S+x0zJW4TFc=","=?us-ascii?Q?1; BN3PR03MB2259;\n\t23:pXK4shocwDfmXg8Owb0ShjQx0jKjBEfhbi9H5VZLF?=\n\txF15soxWocVbAMEKnmw87NFp0cEDp8b7WKY7MDiEXKwVy9lAyysZbtPCUOyGoe8yUSs6HlsRnppAskaQiFem7J5CW6ZpFvTGoC+ZeObypc+RFGM3A0FGTE5GHfX4/uOKHGtoT42qvL2GUf5YEWGTWy3AoSjpOLFJesQWDkfU0MoCXpAUzzjcfpauS0Trr6LmANcuOKdsOU4LH7CN+nGBBV4YSD2D34yRVM0rhiBTtHCFfUIQ/UHBOjH4jJu8wIFNaYdNChf26JlWUlBnFQWhypi8zkrTgF+yrLOFpbT7uUrX4gprClDlQAWPzB26R/dr5XmQHN1HRe5kKQ437GklPyHz73sPmtDGRll0TE5jT6+0TOk7QMRkoGay+V6ad1aNo7bTvLRiSlR85vs2Tqz2dvIhmMw2snJDD2paMuFlr/GB/CE10YUOnKnV85V3llxSPLt0heHGb8XkPbiGgA5laJ/oZbeCC40/kAUeW+cg/YWpAPpc43CfzeKYUPch4NRZ+q6IIBbehAJKRp3NMsWU/9bduP4r37jFyYZnw7gUJR3wZFCcrX1cH+7cX84kshCWS57T4zQkggR2ToDUKeK72znxMEaq7Rrgffqt2QDp6Uw9hpi6BsPGEzs1qTi80H74clcr4lmwQYGwKbVSL2ZD48pPrfcVGJzPvDn/vRQBSEXD2jOv6biEYw1peXrLFbSAvFjapk0xQLeKlYvhYkE1prCPkAWrX49OWxesx2Tx+TBh3vRUqpPJqjghO5Fr1CyeTbeVERcTO7XItfmdcSudy6+pAwBam2HWsLS49BDkILbQHwIAtpcjMXfHhXyZArBpeptr9WzHipnjCZ75bJa+K4FmGFl1YhZ6rld6khWeqqa15KvKGa/qWRgsK7UP3DA1TH5kY+FJJQWGM9qAEPFKvoxhMbZ5lkAvUUj5mi3JsHPacE4mbJ5Gbpxz3seNMQGuGedh1M0TLkAqvAVSC9nfhfzUL5WbJqzIgObagHItoVVTmrVvVbaN8ghCuyWxOWepqyVojkftGI1pr+MVi324OdGVWcCxsmPU1HHOKkEK+3dtv8gXcRDa+tYuM0jWAAOI1Tf/w1oEiXRBDKnU8c56tqhLNPY5Ain7HUKjNtdPWdS+yvEn2kEIZ8/acNXPSSxCrM=","1; BN3PR03MB2259;\n\t6:zB7VXlM/PG+iO6i3TSdDbfp/VEQm1KJi4yBMFbb2pAakRXQR6gi1QzIBf/vWLNdpWQ5I5ezqEv/DGA7W/TtAZf9BzmR0H1S7YeiGIWs9TdhBRUA4TNZ2XI6WISirxgWNK4zA6LO4EYFatc39qcyJqwx2HskImXCIvjSBVMtxN3drmjM+mD/dAwEpGM9/TyBfvmKPEFxrT05lTGv6HRN/Mz1MmdYv0K4rSBKDz1nrqsUpHc7aY5XZrXx2Q9lkx9Y/iY1wQrwtXd6g9SrXf7qDId/ttPEDscJqlwOuinjkR3JxAi4Omc8n25K3XoqRRTRDE/UUy6/6eiFicyo3Ll0LPw==;\n\t5:WoRwZ9nM4GW/LndDio6F8heTooYIXiNc0d3DTMCQgKCKo6GTC0quwhpfZkjue2pIz+rf4r+8qJ3zwqbw5fGnaL7lQPDY8UX+l5z9Fd+kKm0f1o8f+hxiOfX4DSoniIrMA3fAYmHqxix55o6J3dwJ91k0r6az134tFTMMeDzwIiw=;\n\t24:eRY2armrF1/vua5mUux3wj7VmoQv/oSQYCcMeePhOJCqsLYmXDWgD0FuTGqbhHHRbgG/URihOus8d8xkYlc/keDsOq52XsJeZKyRYkfIbdg=;\n\t7:uQdFk1OvqBx9zc3nIKGSHKYMP9NY0K2bt6zd12qYA2D+eM5Tey3oR2Eif0db+P7YF6TsoCvstibCCspHf1Rqzo/WCk6KEZwLAD8wcx0ea/qQZSfrasQlbUNWaEzaVpKwyOtvQQCv8mHGmgrubiUwxkt0mLNWCvDYENnADwGCwtNT3Pk9bo2StXNkiVHcKB5vNCfZSGbTRBN8Gj0ynfgXUYzoaGMiS750NOLMoO9fV0g="],"MIME-Version":"1.0","X-MS-PublicTrafficType":"Email","X-MS-Office365-Filtering-Correlation-Id":"0706644a-1845-414b-e285-08d4f384ae01","X-Microsoft-Antispam":"UriScan:; BCL:0; PCL:0;\n\tRULEID:(300000500095)(300135000095)(300000501095)(300135300095)(300000502095)(300135100095)(22001)(300000503095)(300135400095)(2017052603199)(201703131430075)(201703131517081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);\n\tSRVR:BN3PR03MB2259; ","X-MS-TrafficTypeDiagnostic":"BN3PR03MB2259:","X-Exchange-Antispam-Report-Test":"UriScan:(185117386973197);","X-Microsoft-Antispam-PRVS":"","X-Exchange-Antispam-Report-CFA-Test":"BCL:0; PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6095135)(2401047)(8121501046)(5005006)(3002001)(10201501046)(93006095)(93001095)(100000703101)(100105400095)(6055026)(6096035)(20161123563025)(20161123565025)(20161123559100)(201703131430075)(201703131433075)(201703131448075)(201703161259150)(201703151042153)(20161123556025)(20161123561025)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:BN3PR03MB2259; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(400006)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BN3PR03MB2259; ","X-Forefront-PRVS":"0420213CCD","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"04 Sep 2017 11:04:14.5582\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.158.2]; \n\tHelo=[az84smr01.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BN3PR03MB2259","Cc":"Priyanka Jain ,\n\tSuresh Gupta , ran.wang_1@nxp.com","Subject":"[U-Boot] [PATCH v5 2/9] armv8: Add workaround for USB erratum\n\tA-009008","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"USB High Speed (HS) EYE Height Adjustment\nUSB HS speed eye diagram fails with the default value at\nmany corners, particularly at a high temperature\n\nOptimal eye at TXREFTUNE value to 0x9 is observed, change\nset the same value.\n\nSigned-off-by: Ran Wang \n---\nChange in v5:\n\tUse scfg_clrsetbits32() instead.\n\nChange in v4:\n\tChange 1001 to 0x9 in the commit message to match the code.\n\tClean up the math in set_usb_txvreftune().\n\tRename USB_TXVREFTUNE to SCFG_USB_TXVREFTUNE.\n\nChange in v3:\n\tUse inline function to make code cleaner.\n\nChange in v2:\n\tIn function erratum_a009008():\n\t1.Put a blank line after variable declaration.\n\t2.Move common code together.\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 23 ++++++++++++++++++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +\n 4 files changed, 37 insertions(+)","diff":"diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex cdeef26fe5..d8936a4334 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -22,6 +22,7 @@ config ARCH_LS1043A\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010315\n \tselect SYS_FSL_ERRATUM_A010539\n+\tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_HAS_DDR3\n \tselect SYS_FSL_HAS_DDR4\n \tselect ARCH_EARLY_INIT_R\n@@ -44,6 +45,7 @@ config ARCH_LS1046A\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010165\n \tselect SYS_FSL_ERRATUM_A010539\n+\tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_HAS_DDR4\n \tselect SYS_FSL_SRDS_2\n \tselect ARCH_EARLY_INIT_R\n@@ -80,6 +82,7 @@ config ARCH_LS2080A\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010165\n \tselect SYS_FSL_ERRATUM_A009203\n+\tselect SYS_FSL_ERRATUM_A009008\n \tselect ARCH_EARLY_INIT_R\n \tselect BOARD_EARLY_INIT_F\n \n@@ -223,6 +226,10 @@ config SYS_FSL_ERRATUM_A010315\n config SYS_FSL_ERRATUM_A010539\n \tbool \"Workaround for PIN MUX erratum A010539\"\n \n+config SYS_FSL_ERRATUM_A009008\n+\tbool \"Workaround for USB PHY erratum A009008\"\n+\n+\n config MAX_CPUS\n \tint \"Maximum number of CPUs permitted for Layerscape\"\n \tdefault 4 if ARCH_LS1043A\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex 639e9d2ddc..ea71fa0dc7 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -52,6 +52,27 @@ bool soc_has_aiop(void)\n \treturn false;\n }\n \n+static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)\n+{\n+\tscfg_clrsetbits32(scfg + offset / 4,\n+\t\t\t0xF << 6,\n+\t\t\tSCFG_USB_TXVREFTUNE << 6);\n+}\n+\n+static void erratum_a009008(void)\n+{\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008\n+\tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);\n+\tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);\n+\tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR);\n+#endif\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */\n+}\n+\n #if defined(CONFIG_FSL_LSCH3)\n /*\n * This erratum requires setting a value to eddrtqcr1 to\n@@ -198,6 +219,7 @@ void fsl_lsch3_early_init_f(void)\n #endif\n \terratum_a008514();\n \terratum_a008336();\n+\terratum_a009008();\n #ifdef CONFIG_CHAIN_OF_TRUST\n \t/* In case of Secure Boot, the IBR configures the SMMU\n \t* to allow only Secure transactions.\n@@ -473,6 +495,7 @@ void fsl_lsch2_early_init_f(void)\n \terratum_a009929();\n \terratum_a009660();\n \terratum_a010539();\n+\terratum_a009008();\n }\n #endif\n \ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\nindex 4afc338b8e..c60d8ddfa2 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n@@ -338,6 +338,12 @@ struct ccsr_gur {\n #define SCFG_USBPWRFAULT_USB2_SHIFT\t2\n #define SCFG_USBPWRFAULT_USB1_SHIFT\t0\n \n+#define SCFG_BASE\t\t\t0x01570000\n+#define SCFG_USB3PRM1CR_USB1\t\t0x070\n+#define SCFG_USB3PRM1CR_USB2\t\t0x07C\n+#define SCFG_USB3PRM1CR_USB3\t\t0x088\n+#define SCFG_USB_TXVREFTUNE\t\t\t0x9\n+\n #define SCFG_SNPCNFGCR_SECRDSNP\t\t0x80000000\n #define SCFG_SNPCNFGCR_SECWRSNP\t\t0x40000000\n #define SCFG_SNPCNFGCR_SATARDSNP\t0x00800000\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 59410aa7e7..01b24d03f1 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -133,6 +133,7 @@\n #define SCFG_BASE\t\t0x01fc0000\n #define SCFG_USB3PRM1CR\t\t\t0x000\n #define SCFG_USB3PRM1CR_INIT\t\t0x27672b2a\n+#define SCFG_USB_TXVREFTUNE\t\t0x9\n #define SCFG_QSPICLKCTLR\t0x10\n \n #define TP_ITYP_AV\t\t0x00000001\t/* Initiator available */\n","prefixes":["U-Boot","v5","2/9"]}