{"id":809583,"url":"http://patchwork.ozlabs.org/api/1.2/patches/809583/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1504520045-23739-1-git-send-email-sriram.dash@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504520045-23739-1-git-send-email-sriram.dash@nxp.com>","list_archive_url":null,"date":"2017-09-04T10:14:05","name":"[U-Boot] armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"062b3dd03fb28c447bbc9295ac4f1700d07bb61c","submitter":{"id":68400,"url":"http://patchwork.ozlabs.org/api/1.2/people/68400/?format=json","name":"Sriram Dash","email":"sriram.dash@nxp.com"},"delegate":{"id":2666,"url":"http://patchwork.ozlabs.org/api/1.2/users/2666/?format=json","username":"yorksun","first_name":"York","last_name":"Sun","email":"yorksun@freescale.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1504520045-23739-1-git-send-email-sriram.dash@nxp.com/mbox/","series":[{"id":1346,"url":"http://patchwork.ozlabs.org/api/1.2/series/1346/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=1346","date":"2017-09-04T10:14:05","name":"[U-Boot] armv8: fsl: ifc: Put IFC related code under CONFIG_FSL_IFC","version":1,"mbox":"http://patchwork.ozlabs.org/series/1346/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809583/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809583/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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","X-Forefront-PRVS":"0420213CCD","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"04 Sep 2017 10:14:12.6150\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"CY1PR03MB2268","Cc":"albert.u.boot@aribaud.net, priyanka.jain@nxp.com","Subject":"[U-Boot] [PATCH] armv8: fsl: ifc: Put IFC related code under\n\tCONFIG_FSL_IFC","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"IFC code is put under CONFIG_FSL_IFC\n\nSigned-off-by: Sriram Dash \n---\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 ++\n arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 10 ++++++++++\n 2 files changed, 12 insertions(+)","diff":"diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex 639e9d2..a538d76 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -192,7 +192,9 @@ void bypass_smmu(void)\n void fsl_lsch3_early_init_f(void)\n {\n \terratum_rcw_src();\n+#ifdef CONFIG_FSL_IFC\n \tinit_early_memctl_regs();\t/* tighten IFC timing */\n+#endif\n #ifdef CONFIG_SYS_FSL_ERRATUM_A009203\n \terratum_a009203();\n #endif\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\nindex c4e5ecc..f231688 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h\n@@ -102,6 +102,7 @@ static struct mm_region early_map[] = {\n \t{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,\n \t CONFIG_SYS_FSL_QSPI_SIZE1,\n \t PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},\n+#ifdef CONFIG_FSL_IFC\n \t/* For IFC Region #1, only the first 4MB is cache-enabled */\n \t{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,\n \t CONFIG_SYS_FSL_IFC_SIZE1_1,\n@@ -116,6 +117,7 @@ static struct mm_region early_map[] = {\n \t CONFIG_SYS_FSL_IFC_SIZE1,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE\n \t},\n+#endif\n \t{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,\n \t CONFIG_SYS_FSL_DRAM_SIZE1,\n #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)\n@@ -125,11 +127,13 @@ static struct mm_region early_map[] = {\n #endif\n \t PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS\n \t},\n+#ifdef CONFIG_FSL_IFC\n \t/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */\n \t{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,\n \t CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE\n \t},\n+#endif\n \t{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,\n \t CONFIG_SYS_FSL_DCSR_SIZE,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n@@ -159,10 +163,12 @@ static struct mm_region early_map[] = {\n \t CONFIG_SYS_FSL_QSPI_SIZE,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE\n \t},\n+#ifdef CONFIG_FSL_IFC\n \t{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,\n \t CONFIG_SYS_FSL_IFC_SIZE,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE\n \t},\n+#endif\n \t{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,\n \t CONFIG_SYS_FSL_DRAM_SIZE1,\n #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)\n@@ -206,10 +212,12 @@ static struct mm_region final_map[] = {\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN\n \t},\n+#ifdef CONFIG_FSL_IFC\n \t{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,\n \t CONFIG_SYS_FSL_IFC_SIZE2,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE\n \t},\n+#endif\n \t{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,\n \t CONFIG_SYS_FSL_DCSR_SIZE,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n@@ -304,10 +312,12 @@ static struct mm_region final_map[] = {\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN\n \t},\n+#ifdef CONFIG_FSL_IFC\n \t{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,\n \t CONFIG_SYS_FSL_IFC_SIZE,\n \t PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE\n \t},\n+#endif\n \t{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,\n \t CONFIG_SYS_FSL_DRAM_SIZE1,\n \t PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n","prefixes":["U-Boot"]}