{"id":809343,"url":"http://patchwork.ozlabs.org/api/1.2/patches/809343/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170903181513.29635-1-fbarrat@linux.vnet.ibm.com/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.2/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<20170903181513.29635-1-fbarrat@linux.vnet.ibm.com>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/20170903181513.29635-1-fbarrat@linux.vnet.ibm.com/","date":"2017-09-03T18:15:12","name":"[v3,1/2] powerpc/mm: Export flush_all_mm()","commit_ref":"6110236b9bbd177debc045c5fc29224444686ece","pull_url":null,"state":"accepted","archived":false,"hash":"f5ec55b522c203b7b27ccf6dcdebb124dd6a9684","submitter":{"id":67555,"url":"http://patchwork.ozlabs.org/api/1.2/people/67555/?format=json","name":"Frederic Barrat","email":"fbarrat@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20170903181513.29635-1-fbarrat@linux.vnet.ibm.com/mbox/","series":[{"id":1267,"url":"http://patchwork.ozlabs.org/api/1.2/series/1267/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=1267","date":"2017-09-03T18:15:12","name":"[v3,1/2] powerpc/mm: Export flush_all_mm()","version":3,"mbox":"http://patchwork.ozlabs.org/series/1267/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/809343/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/809343/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xlh6R2r0xz9s7h\n\tfor ;\n\tMon, 4 Sep 2017 04:17:51 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xlh6R1TNYzDrk2\n\tfor ;\n\tMon, 4 Sep 2017 04:17:51 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xlh3d6MxrzDqjm\n\tfor ;\n\tMon, 4 Sep 2017 04:15:25 +1000 (AEST)","from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv83IDVsX001545\n\tfor ; Sun, 3 Sep 2017 14:15:23 -0400","from e06smtp12.uk.ibm.com (e06smtp12.uk.ibm.com [195.75.94.108])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2crgmekfhv-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Sun, 03 Sep 2017 14:15:22 -0400","from localhost\n\tby e06smtp12.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tSun, 3 Sep 2017 19:15:18 +0100","from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com\n\t[9.149.105.232])\n\tby b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v83IFIQZ8060942; Sun, 3 Sep 2017 18:15:18 GMT","from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 2A49252041;\n\tSun, 3 Sep 2017 18:10:39 +0100 (BST)","from localhost.localdomain (unknown [9.167.235.194])\n\tby d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 4B3EE5203F; \n\tSun, 3 Sep 2017 18:10:38 +0100 (BST)"],"From":"Frederic Barrat ","To":"mpe@ellerman.id.au, linuxppc-dev@lists.ozlabs.org,\n\tbenh@kernel.crashing.org, andrew.donnellan@au1.ibm.com,\n\tclombard@linux.vnet.ibm.com, vaibhav@linux.vnet.ibm.com","Subject":"[PATCH v3 1/2] powerpc/mm: Export flush_all_mm()","Date":"Sun, 3 Sep 2017 20:15:12 +0200","X-Mailer":"git-send-email 2.11.0","X-TM-AS-GCONF":"00","x-cbid":"17090318-0008-0000-0000-000004924979","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17090318-0009-0000-0000-00001E22A8C4","Message-Id":"<20170903181513.29635-1-fbarrat@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-03_05:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1709030303","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"alistair@popple.id.au","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"With the optimizations introduced by commit a46cc7a90fd8\n(\"powerpc/mm/radix: Improve TLB/PWC flushes\"), flush_tlb_mm() no\nlonger flushes the page walk cache with radix. This patch introduces\nflush_all_mm(), which flushes everything, tlb and pwc, for a given mm.\n\nSigned-off-by: Frederic Barrat \n---\nChangelog:\nv3: add comment to explain limitations on hash\nv2: this patch is new\n\n arch/powerpc/include/asm/book3s/64/tlbflush-hash.h | 20 ++++++++++++++++++++\n arch/powerpc/include/asm/book3s/64/tlbflush-radix.h | 3 +++\n arch/powerpc/include/asm/book3s/64/tlbflush.h | 15 +++++++++++++++\n arch/powerpc/mm/tlb-radix.c | 6 ++++--\n 4 files changed, 42 insertions(+), 2 deletions(-)","diff":"diff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h b/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h\nindex 2f6373144e2c..2ac45cf85042 100644\n--- a/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h\n+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-hash.h\n@@ -65,6 +65,26 @@ static inline void hash__flush_tlb_mm(struct mm_struct *mm)\n {\n }\n \n+static inline void hash__local_flush_all_mm(struct mm_struct *mm)\n+{\n+\t/*\n+\t * There's no Page Walk Cache for hash, so what is needed is\n+\t * the same as flush_tlb_mm(), which doesn't really make sense\n+\t * with hash. So the only thing we could do is flush the\n+\t * entire LPID! Punt for now, as it's not being used.\n+\t */\n+}\n+\n+static inline void hash__flush_all_mm(struct mm_struct *mm)\n+{\n+\t/*\n+\t * There's no Page Walk Cache for hash, so what is needed is\n+\t * the same as flush_tlb_mm(), which doesn't really make sense\n+\t * with hash. So the only thing we could do is flush the\n+\t * entire LPID! Punt for now, as it's not being used.\n+\t */\n+}\n+\n static inline void hash__local_flush_tlb_page(struct vm_area_struct *vma,\n \t\t\t\t\t unsigned long vmaddr)\n {\ndiff --git a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h\nindex 9b433a624bf3..af06c6fe8a9f 100644\n--- a/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h\n+++ b/arch/powerpc/include/asm/book3s/64/tlbflush-radix.h\n@@ -21,17 +21,20 @@ extern void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long sta\n extern void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end);\n \n extern void radix__local_flush_tlb_mm(struct mm_struct *mm);\n+extern void radix__local_flush_all_mm(struct mm_struct *mm);\n extern void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);\n extern void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,\n \t\t\t\t\t int psize);\n extern void radix__tlb_flush(struct mmu_gather *tlb);\n #ifdef CONFIG_SMP\n extern void radix__flush_tlb_mm(struct mm_struct *mm);\n+extern void radix__flush_all_mm(struct mm_struct *mm);\n extern void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);\n extern void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,\n \t\t\t\t\tint psize);\n #else\n #define radix__flush_tlb_mm(mm)\t\tradix__local_flush_tlb_mm(mm)\n+#define radix__flush_all_mm(mm)\t\tradix__local_flush_all_mm(mm)\n #define radix__flush_tlb_page(vma,addr)\tradix__local_flush_tlb_page(vma,addr)\n #define radix__flush_tlb_page_psize(mm,addr,p) radix__local_flush_tlb_page_psize(mm,addr,p)\n #endif\ndiff --git a/arch/powerpc/include/asm/book3s/64/tlbflush.h b/arch/powerpc/include/asm/book3s/64/tlbflush.h\nindex 72b925f97bab..70760d018bcd 100644\n--- a/arch/powerpc/include/asm/book3s/64/tlbflush.h\n+++ b/arch/powerpc/include/asm/book3s/64/tlbflush.h\n@@ -57,6 +57,13 @@ static inline void local_flush_tlb_page(struct vm_area_struct *vma,\n \treturn hash__local_flush_tlb_page(vma, vmaddr);\n }\n \n+static inline void local_flush_all_mm(struct mm_struct *mm)\n+{\n+\tif (radix_enabled())\n+\t\treturn radix__local_flush_all_mm(mm);\n+\treturn hash__local_flush_all_mm(mm);\n+}\n+\n static inline void tlb_flush(struct mmu_gather *tlb)\n {\n \tif (radix_enabled())\n@@ -79,9 +86,17 @@ static inline void flush_tlb_page(struct vm_area_struct *vma,\n \t\treturn radix__flush_tlb_page(vma, vmaddr);\n \treturn hash__flush_tlb_page(vma, vmaddr);\n }\n+\n+static inline void flush_all_mm(struct mm_struct *mm)\n+{\n+\tif (radix_enabled())\n+\t\treturn radix__flush_all_mm(mm);\n+\treturn hash__flush_all_mm(mm);\n+}\n #else\n #define flush_tlb_mm(mm)\t\tlocal_flush_tlb_mm(mm)\n #define flush_tlb_page(vma, addr)\tlocal_flush_tlb_page(vma, addr)\n+#define flush_all_mm(mm)\t\tlocal_flush_all_mm(mm)\n #endif /* CONFIG_SMP */\n /*\n * flush the page walk cache for the address\ndiff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c\nindex b3e849c4886e..5a1f46eff3a2 100644\n--- a/arch/powerpc/mm/tlb-radix.c\n+++ b/arch/powerpc/mm/tlb-radix.c\n@@ -144,7 +144,7 @@ void radix__local_flush_tlb_mm(struct mm_struct *mm)\n EXPORT_SYMBOL(radix__local_flush_tlb_mm);\n \n #ifndef CONFIG_SMP\n-static void radix__local_flush_all_mm(struct mm_struct *mm)\n+void radix__local_flush_all_mm(struct mm_struct *mm)\n {\n \tunsigned long pid;\n \n@@ -154,6 +154,7 @@ static void radix__local_flush_all_mm(struct mm_struct *mm)\n \t\t_tlbiel_pid(pid, RIC_FLUSH_ALL);\n \tpreempt_enable();\n }\n+EXPORT_SYMBOL(radix__local_flush_all_mm);\n #endif /* CONFIG_SMP */\n \n void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,\n@@ -200,7 +201,7 @@ void radix__flush_tlb_mm(struct mm_struct *mm)\n }\n EXPORT_SYMBOL(radix__flush_tlb_mm);\n \n-static void radix__flush_all_mm(struct mm_struct *mm)\n+void radix__flush_all_mm(struct mm_struct *mm)\n {\n \tunsigned long pid;\n \n@@ -216,6 +217,7 @@ static void radix__flush_all_mm(struct mm_struct *mm)\n no_context:\n \tpreempt_enable();\n }\n+EXPORT_SYMBOL(radix__flush_all_mm);\n \n void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)\n {\n","prefixes":["v3","1/2"]}