{"id":808843,"url":"http://patchwork.ozlabs.org/api/1.2/patches/808843/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504286483-23327-2-git-send-email-eric.auger@redhat.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504286483-23327-2-git-send-email-eric.auger@redhat.com>","list_archive_url":null,"date":"2017-09-01T17:21:04","name":"[v7,01/20] hw/arm/smmu-common: smmu base device and datatypes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ad8c07a4157343e786c15d91130dd0c99cc7ccd0","submitter":{"id":69187,"url":"http://patchwork.ozlabs.org/api/1.2/people/69187/?format=json","name":"Eric Auger","email":"eric.auger@redhat.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1504286483-23327-2-git-send-email-eric.auger@redhat.com/mbox/","series":[{"id":1082,"url":"http://patchwork.ozlabs.org/api/1.2/series/1082/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1082","date":"2017-09-01T17:21:04","name":"[v7,01/20] hw/arm/smmu-common: smmu base device and datatypes","version":7,"mbox":"http://patchwork.ozlabs.org/series/1082/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/808843/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808843/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ext-mx08.extmail.prod.ext.phx2.redhat.com;\n\tdmarc=none (p=none dis=none) header.from=redhat.com","ext-mx08.extmail.prod.ext.phx2.redhat.com;\n\tspf=fail smtp.mailfrom=eric.auger@redhat.com"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xkQzd2nxmz9t32\n\tfor ;\n\tSat, 2 Sep 2017 03:22:37 +1000 (AEST)","from localhost ([::1]:51215 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1dnpeN-0004kq-4l\n\tfor incoming@patchwork.ozlabs.org; Fri, 01 Sep 2017 13:22:35 -0400","from eggs.gnu.org ([2001:4830:134:3::10]:36053)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from ) id 1dnpde-0004dw-73\n\tfor qemu-devel@nongnu.org; Fri, 01 Sep 2017 13:21:55 -0400","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from ) id 1dnpdc-0001r2-Gh\n\tfor qemu-devel@nongnu.org; Fri, 01 Sep 2017 13:21:50 -0400","from mx1.redhat.com ([209.132.183.28]:53964)\n\tby eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.71) (envelope-from )\n\tid 1dnpdY-0001mW-Bb; Fri, 01 Sep 2017 13:21:44 -0400","from smtp.corp.redhat.com\n\t(int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby mx1.redhat.com (Postfix) with ESMTPS id 3BB83C057FA1;\n\tFri, 1 Sep 2017 17:21:43 +0000 (UTC)","from localhost.localdomain.com (ovpn-117-241.ams2.redhat.com\n\t[10.36.117.241])\n\tby smtp.corp.redhat.com (Postfix) with ESMTP id 7494B62929;\n\tFri, 1 Sep 2017 17:21:38 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mx1.redhat.com 3BB83C057FA1","From":"Eric Auger ","To":"eric.auger.pro@gmail.com, eric.auger@redhat.com, peter.maydell@linaro.org,\n\tqemu-arm@nongnu.org, qemu-devel@nongnu.org, prem.mallappa@gmail.com, \n\talex.williamson@redhat.com","Date":"Fri, 1 Sep 2017 19:21:04 +0200","Message-Id":"<1504286483-23327-2-git-send-email-eric.auger@redhat.com>","In-Reply-To":"<1504286483-23327-1-git-send-email-eric.auger@redhat.com>","References":"<1504286483-23327-1-git-send-email-eric.auger@redhat.com>","X-Scanned-By":"MIMEDefang 2.79 on 10.5.11.15","X-Greylist":"Sender IP whitelisted, not delayed by milter-greylist-4.5.16\n\t(mx1.redhat.com [10.5.110.32]);\n\tFri, 01 Sep 2017 17:21:43 +0000 (UTC)","X-detected-operating-system":"by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic]\n\t[fuzzy]","X-Received-From":"209.132.183.28","Subject":"[Qemu-devel] [PATCH v7 01/20] hw/arm/smmu-common: smmu base device\n\tand datatypes","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mohun106@gmail.com, drjones@redhat.com, tcain@qti.qualcomm.com,\n\tRadha.Chintakuntla@cavium.com, Sunil.Goutham@cavium.com,\n\tmst@redhat.com, jean-philippe.brucker@arm.com, tn@semihalf.com,\n\twill.deacon@arm.com, robin.murphy@arm.com, peterx@redhat.com,\n\tedgar.iglesias@gmail.com, bharat.bhushan@nxp.com,\n\tchristoffer.dall@linaro.org, wtownsen@redhat.com","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"The patch introduces the smmu base device and class for the ARM\nsmmu. Devices for specific versions will be derived from this\nbase device.\n\nWe also introduce some important datatypes.\n\nSigned-off-by: Eric Auger \nSigned-off-by: Prem Mallappa \n\n---\n\nv3 -> v4:\n- added smmu_find_as_from_bus_num\n- SMMU_PCI_BUS_MAX and SMMU_PCI_DEVFN_MAX in smmu-common header\n- new fields in SMMUState:\n - iommu_ops, smmu_as_by_busptr, smmu_as_by_bus_num\n- add aa64[] field in SMMUTransCfg\n\nv3:\n- moved the base code in a separate patch to ease the review.\n- clearer separation between base class and smmuv3 class\n- translate_* only implemented as class methods\n---\n default-configs/aarch64-softmmu.mak | 1 +\n hw/arm/Makefile.objs | 1 +\n hw/arm/smmu-common.c | 58 +++++++++++++++++++\n include/hw/arm/smmu-common.h | 108 ++++++++++++++++++++++++++++++++++++\n 4 files changed, 168 insertions(+)\n create mode 100644 hw/arm/smmu-common.c\n create mode 100644 include/hw/arm/smmu-common.h","diff":"diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-softmmu.mak\nindex 2449483..83a2932 100644\n--- a/default-configs/aarch64-softmmu.mak\n+++ b/default-configs/aarch64-softmmu.mak\n@@ -7,3 +7,4 @@ CONFIG_AUX=y\n CONFIG_DDC=y\n CONFIG_DPCD=y\n CONFIG_XLNX_ZYNQMP=y\n+CONFIG_ARM_SMMUV3=y\ndiff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs\nindex a2e56ec..5b2d38d 100644\n--- a/hw/arm/Makefile.objs\n+++ b/hw/arm/Makefile.objs\n@@ -19,3 +19,4 @@ obj-$(CONFIG_FSL_IMX31) += fsl-imx31.o kzm.o\n obj-$(CONFIG_FSL_IMX6) += fsl-imx6.o sabrelite.o\n obj-$(CONFIG_ASPEED_SOC) += aspeed_soc.o aspeed.o\n obj-$(CONFIG_MPS2) += mps2.o\n+obj-$(CONFIG_ARM_SMMUV3) += smmu-common.o\ndiff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c\nnew file mode 100644\nindex 0000000..56608f1\n--- /dev/null\n+++ b/hw/arm/smmu-common.c\n@@ -0,0 +1,58 @@\n+/*\n+ * Copyright (C) 2014-2016 Broadcom Corporation\n+ * Copyright (c) 2017 Red Hat, Inc.\n+ * Written by Prem Mallappa, Eric Auger\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License version 2 as\n+ * published by the Free Software Foundation.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License\n+ * along with this program; if not, write to the Free Software\n+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.\n+ *\n+ * Author: Prem Mallappa \n+ *\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"sysemu/sysemu.h\"\n+#include \"exec/address-spaces.h\"\n+#include \"trace.h\"\n+#include \"exec/target_page.h\"\n+#include \"qom/cpu.h\"\n+\n+#include \"qemu/error-report.h\"\n+#include \"hw/arm/smmu-common.h\"\n+\n+static void smmu_base_instance_init(Object *obj)\n+{\n+}\n+\n+static void smmu_base_class_init(ObjectClass *klass, void *data)\n+{\n+}\n+\n+static const TypeInfo smmu_base_info = {\n+ .name = TYPE_SMMU_DEV_BASE,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(SMMUState),\n+ .instance_init = smmu_base_instance_init,\n+ .class_data = NULL,\n+ .class_size = sizeof(SMMUBaseClass),\n+ .class_init = smmu_base_class_init,\n+ .abstract = true,\n+};\n+\n+static void smmu_base_register_types(void)\n+{\n+ type_register_static(&smmu_base_info);\n+}\n+\n+type_init(smmu_base_register_types)\n+\ndiff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h\nnew file mode 100644\nindex 0000000..38cd18f\n--- /dev/null\n+++ b/include/hw/arm/smmu-common.h\n@@ -0,0 +1,108 @@\n+/*\n+ * ARM SMMU Support\n+ *\n+ * Copyright (C) 2015-2016 Broadcom Corporation\n+ * Copyright (c) 2017 Red Hat, Inc.\n+ * Written by Prem Mallappa, Eric Auger\n+ *\n+ * This program is free software; you can redistribute it and/or modify\n+ * it under the terms of the GNU General Public License as published by\n+ * the Free Software Foundation, either version 2 of the License, or\n+ * (at your option) any later version.\n+ *\n+ * This program is distributed in the hope that it will be useful,\n+ * but WITHOUT ANY WARRANTY; without even the implied warranty of\n+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+ * GNU General Public License for more details.\n+ *\n+ * You should have received a copy of the GNU General Public License along\n+ * with this program; if not, see .\n+ */\n+\n+#ifndef HW_ARM_SMMU_COMMON_H\n+#define HW_ARM_SMMU_COMMON_H\n+\n+#include \n+#include \"hw/pci/pci.h\"\n+\n+#define SMMU_PCI_BUS_MAX 256\n+#define SMMU_PCI_DEVFN_MAX 256\n+\n+/*\n+ * Page table walk generic errors\n+ * At the moment values match SMMUv3 event numbers though\n+ */\n+typedef enum {\n+ SMMU_TRANS_ERR_NONE = 0x0,\n+ SMMU_TRANS_ERR_WALK_EXT_ABRT = 0x1, /* Translation walk external abort */\n+ SMMU_TRANS_ERR_TRANS = 0x10, /* Translation fault */\n+ SMMU_TRANS_ERR_ADDR_SZ, /* Address Size fault */\n+ SMMU_TRANS_ERR_ACCESS, /* Access fault */\n+ SMMU_TRANS_ERR_PERM, /* Permission fault */\n+ SMMU_TRANS_ERR_TLB_CONFLICT = 0x20, /* TLB Conflict */\n+} SMMUTransErr;\n+\n+/*\n+ * Generic structure populated by derived SMMU devices\n+ * after decoding the configuration information and used as\n+ * input to the page table walk\n+ */\n+typedef struct SMMUTransCfg {\n+ hwaddr input; /* input address */\n+ hwaddr output; /* Output address */\n+ int stage; /* translation stage */\n+ uint32_t oas; /* output address width */\n+ uint32_t tsz; /* input range, ie. 2^(64 -tnsz)*/\n+ uint64_t ttbr; /* TTBR address */\n+ uint32_t granule_sz; /* granule page shift */\n+ bool aa64; /* arch64 or aarch32 translation table */\n+ int initial_level; /* initial lookup level */\n+ bool disabled; /* smmu is disabled */\n+ bool bypassed; /* stage is bypassed */\n+} SMMUTransCfg;\n+\n+typedef struct SMMUDevice {\n+ void *smmu;\n+ PCIBus *bus;\n+ int devfn;\n+ IOMMUMemoryRegion iommu;\n+ AddressSpace as;\n+} SMMUDevice;\n+\n+typedef struct SMMUNotifierNode {\n+ SMMUDevice *sdev;\n+ QLIST_ENTRY(SMMUNotifierNode) next;\n+} SMMUNotifierNode;\n+\n+typedef struct SMMUPciBus {\n+ PCIBus *bus;\n+ SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */\n+} SMMUPciBus;\n+\n+typedef struct SMMUState {\n+ /* */\n+ SysBusDevice dev;\n+ char *mrtypename;\n+ MemoryRegion iomem;\n+\n+ GHashTable *smmu_as_by_busptr;\n+ SMMUPciBus *smmu_as_by_bus_num[SMMU_PCI_BUS_MAX];\n+ QLIST_HEAD(, SMMUNotifierNode) notifiers_list;\n+\n+} SMMUState;\n+\n+typedef int (*smmu_page_walk_hook)(IOMMUTLBEntry *entry, void *private);\n+\n+typedef struct {\n+ /* */\n+ SysBusDeviceClass parent_class;\n+} SMMUBaseClass;\n+\n+#define TYPE_SMMU_DEV_BASE \"smmu-base\"\n+#define SMMU_SYS_DEV(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_SMMU_DEV_BASE)\n+#define SMMU_DEVICE_GET_CLASS(obj) \\\n+ OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_SMMU_DEV_BASE)\n+#define SMMU_DEVICE_CLASS(klass) \\\n+ OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_SMMU_DEV_BASE)\n+\n+#endif /* HW_ARM_SMMU_COMMON */\n","prefixes":["v7","01/20"]}