{"id":808289,"url":"http://patchwork.ozlabs.org/api/1.2/patches/808289/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170831155519.3704-2-boris.brezillon@free-electrons.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.2/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170831155519.3704-2-boris.brezillon@free-electrons.com>","list_archive_url":null,"date":"2017-08-31T15:55:19","name":"[v3,2/2] dt-bindings: drm/bridge: Document Cadence DSI bridge bindings","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"2e81347e1e58732c370f93c20e7a4562a9dbf408","submitter":{"id":63120,"url":"http://patchwork.ozlabs.org/api/1.2/people/63120/?format=json","name":"Boris Brezillon","email":"boris.brezillon@free-electrons.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20170831155519.3704-2-boris.brezillon@free-electrons.com/mbox/","series":[{"id":862,"url":"http://patchwork.ozlabs.org/api/1.2/series/862/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=862","date":"2017-08-31T15:55:19","name":null,"version":3,"mbox":"http://patchwork.ozlabs.org/series/862/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/808289/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/808289/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xjn5l5L6kz9sD9\n\tfor ;\n\tFri, 1 Sep 2017 01:55:39 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751814AbdHaPzh (ORCPT\n\t);\n\tThu, 31 Aug 2017 11:55:37 -0400","from mail.free-electrons.com ([62.4.15.54]:55595 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752066AbdHaPze (ORCPT\n\t); Thu, 31 Aug 2017 11:55:34 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 556D4209BD; Thu, 31 Aug 2017 17:55:32 +0200 (CEST)","from localhost.localdomain\n\t(LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id D970520A19;\n\tThu, 31 Aug 2017 17:55:21 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","From":"Boris Brezillon ","To":"David Airlie , Daniel Vetter ,\n\tdri-devel@lists.freedesktop.org, Archit Taneja ","Cc":"Rob Herring , Pawel Moll ,\n\tMark Rutland ,\n\tIan Campbell ,\n\tKumar Gala , devicetree@vger.kernel.org,\n\tNeil Webb , Richard Sproul ,\n\tSimon Hatliff ,\n\tMaxime Ripard ,\n\tThomas Petazzoni ,\n\tCyprian Wronka ,\n\tAlan Douglas , \n\tTomi Valkeinen , Jyri Sarha ,\n\tBoris Brezillon ","Subject":"[PATCH v3 2/2] dt-bindings: drm/bridge: Document Cadence DSI bridge\n\tbindings","Date":"Thu, 31 Aug 2017 17:55:19 +0200","Message-Id":"<20170831155519.3704-2-boris.brezillon@free-electrons.com>","X-Mailer":"git-send-email 2.11.0","In-Reply-To":"<20170831155519.3704-1-boris.brezillon@free-electrons.com>","References":"<20170831155519.3704-1-boris.brezillon@free-electrons.com>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"Document the bindings used for the Cadence DSI bridge.\n\nSigned-off-by: Boris Brezillon \n---\nChanges in v3:\n- Fix clock names in the example\n- Document how to represent DSI devices that are controller through\n an external bus like I2C or SPI\n\nChanges in v2:\n- None\n---\n .../bindings/display/bridge/cdns,dsi.txt | 109 +++++++++++++++++++++\n 1 file changed, 109 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt","diff":"diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\nnew file mode 100644\nindex 000000000000..c70008bd8c0d\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt\n@@ -0,0 +1,109 @@\n+Cadence DSI bridge\n+==================\n+\n+The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.\n+\n+Required properties:\n+- compatible: should be set to \"cdns,dsi-1.3.1\".\n+- reg: physical base address and length of the controller's registers.\n+- interrupts: interrupt line connected to the DSI bridge.\n+- clocks: DSI bridge clocks.\n+- clock-names: must contain \"pclk\" and \"sysclk\".\n+- phys: phandle link to the MIPI D-PHY controller.\n+- phy-names: must contain \"dphy\".\n+- #address-cells: must be set to 1.\n+- #size-cells: must be set to 0.\n+\n+Required subnodes:\n+- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.\n+ 2 ports are available:\n+ * port 0: this port is only needed if some of your DSI devices are\n+\t controlled through an external bus like I2C or SPI. Can have at\n+\t most 4 endpoints. The endpoint number is directly encoding the\n+\t DSI virtual channel used by this device.\n+ * port 1: represents the DPI input.\n+ Other ports will be added later to support the new kind of inputs.\n+\n+- one subnode per DSI device connected on the DSI bus. Each DSI device should\n+ contain a reg property encoding its virtual channel.\n+\n+Example:\n+\n+\tdsi0: dsi@fd0c0000 {\n+\t\tcompatible = \"cdns,dsi-1.3.1\";\n+\t\treg = <0x0 0xfd0c0000 0x0 0x1000>;\n+\t\tclocks = <&pclk>, <&sysclk>;\n+\t\tclock-names = \"pclk\", \"sysclk\";\n+\t\tinterrupts = <1>;\n+\t\tphys = <&dphy1>;\n+\t\tphy-names = \"dphy\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tdsi0_dpi_input: endpoint {\n+\t\t\t\t\tremote-endpoint = <&xxx_dpi_output>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n+\t\tpanel: dsi-dev@0 {\n+\t\t\tcompatible = \"\";\n+\t\t\treg = <0>;\n+\t\t};\n+\t};\n+\n+or\n+\n+\tdsi0: dsi@fd0c0000 {\n+\t\tcompatible = \"cdns,dsi\";\n+\t\treg = <0x0 0xfd0c0000 0x0 0x1000>;\n+\t\tclocks = <&pclk>, <&sysclk>;\n+\t\tclock-names = \"pclk\", \"sysclk\";\n+\t\tinterrupts = <1>;\n+\t\tphys = <&dphy1>;\n+\t\tphy-names = \"dphy\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tports {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\n+\t\t\tport@0 {\n+\t\t\t\treg = <0>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\tdsi0_output: endpoint@0 {\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t\tremote-endpoint = <&dsi_panel_input>;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\tport@1 {\n+\t\t\t\treg = <1>;\n+\t\t\t\tdsi0_dpi_input: endpoint {\n+\t\t\t\t\tremote-endpoint = <&xxx_dpi_output>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\ti2c@xxx {\n+\t\tpanel: panel@59 {\n+\t\t\tcompatible = \"\";\n+\t\t\treg = <0x59>;\n+\n+\t\t\tport {\n+\t\t\t\tdsi_panel_input: endpoint {\n+\t\t\t\t\tremote-endpoint = <&dsi0_output>;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n","prefixes":["v3","2/2"]}