{"id":807669,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807669/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504104653-26804-2-git-send-email-alexandre.torgue@st.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.2/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504104653-26804-2-git-send-email-alexandre.torgue@st.com>","list_archive_url":null,"date":"2017-08-30T14:50:53","name":"[v4] ARM: dts: stm32: change pinctrl bindings definition","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"b00d6f773558f33d85995fbe0f5474148ad5467c","submitter":{"id":68429,"url":"http://patchwork.ozlabs.org/api/1.2/people/68429/?format=json","name":"Alexandre TORGUE","email":"alexandre.torgue@st.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1504104653-26804-2-git-send-email-alexandre.torgue@st.com/mbox/","series":[{"id":632,"url":"http://patchwork.ozlabs.org/api/1.2/series/632/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=632","date":"2017-08-30T14:50:53","name":"[v4] ARM: dts: stm32: change pinctrl bindings definition","version":4,"mbox":"http://patchwork.ozlabs.org/series/632/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807669/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807669/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xj81S64x7z9sN7\n\tfor ;\n\tThu, 31 Aug 2017 01:04:44 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751710AbdH3PEn (ORCPT\n\t);\n\tWed, 30 Aug 2017 11:04:43 -0400","from mx08-00178001.pphosted.com ([91.207.212.93]:35998 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751435AbdH3PAN (ORCPT\n\t); Wed, 30 Aug 2017 11:00:13 -0400","from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7UEwkgw021809; Wed, 30 Aug 2017 16:59:00 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-.pphosted.com with ESMTP id 2cnkgpvtrb-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tWed, 30 Aug 2017 16:59:00 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4836C31;\n\tWed, 30 Aug 2017 14:58:59 +0000 (GMT)","from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C8B95260E;\n\tWed, 30 Aug 2017 14:58:55 +0000 (GMT)","from localhost (10.75.127.50) by SFHDAG3NODE2.st.com (10.75.127.8)\n\twith Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tWed, 30 Aug 2017 16:58:54 +0200"],"From":"Alexandre Torgue ","To":"Maxime Coquelin ,\n\tLinus Walleij ,\n\tRob Herring , \n\tMark Rutland , Arnd Bergmann ,\n\tRussell King ","CC":",\n\t, ,\n\t, Benjamin Gaignard ","Subject":"[PATCH v4] ARM: dts: stm32: change pinctrl bindings definition","Date":"Wed, 30 Aug 2017 16:50:53 +0200","Message-ID":"<1504104653-26804-2-git-send-email-alexandre.torgue@st.com>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1504104653-26804-1-git-send-email-alexandre.torgue@st.com>","References":"<1504104653-26804-1-git-send-email-alexandre.torgue@st.com>","MIME-Version":"1.0","Content-Type":"text/plain","X-Originating-IP":"[10.75.127.50]","X-ClientProxiedBy":"SFHDAG2NODE1.st.com (10.75.127.4) To SFHDAG3NODE2.st.com\n\t(10.75.127.8)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-30_06:, , signatures=0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"Initially each pin was declared in \"include/dt-bindings/stm32-pinfunc.h\"\nand each definition contained SOC names (ex: STM32F429_PA9_FUNC_USART1_TX).\nSince this approach was approved, the number of supported MCU has\nincreased (STM32F429/STM32F469/STM32f746/STM32H743). To avoid to add a new\nfile in \"include/dt-bindings\" each time a new STM32 SOC arrives I propose\na new approach which consist to use a macro to define pin muxing in device\ntree. All STM32 will use the common macro to define pinmux. Furthermore, it\nwill make STM32 maintenance and integration of new SOC easier .\n\nSigned-off-by: Alexandre TORGUE \nReviewed-by: Vikas MANOCHA \nReviewed-by: Benjamin Gaignard \nAcked-by: Linus Walleij ","diff":"diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt\nindex d907a74..900be24 100644\n--- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt\n+++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt\n@@ -143,6 +143,24 @@ Required properties:\n * 16 : Alternate Function 15\n * 17 : Analog\n \n+ To simplify the usage, macro is available to generate \"pinmux\" field.\n+ This macro is available here:\n+ - include/dt-bindings/pinctrl/stm32-pinfunc.h\n+\n+ Some examples of using macro:\n+ /* GPIO A9 set as alernate function 2 */\n+ ... {\n+\t\tpinmux = ;\n+ };\n+ /* GPIO A9 set as GPIO */\n+ ... {\n+\t\tpinmux = ;\n+ };\n+ /* GPIO A9 set as analog */\n+ ... {\n+\t\tpinmux = ;\n+ };\n+\n Optional properties:\n - GENERIC_PINCONFIG: is the generic pinconfig options to use.\n Available options are:\n@@ -165,13 +183,13 @@ pin-controller {\n ...\n \tusart1_pins_a: usart1@0 {\n \t\tpins1 {\n-\t\t\tpinmux = ;\n+\t\t\tpinmux = ;\n \t\t\tbias-disable;\n \t\t\tdrive-push-pull;\n \t\t\tslew-rate = <0>;\n \t\t};\n \t\tpins2 {\n-\t\t\tpinmux = ;\n+\t\t\tpinmux = ;\n \t\t\tbias-disable;\n \t\t};\n \t};\ndiff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi\nindex a8113dc..e0b3337 100644\n--- a/arch/arm/boot/dts/stm32f429.dtsi\n+++ b/arch/arm/boot/dts/stm32f429.dtsi\n@@ -47,7 +47,7 @@\n \n #include \"skeleton.dtsi\"\n #include \"armv7-m.dtsi\"\n-#include \n+#include \n #include \n #include \n \n@@ -687,35 +687,35 @@\n \n \t\t\tusart1_pins_a: usart1@0 {\n \t\t\t\tpins1 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART1_TX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <0>;\n \t\t\t\t};\n \t\t\t\tpins2 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART1_RX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\tusart3_pins_a: usart3@0 {\n \t\t\t\tpins1 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART3_TX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <0>;\n \t\t\t\t};\n \t\t\t\tpins2 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART3_RX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\tusbotg_fs_pins_a: usbotg_fs@0 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* OTG_FS_ID */\n+\t\t\t\t\t\t , /* OTG_FS_DM */\n+\t\t\t\t\t\t ; /* OTG_FS_DP */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <2>;\n@@ -724,9 +724,9 @@\n \n \t\t\tusbotg_fs_pins_b: usbotg_fs@1 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* OTG_HS_ID */\n+\t\t\t\t\t\t , /* OTG_HS_DM */\n+\t\t\t\t\t\t ; /* OTG_HS_DP */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <2>;\n@@ -735,18 +735,18 @@\n \n \t\t\tusbotg_hs_pins_a: usbotg_hs@0 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* OTG_HS_ULPI_NXT*/\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_DIR */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_STP */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_CK */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_D0 */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_D1 */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_D2 */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_D3 */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_D4 */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_D5 */\n+\t\t\t\t\t\t , /* OTG_HS_ULPI_D6 */\n+\t\t\t\t\t\t ; /* OTG_HS_ULPI_D7 */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <2>;\n@@ -755,49 +755,49 @@\n \n \t\t\tethernet_mii: mii@0 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* ETH_MII_TXD0_ETH_RMII_TXD0 */\n+\t\t\t\t\t\t , /* ETH_MII_TXD1_ETH_RMII_TXD1 */\n+\t\t\t\t\t\t , /* ETH_MII_TXD2 */\n+\t\t\t\t\t\t , /* ETH_MII_TXD3 */\n+\t\t\t\t\t\t , /* ETH_MII_TX_CLK */\n+\t\t\t\t\t\t , /* ETH_MII_TX_EN_ETH_RMII_TX_EN */\n+\t\t\t\t\t\t , /* ETH_MDIO */\n+\t\t\t\t\t\t , /* ETH_MDC */\n+\t\t\t\t\t\t , /* ETH_MII_RX_CLK_ETH_RMII_REF_CLK */\n+\t\t\t\t\t\t , /* ETH_MII_RX_DV_ETH_RMII_CRS_DV */\n+\t\t\t\t\t\t , /* ETH_MII_RXD0_ETH_RMII_RXD0 */\n+\t\t\t\t\t\t , /* ETH_MII_RXD1_ETH_RMII_RXD1 */\n+\t\t\t\t\t\t , /* ETH_MII_RXD2 */\n+\t\t\t\t\t\t ; /* ETH_MII_RXD3 */\n \t\t\t\t\tslew-rate = <2>;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\tadc3_in8_pin: adc@200 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\tpwm1_pins: pwm@1 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* TIM1_CH1 */\n+\t\t\t\t\t\t , /* TIM1_CH1N */\n+\t\t\t\t\t\t ; /* TIM1_BKIN */\n \t\t\t\t};\n \t\t\t};\n \n \t\t\tpwm3_pins: pwm@3 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* TIM3_CH1 */\n+\t\t\t\t\t\t ; /* TIM3_CH2 */\n \t\t\t\t};\n \t\t\t};\n \n \t\t\ti2c1_pins: i2c1@0 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* I2C1_SDA */\n+\t\t\t\t\t\t ; /* I2C1_SCL */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-open-drain;\n \t\t\t\t\tslew-rate = <3>;\n@@ -806,55 +806,55 @@\n \n \t\t\tltdc_pins: ltdc@0 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* LCD_HSYNC */\n+\t\t\t\t\t\t , /* LCD_VSYNC */\n+\t\t\t\t\t\t , /* LCD_CLK */\n+\t\t\t\t\t\t , /* LCD_R0 */\n+\t\t\t\t\t\t , /* LCD_R1 */\n+\t\t\t\t\t\t , /* LCD_R2 */\n+\t\t\t\t\t\t , /* LCD_R3 */\n+\t\t\t\t\t\t , /* LCD_R4 */\n+\t\t\t\t\t\t , /* LCD_R5 */\n+\t\t\t\t\t\t , /* LCD_R6*/\n+\t\t\t\t\t\t , /* LCD_R7 */\n+\t\t\t\t\t\t , /* LCD_G0 */\n+\t\t\t\t\t\t , /* LCD_G1 */\n+\t\t\t\t\t\t , /* LCD_G2 */\n+\t\t\t\t\t\t , /* LCD_G3 */\n+\t\t\t\t\t\t , /* LCD_G4 */\n+\t\t\t\t\t\t , /* LCD_B0 */\n+\t\t\t\t\t\t , /* LCD_B1 */\n+\t\t\t\t\t\t , /* LCD_B2 */\n+\t\t\t\t\t\t , /* LCD_B3*/\n+\t\t\t\t\t\t , /* LCD_G5 */\n+\t\t\t\t\t\t , /* LCD_G6 */\n+\t\t\t\t\t\t , /* LCD_G7 */\n+\t\t\t\t\t\t , /* LCD_B4 */\n+\t\t\t\t\t\t , /* LCD_B5 */\n+\t\t\t\t\t\t , /* LCD_B6 */\n+\t\t\t\t\t\t , /* LCD_B7 */\n+\t\t\t\t\t\t ; /* LCD_DE */\n \t\t\t\t\tslew-rate = <2>;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\tdcmi_pins: dcmi@0 {\n \t\t\t\tpins {\n-\t\t\t\t\tpinmux = ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ,\n-\t\t\t\t\t\t ;\n+\t\t\t\t\tpinmux = , /* DCMI_HSYNC */\n+\t\t\t\t\t\t , /* DCMI_VSYNC */\n+\t\t\t\t\t\t , /* DCMI_PIXCLK */\n+\t\t\t\t\t\t , /* DCMI_D0 */\n+\t\t\t\t\t\t , /* DCMI_D1 */\n+\t\t\t\t\t\t , /* DCMI_D2 */\n+\t\t\t\t\t\t , /* DCMI_D3 */\n+\t\t\t\t\t\t , /*DCMI_D4 */\n+\t\t\t\t\t\t , /* DCMI_D5 */\n+\t\t\t\t\t\t , /* DCMI_D6 */\n+\t\t\t\t\t\t , /* DCMI_D7 */\n+\t\t\t\t\t\t , /* DCMI_D8 */\n+\t\t\t\t\t\t , /* DCMI_D9 */\n+\t\t\t\t\t\t , /* DCMI_D10 */\n+\t\t\t\t\t\t ; /* DCMI_D11 */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <3>;\ndiff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi\nindex 4506eb9..d00d445 100644\n--- a/arch/arm/boot/dts/stm32f746.dtsi\n+++ b/arch/arm/boot/dts/stm32f746.dtsi\n@@ -42,7 +42,7 @@\n \n #include \"skeleton.dtsi\"\n #include \"armv7-m.dtsi\"\n-#include \n+#include \n #include \n #include \n \n@@ -338,26 +338,26 @@\n \n \t\t\tusart1_pins_a: usart1@0 {\n \t\t\t\tpins1 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART1_TX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <0>;\n \t\t\t\t};\n \t\t\t\tpins2 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART1_RX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\tusart1_pins_b: usart1@1 {\n \t\t\t\tpins1 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART1_TX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <0>;\n \t\t\t\t};\n \t\t\t\tpins2 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART1_RX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t};\ndiff --git a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi\nindex 76bbd65..a5c1a5c 100644\n--- a/arch/arm/boot/dts/stm32h743-pinctrl.dtsi\n+++ b/arch/arm/boot/dts/stm32h743-pinctrl.dtsi\n@@ -40,7 +40,7 @@\n * OTHER DEALINGS IN THE SOFTWARE.\n */\n \n-#include \n+#include \n \n / {\n \tsoc {\n@@ -141,26 +141,26 @@\n \n \t\t\tusart1_pins: usart1@0 {\n \t\t\t\tpins1 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART1_TX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <0>;\n \t\t\t\t};\n \t\t\t\tpins2 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART1_RX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t};\n \n \t\t\tusart2_pins: usart2@0 {\n \t\t\t\tpins1 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART2_TX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t\tdrive-push-pull;\n \t\t\t\t\tslew-rate = <0>;\n \t\t\t\t};\n \t\t\t\tpins2 {\n-\t\t\t\t\tpinmux = ;\n+\t\t\t\t\tpinmux = ; /* USART2_RX */\n \t\t\t\t\tbias-disable;\n \t\t\t\t};\n \t\t\t};\ndiff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h\nnew file mode 100644\nindex 0000000..3e72766\n--- /dev/null\n+++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h\n@@ -0,0 +1,30 @@\n+#ifndef _DT_BINDINGS_STM32_PINFUNC_H\n+#define _DT_BINDINGS_STM32_PINFUNC_H\n+\n+/* define PIN modes */\n+#define GPIO\t0x0\n+#define AF0\t0x1\n+#define AF1\t0x2\n+#define AF2\t0x3\n+#define AF3\t0x4\n+#define AF4\t0x5\n+#define AF5\t0x6\n+#define AF6\t0x7\n+#define AF7\t0x8\n+#define AF8\t0x9\n+#define AF9\t0xa\n+#define AF10\t0xb\n+#define AF11\t0xc\n+#define AF12\t0xd\n+#define AF13\t0xe\n+#define AF14\t0xf\n+#define AF15\t0x10\n+#define ANALOG\t0x11\n+\n+/* define Pins number*/\n+#define PIN_NO(port, line)\t((port - 'A') * 0x10 + line)\n+\n+#define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode))\n+\n+#endif /* _DT_BINDINGS_STM32_PINFUNC_H */\n+\ndiff --git a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h b/include/dt-bindings/pinctrl/stm32f429-pinfunc.h\ndeleted file mode 100644\nindex 26f1879..0000000\n--- a/include/dt-bindings/pinctrl/stm32f429-pinfunc.h\n+++ /dev/null\n@@ -1,1239 +0,0 @@\n-#ifndef _DT_BINDINGS_STM32F429_PINFUNC_H\n-#define _DT_BINDINGS_STM32F429_PINFUNC_H\n-\n-#define STM32F429_PA0_FUNC_GPIO 0x0\n-#define STM32F429_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2\n-#define STM32F429_PA0_FUNC_TIM5_CH1 0x3\n-#define STM32F429_PA0_FUNC_TIM8_ETR 0x4\n-#define STM32F429_PA0_FUNC_USART2_CTS 0x8\n-#define STM32F429_PA0_FUNC_UART4_TX 0x9\n-#define STM32F429_PA0_FUNC_ETH_MII_CRS 0xc\n-#define STM32F429_PA0_FUNC_EVENTOUT 0x10\n-#define STM32F429_PA0_FUNC_ANALOG 0x11\n-\n-#define STM32F429_PA1_FUNC_GPIO 0x100\n-#define STM32F429_PA1_FUNC_TIM2_CH2 0x102\n-#define STM32F429_PA1_FUNC_TIM5_CH2 0x103\n-#define STM32F429_PA1_FUNC_USART2_RTS 0x108\n-#define STM32F429_PA1_FUNC_UART4_RX 0x109\n-#define STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c\n-#define STM32F429_PA1_FUNC_EVENTOUT 0x110\n-#define STM32F429_PA1_FUNC_ANALOG 0x111\n-\n-#define STM32F429_PA2_FUNC_GPIO 0x200\n-#define STM32F429_PA2_FUNC_TIM2_CH3 0x202\n-#define STM32F429_PA2_FUNC_TIM5_CH3 0x203\n-#define STM32F429_PA2_FUNC_TIM9_CH1 0x204\n-#define STM32F429_PA2_FUNC_USART2_TX 0x208\n-#define STM32F429_PA2_FUNC_ETH_MDIO 0x20c\n-#define STM32F429_PA2_FUNC_EVENTOUT 0x210\n-#define STM32F429_PA2_FUNC_ANALOG 0x211\n-\n-#define STM32F429_PA3_FUNC_GPIO 0x300\n-#define STM32F429_PA3_FUNC_TIM2_CH4 0x302\n-#define STM32F429_PA3_FUNC_TIM5_CH4 0x303\n-#define STM32F429_PA3_FUNC_TIM9_CH2 0x304\n-#define STM32F429_PA3_FUNC_USART2_RX 0x308\n-#define STM32F429_PA3_FUNC_OTG_HS_ULPI_D0 0x30b\n-#define STM32F429_PA3_FUNC_ETH_MII_COL 0x30c\n-#define STM32F429_PA3_FUNC_LCD_B5 0x30f\n-#define STM32F429_PA3_FUNC_EVENTOUT 0x310\n-#define STM32F429_PA3_FUNC_ANALOG 0x311\n-\n-#define STM32F429_PA4_FUNC_GPIO 0x400\n-#define STM32F429_PA4_FUNC_SPI1_NSS 0x406\n-#define STM32F429_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407\n-#define STM32F429_PA4_FUNC_USART2_CK 0x408\n-#define STM32F429_PA4_FUNC_OTG_HS_SOF 0x40d\n-#define STM32F429_PA4_FUNC_DCMI_HSYNC 0x40e\n-#define STM32F429_PA4_FUNC_LCD_VSYNC 0x40f\n-#define STM32F429_PA4_FUNC_EVENTOUT 0x410\n-#define STM32F429_PA4_FUNC_ANALOG 0x411\n-\n-#define STM32F429_PA5_FUNC_GPIO 0x500\n-#define STM32F429_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502\n-#define STM32F429_PA5_FUNC_TIM8_CH1N 0x504\n-#define STM32F429_PA5_FUNC_SPI1_SCK 0x506\n-#define STM32F429_PA5_FUNC_OTG_HS_ULPI_CK 0x50b\n-#define STM32F429_PA5_FUNC_EVENTOUT 0x510\n-#define STM32F429_PA5_FUNC_ANALOG 0x511\n-\n-#define STM32F429_PA6_FUNC_GPIO 0x600\n-#define STM32F429_PA6_FUNC_TIM1_BKIN 0x602\n-#define STM32F429_PA6_FUNC_TIM3_CH1 0x603\n-#define STM32F429_PA6_FUNC_TIM8_BKIN 0x604\n-#define STM32F429_PA6_FUNC_SPI1_MISO 0x606\n-#define STM32F429_PA6_FUNC_TIM13_CH1 0x60a\n-#define STM32F429_PA6_FUNC_DCMI_PIXCLK 0x60e\n-#define STM32F429_PA6_FUNC_LCD_G2 0x60f\n-#define STM32F429_PA6_FUNC_EVENTOUT 0x610\n-#define STM32F429_PA6_FUNC_ANALOG 0x611\n-\n-#define STM32F429_PA7_FUNC_GPIO 0x700\n-#define STM32F429_PA7_FUNC_TIM1_CH1N 0x702\n-#define STM32F429_PA7_FUNC_TIM3_CH2 0x703\n-#define STM32F429_PA7_FUNC_TIM8_CH1N 0x704\n-#define STM32F429_PA7_FUNC_SPI1_MOSI 0x706\n-#define STM32F429_PA7_FUNC_TIM14_CH1 0x70a\n-#define STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c\n-#define STM32F429_PA7_FUNC_EVENTOUT 0x710\n-#define STM32F429_PA7_FUNC_ANALOG 0x711\n-\n-#define STM32F429_PA8_FUNC_GPIO 0x800\n-#define STM32F429_PA8_FUNC_MCO1 0x801\n-#define STM32F429_PA8_FUNC_TIM1_CH1 0x802\n-#define STM32F429_PA8_FUNC_I2C3_SCL 0x805\n-#define STM32F429_PA8_FUNC_USART1_CK 0x808\n-#define STM32F429_PA8_FUNC_OTG_FS_SOF 0x80b\n-#define STM32F429_PA8_FUNC_LCD_R6 0x80f\n-#define STM32F429_PA8_FUNC_EVENTOUT 0x810\n-#define STM32F429_PA8_FUNC_ANALOG 0x811\n-\n-#define STM32F429_PA9_FUNC_GPIO 0x900\n-#define STM32F429_PA9_FUNC_TIM1_CH2 0x902\n-#define STM32F429_PA9_FUNC_I2C3_SMBA 0x905\n-#define STM32F429_PA9_FUNC_USART1_TX 0x908\n-#define STM32F429_PA9_FUNC_DCMI_D0 0x90e\n-#define STM32F429_PA9_FUNC_EVENTOUT 0x910\n-#define STM32F429_PA9_FUNC_ANALOG 0x911\n-\n-#define STM32F429_PA10_FUNC_GPIO 0xa00\n-#define STM32F429_PA10_FUNC_TIM1_CH3 0xa02\n-#define STM32F429_PA10_FUNC_USART1_RX 0xa08\n-#define STM32F429_PA10_FUNC_OTG_FS_ID 0xa0b\n-#define STM32F429_PA10_FUNC_DCMI_D1 0xa0e\n-#define STM32F429_PA10_FUNC_EVENTOUT 0xa10\n-#define STM32F429_PA10_FUNC_ANALOG 0xa11\n-\n-#define STM32F429_PA11_FUNC_GPIO 0xb00\n-#define STM32F429_PA11_FUNC_TIM1_CH4 0xb02\n-#define STM32F429_PA11_FUNC_USART1_CTS 0xb08\n-#define STM32F429_PA11_FUNC_CAN1_RX 0xb0a\n-#define STM32F429_PA11_FUNC_OTG_FS_DM 0xb0b\n-#define STM32F429_PA11_FUNC_LCD_R4 0xb0f\n-#define STM32F429_PA11_FUNC_EVENTOUT 0xb10\n-#define STM32F429_PA11_FUNC_ANALOG 0xb11\n-\n-#define STM32F429_PA12_FUNC_GPIO 0xc00\n-#define STM32F429_PA12_FUNC_TIM1_ETR 0xc02\n-#define STM32F429_PA12_FUNC_USART1_RTS 0xc08\n-#define STM32F429_PA12_FUNC_CAN1_TX 0xc0a\n-#define STM32F429_PA12_FUNC_OTG_FS_DP 0xc0b\n-#define STM32F429_PA12_FUNC_LCD_R5 0xc0f\n-#define STM32F429_PA12_FUNC_EVENTOUT 0xc10\n-#define STM32F429_PA12_FUNC_ANALOG 0xc11\n-\n-#define STM32F429_PA13_FUNC_GPIO 0xd00\n-#define STM32F429_PA13_FUNC_JTMS_SWDIO 0xd01\n-#define STM32F429_PA13_FUNC_EVENTOUT 0xd10\n-#define STM32F429_PA13_FUNC_ANALOG 0xd11\n-\n-#define STM32F429_PA14_FUNC_GPIO 0xe00\n-#define STM32F429_PA14_FUNC_JTCK_SWCLK 0xe01\n-#define STM32F429_PA14_FUNC_EVENTOUT 0xe10\n-#define STM32F429_PA14_FUNC_ANALOG 0xe11\n-\n-#define STM32F429_PA15_FUNC_GPIO 0xf00\n-#define STM32F429_PA15_FUNC_JTDI 0xf01\n-#define STM32F429_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02\n-#define STM32F429_PA15_FUNC_SPI1_NSS 0xf06\n-#define STM32F429_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07\n-#define STM32F429_PA15_FUNC_EVENTOUT 0xf10\n-#define STM32F429_PA15_FUNC_ANALOG 0xf11\n-\n-\n-\n-#define STM32F429_PB0_FUNC_GPIO 0x1000\n-#define STM32F429_PB0_FUNC_TIM1_CH2N 0x1002\n-#define STM32F429_PB0_FUNC_TIM3_CH3 0x1003\n-#define STM32F429_PB0_FUNC_TIM8_CH2N 0x1004\n-#define STM32F429_PB0_FUNC_LCD_R3 0x100a\n-#define STM32F429_PB0_FUNC_OTG_HS_ULPI_D1 0x100b\n-#define STM32F429_PB0_FUNC_ETH_MII_RXD2 0x100c\n-#define STM32F429_PB0_FUNC_EVENTOUT 0x1010\n-#define STM32F429_PB0_FUNC_ANALOG 0x1011\n-\n-#define STM32F429_PB1_FUNC_GPIO 0x1100\n-#define STM32F429_PB1_FUNC_TIM1_CH3N 0x1102\n-#define STM32F429_PB1_FUNC_TIM3_CH4 0x1103\n-#define STM32F429_PB1_FUNC_TIM8_CH3N 0x1104\n-#define STM32F429_PB1_FUNC_LCD_R6 0x110a\n-#define STM32F429_PB1_FUNC_OTG_HS_ULPI_D2 0x110b\n-#define STM32F429_PB1_FUNC_ETH_MII_RXD3 0x110c\n-#define STM32F429_PB1_FUNC_EVENTOUT 0x1110\n-#define STM32F429_PB1_FUNC_ANALOG 0x1111\n-\n-#define STM32F429_PB2_FUNC_GPIO 0x1200\n-#define STM32F429_PB2_FUNC_EVENTOUT 0x1210\n-#define STM32F429_PB2_FUNC_ANALOG 0x1211\n-\n-#define STM32F429_PB3_FUNC_GPIO 0x1300\n-#define STM32F429_PB3_FUNC_JTDO_TRACESWO 0x1301\n-#define STM32F429_PB3_FUNC_TIM2_CH2 0x1302\n-#define STM32F429_PB3_FUNC_SPI1_SCK 0x1306\n-#define STM32F429_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307\n-#define STM32F429_PB3_FUNC_EVENTOUT 0x1310\n-#define STM32F429_PB3_FUNC_ANALOG 0x1311\n-\n-#define STM32F429_PB4_FUNC_GPIO 0x1400\n-#define STM32F429_PB4_FUNC_NJTRST 0x1401\n-#define STM32F429_PB4_FUNC_TIM3_CH1 0x1403\n-#define STM32F429_PB4_FUNC_SPI1_MISO 0x1406\n-#define STM32F429_PB4_FUNC_SPI3_MISO 0x1407\n-#define STM32F429_PB4_FUNC_I2S3EXT_SD 0x1408\n-#define STM32F429_PB4_FUNC_EVENTOUT 0x1410\n-#define STM32F429_PB4_FUNC_ANALOG 0x1411\n-\n-#define STM32F429_PB5_FUNC_GPIO 0x1500\n-#define STM32F429_PB5_FUNC_TIM3_CH2 0x1503\n-#define STM32F429_PB5_FUNC_I2C1_SMBA 0x1505\n-#define STM32F429_PB5_FUNC_SPI1_MOSI 0x1506\n-#define STM32F429_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507\n-#define STM32F429_PB5_FUNC_CAN2_RX 0x150a\n-#define STM32F429_PB5_FUNC_OTG_HS_ULPI_D7 0x150b\n-#define STM32F429_PB5_FUNC_ETH_PPS_OUT 0x150c\n-#define STM32F429_PB5_FUNC_FMC_SDCKE1 0x150d\n-#define STM32F429_PB5_FUNC_DCMI_D10 0x150e\n-#define STM32F429_PB5_FUNC_EVENTOUT 0x1510\n-#define STM32F429_PB5_FUNC_ANALOG 0x1511\n-\n-#define STM32F429_PB6_FUNC_GPIO 0x1600\n-#define STM32F429_PB6_FUNC_TIM4_CH1 0x1603\n-#define STM32F429_PB6_FUNC_I2C1_SCL 0x1605\n-#define STM32F429_PB6_FUNC_USART1_TX 0x1608\n-#define STM32F429_PB6_FUNC_CAN2_TX 0x160a\n-#define STM32F429_PB6_FUNC_FMC_SDNE1 0x160d\n-#define STM32F429_PB6_FUNC_DCMI_D5 0x160e\n-#define STM32F429_PB6_FUNC_EVENTOUT 0x1610\n-#define STM32F429_PB6_FUNC_ANALOG 0x1611\n-\n-#define STM32F429_PB7_FUNC_GPIO 0x1700\n-#define STM32F429_PB7_FUNC_TIM4_CH2 0x1703\n-#define STM32F429_PB7_FUNC_I2C1_SDA 0x1705\n-#define STM32F429_PB7_FUNC_USART1_RX 0x1708\n-#define STM32F429_PB7_FUNC_FMC_NL 0x170d\n-#define STM32F429_PB7_FUNC_DCMI_VSYNC 0x170e\n-#define STM32F429_PB7_FUNC_EVENTOUT 0x1710\n-#define STM32F429_PB7_FUNC_ANALOG 0x1711\n-\n-#define STM32F429_PB8_FUNC_GPIO 0x1800\n-#define STM32F429_PB8_FUNC_TIM4_CH3 0x1803\n-#define STM32F429_PB8_FUNC_TIM10_CH1 0x1804\n-#define STM32F429_PB8_FUNC_I2C1_SCL 0x1805\n-#define STM32F429_PB8_FUNC_CAN1_RX 0x180a\n-#define STM32F429_PB8_FUNC_ETH_MII_TXD3 0x180c\n-#define STM32F429_PB8_FUNC_SDIO_D4 0x180d\n-#define STM32F429_PB8_FUNC_DCMI_D6 0x180e\n-#define STM32F429_PB8_FUNC_LCD_B6 0x180f\n-#define STM32F429_PB8_FUNC_EVENTOUT 0x1810\n-#define STM32F429_PB8_FUNC_ANALOG 0x1811\n-\n-#define STM32F429_PB9_FUNC_GPIO 0x1900\n-#define STM32F429_PB9_FUNC_TIM4_CH4 0x1903\n-#define STM32F429_PB9_FUNC_TIM11_CH1 0x1904\n-#define STM32F429_PB9_FUNC_I2C1_SDA 0x1905\n-#define STM32F429_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906\n-#define STM32F429_PB9_FUNC_CAN1_TX 0x190a\n-#define STM32F429_PB9_FUNC_SDIO_D5 0x190d\n-#define STM32F429_PB9_FUNC_DCMI_D7 0x190e\n-#define STM32F429_PB9_FUNC_LCD_B7 0x190f\n-#define STM32F429_PB9_FUNC_EVENTOUT 0x1910\n-#define STM32F429_PB9_FUNC_ANALOG 0x1911\n-\n-#define STM32F429_PB10_FUNC_GPIO 0x1a00\n-#define STM32F429_PB10_FUNC_TIM2_CH3 0x1a02\n-#define STM32F429_PB10_FUNC_I2C2_SCL 0x1a05\n-#define STM32F429_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06\n-#define STM32F429_PB10_FUNC_USART3_TX 0x1a08\n-#define STM32F429_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b\n-#define STM32F429_PB10_FUNC_ETH_MII_RX_ER 0x1a0c\n-#define STM32F429_PB10_FUNC_LCD_G4 0x1a0f\n-#define STM32F429_PB10_FUNC_EVENTOUT 0x1a10\n-#define STM32F429_PB10_FUNC_ANALOG 0x1a11\n-\n-#define STM32F429_PB11_FUNC_GPIO 0x1b00\n-#define STM32F429_PB11_FUNC_TIM2_CH4 0x1b02\n-#define STM32F429_PB11_FUNC_I2C2_SDA 0x1b05\n-#define STM32F429_PB11_FUNC_USART3_RX 0x1b08\n-#define STM32F429_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b\n-#define STM32F429_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c\n-#define STM32F429_PB11_FUNC_LCD_G5 0x1b0f\n-#define STM32F429_PB11_FUNC_EVENTOUT 0x1b10\n-#define STM32F429_PB11_FUNC_ANALOG 0x1b11\n-\n-#define STM32F429_PB12_FUNC_GPIO 0x1c00\n-#define STM32F429_PB12_FUNC_TIM1_BKIN 0x1c02\n-#define STM32F429_PB12_FUNC_I2C2_SMBA 0x1c05\n-#define STM32F429_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06\n-#define STM32F429_PB12_FUNC_USART3_CK 0x1c08\n-#define STM32F429_PB12_FUNC_CAN2_RX 0x1c0a\n-#define STM32F429_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b\n-#define STM32F429_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c\n-#define STM32F429_PB12_FUNC_OTG_HS_ID 0x1c0d\n-#define STM32F429_PB12_FUNC_EVENTOUT 0x1c10\n-#define STM32F429_PB12_FUNC_ANALOG 0x1c11\n-\n-#define STM32F429_PB13_FUNC_GPIO 0x1d00\n-#define STM32F429_PB13_FUNC_TIM1_CH1N 0x1d02\n-#define STM32F429_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06\n-#define STM32F429_PB13_FUNC_USART3_CTS 0x1d08\n-#define STM32F429_PB13_FUNC_CAN2_TX 0x1d0a\n-#define STM32F429_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b\n-#define STM32F429_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c\n-#define STM32F429_PB13_FUNC_EVENTOUT 0x1d10\n-#define STM32F429_PB13_FUNC_ANALOG 0x1d11\n-\n-#define STM32F429_PB14_FUNC_GPIO 0x1e00\n-#define STM32F429_PB14_FUNC_TIM1_CH2N 0x1e02\n-#define STM32F429_PB14_FUNC_TIM8_CH2N 0x1e04\n-#define STM32F429_PB14_FUNC_SPI2_MISO 0x1e06\n-#define STM32F429_PB14_FUNC_I2S2EXT_SD 0x1e07\n-#define STM32F429_PB14_FUNC_USART3_RTS 0x1e08\n-#define STM32F429_PB14_FUNC_TIM12_CH1 0x1e0a\n-#define STM32F429_PB14_FUNC_OTG_HS_DM 0x1e0d\n-#define STM32F429_PB14_FUNC_EVENTOUT 0x1e10\n-#define STM32F429_PB14_FUNC_ANALOG 0x1e11\n-\n-#define STM32F429_PB15_FUNC_GPIO 0x1f00\n-#define STM32F429_PB15_FUNC_RTC_REFIN 0x1f01\n-#define STM32F429_PB15_FUNC_TIM1_CH3N 0x1f02\n-#define STM32F429_PB15_FUNC_TIM8_CH3N 0x1f04\n-#define STM32F429_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06\n-#define STM32F429_PB15_FUNC_TIM12_CH2 0x1f0a\n-#define STM32F429_PB15_FUNC_OTG_HS_DP 0x1f0d\n-#define STM32F429_PB15_FUNC_EVENTOUT 0x1f10\n-#define STM32F429_PB15_FUNC_ANALOG 0x1f11\n-\n-\n-\n-#define STM32F429_PC0_FUNC_GPIO 0x2000\n-#define STM32F429_PC0_FUNC_OTG_HS_ULPI_STP 0x200b\n-#define STM32F429_PC0_FUNC_FMC_SDNWE 0x200d\n-#define STM32F429_PC0_FUNC_EVENTOUT 0x2010\n-#define STM32F429_PC0_FUNC_ANALOG 0x2011\n-\n-#define STM32F429_PC1_FUNC_GPIO 0x2100\n-#define STM32F429_PC1_FUNC_ETH_MDC 0x210c\n-#define STM32F429_PC1_FUNC_EVENTOUT 0x2110\n-#define STM32F429_PC1_FUNC_ANALOG 0x2111\n-\n-#define STM32F429_PC2_FUNC_GPIO 0x2200\n-#define STM32F429_PC2_FUNC_SPI2_MISO 0x2206\n-#define STM32F429_PC2_FUNC_I2S2EXT_SD 0x2207\n-#define STM32F429_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b\n-#define STM32F429_PC2_FUNC_ETH_MII_TXD2 0x220c\n-#define STM32F429_PC2_FUNC_FMC_SDNE0 0x220d\n-#define STM32F429_PC2_FUNC_EVENTOUT 0x2210\n-#define STM32F429_PC2_FUNC_ANALOG 0x2211\n-\n-#define STM32F429_PC3_FUNC_GPIO 0x2300\n-#define STM32F429_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306\n-#define STM32F429_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b\n-#define STM32F429_PC3_FUNC_ETH_MII_TX_CLK 0x230c\n-#define STM32F429_PC3_FUNC_FMC_SDCKE0 0x230d\n-#define STM32F429_PC3_FUNC_EVENTOUT 0x2310\n-#define STM32F429_PC3_FUNC_ANALOG 0x2311\n-\n-#define STM32F429_PC4_FUNC_GPIO 0x2400\n-#define STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c\n-#define STM32F429_PC4_FUNC_EVENTOUT 0x2410\n-#define STM32F429_PC4_FUNC_ANALOG 0x2411\n-\n-#define STM32F429_PC5_FUNC_GPIO 0x2500\n-#define STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c\n-#define STM32F429_PC5_FUNC_EVENTOUT 0x2510\n-#define STM32F429_PC5_FUNC_ANALOG 0x2511\n-\n-#define STM32F429_PC6_FUNC_GPIO 0x2600\n-#define STM32F429_PC6_FUNC_TIM3_CH1 0x2603\n-#define STM32F429_PC6_FUNC_TIM8_CH1 0x2604\n-#define STM32F429_PC6_FUNC_I2S2_MCK 0x2606\n-#define STM32F429_PC6_FUNC_USART6_TX 0x2609\n-#define STM32F429_PC6_FUNC_SDIO_D6 0x260d\n-#define STM32F429_PC6_FUNC_DCMI_D0 0x260e\n-#define STM32F429_PC6_FUNC_LCD_HSYNC 0x260f\n-#define STM32F429_PC6_FUNC_EVENTOUT 0x2610\n-#define STM32F429_PC6_FUNC_ANALOG 0x2611\n-\n-#define STM32F429_PC7_FUNC_GPIO 0x2700\n-#define STM32F429_PC7_FUNC_TIM3_CH2 0x2703\n-#define STM32F429_PC7_FUNC_TIM8_CH2 0x2704\n-#define STM32F429_PC7_FUNC_I2S3_MCK 0x2707\n-#define STM32F429_PC7_FUNC_USART6_RX 0x2709\n-#define STM32F429_PC7_FUNC_SDIO_D7 0x270d\n-#define STM32F429_PC7_FUNC_DCMI_D1 0x270e\n-#define STM32F429_PC7_FUNC_LCD_G6 0x270f\n-#define STM32F429_PC7_FUNC_EVENTOUT 0x2710\n-#define STM32F429_PC7_FUNC_ANALOG 0x2711\n-\n-#define STM32F429_PC8_FUNC_GPIO 0x2800\n-#define STM32F429_PC8_FUNC_TIM3_CH3 0x2803\n-#define STM32F429_PC8_FUNC_TIM8_CH3 0x2804\n-#define STM32F429_PC8_FUNC_USART6_CK 0x2809\n-#define STM32F429_PC8_FUNC_SDIO_D0 0x280d\n-#define STM32F429_PC8_FUNC_DCMI_D2 0x280e\n-#define STM32F429_PC8_FUNC_EVENTOUT 0x2810\n-#define STM32F429_PC8_FUNC_ANALOG 0x2811\n-\n-#define STM32F429_PC9_FUNC_GPIO 0x2900\n-#define STM32F429_PC9_FUNC_MCO2 0x2901\n-#define STM32F429_PC9_FUNC_TIM3_CH4 0x2903\n-#define STM32F429_PC9_FUNC_TIM8_CH4 0x2904\n-#define STM32F429_PC9_FUNC_I2C3_SDA 0x2905\n-#define STM32F429_PC9_FUNC_I2S_CKIN 0x2906\n-#define STM32F429_PC9_FUNC_SDIO_D1 0x290d\n-#define STM32F429_PC9_FUNC_DCMI_D3 0x290e\n-#define STM32F429_PC9_FUNC_EVENTOUT 0x2910\n-#define STM32F429_PC9_FUNC_ANALOG 0x2911\n-\n-#define STM32F429_PC10_FUNC_GPIO 0x2a00\n-#define STM32F429_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07\n-#define STM32F429_PC10_FUNC_USART3_TX 0x2a08\n-#define STM32F429_PC10_FUNC_UART4_TX 0x2a09\n-#define STM32F429_PC10_FUNC_SDIO_D2 0x2a0d\n-#define STM32F429_PC10_FUNC_DCMI_D8 0x2a0e\n-#define STM32F429_PC10_FUNC_LCD_R2 0x2a0f\n-#define STM32F429_PC10_FUNC_EVENTOUT 0x2a10\n-#define STM32F429_PC10_FUNC_ANALOG 0x2a11\n-\n-#define STM32F429_PC11_FUNC_GPIO 0x2b00\n-#define STM32F429_PC11_FUNC_I2S3EXT_SD 0x2b06\n-#define STM32F429_PC11_FUNC_SPI3_MISO 0x2b07\n-#define STM32F429_PC11_FUNC_USART3_RX 0x2b08\n-#define STM32F429_PC11_FUNC_UART4_RX 0x2b09\n-#define STM32F429_PC11_FUNC_SDIO_D3 0x2b0d\n-#define STM32F429_PC11_FUNC_DCMI_D4 0x2b0e\n-#define STM32F429_PC11_FUNC_EVENTOUT 0x2b10\n-#define STM32F429_PC11_FUNC_ANALOG 0x2b11\n-\n-#define STM32F429_PC12_FUNC_GPIO 0x2c00\n-#define STM32F429_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07\n-#define STM32F429_PC12_FUNC_USART3_CK 0x2c08\n-#define STM32F429_PC12_FUNC_UART5_TX 0x2c09\n-#define STM32F429_PC12_FUNC_SDIO_CK 0x2c0d\n-#define STM32F429_PC12_FUNC_DCMI_D9 0x2c0e\n-#define STM32F429_PC12_FUNC_EVENTOUT 0x2c10\n-#define STM32F429_PC12_FUNC_ANALOG 0x2c11\n-\n-#define STM32F429_PC13_FUNC_GPIO 0x2d00\n-#define STM32F429_PC13_FUNC_EVENTOUT 0x2d10\n-#define STM32F429_PC13_FUNC_ANALOG 0x2d11\n-\n-#define STM32F429_PC14_FUNC_GPIO 0x2e00\n-#define STM32F429_PC14_FUNC_EVENTOUT 0x2e10\n-#define STM32F429_PC14_FUNC_ANALOG 0x2e11\n-\n-#define STM32F429_PC15_FUNC_GPIO 0x2f00\n-#define STM32F429_PC15_FUNC_EVENTOUT 0x2f10\n-#define STM32F429_PC15_FUNC_ANALOG 0x2f11\n-\n-\n-\n-#define STM32F429_PD0_FUNC_GPIO 0x3000\n-#define STM32F429_PD0_FUNC_CAN1_RX 0x300a\n-#define STM32F429_PD0_FUNC_FMC_D2 0x300d\n-#define STM32F429_PD0_FUNC_EVENTOUT 0x3010\n-#define STM32F429_PD0_FUNC_ANALOG 0x3011\n-\n-#define STM32F429_PD1_FUNC_GPIO 0x3100\n-#define STM32F429_PD1_FUNC_CAN1_TX 0x310a\n-#define STM32F429_PD1_FUNC_FMC_D3 0x310d\n-#define STM32F429_PD1_FUNC_EVENTOUT 0x3110\n-#define STM32F429_PD1_FUNC_ANALOG 0x3111\n-\n-#define STM32F429_PD2_FUNC_GPIO 0x3200\n-#define STM32F429_PD2_FUNC_TIM3_ETR 0x3203\n-#define STM32F429_PD2_FUNC_UART5_RX 0x3209\n-#define STM32F429_PD2_FUNC_SDIO_CMD 0x320d\n-#define STM32F429_PD2_FUNC_DCMI_D11 0x320e\n-#define STM32F429_PD2_FUNC_EVENTOUT 0x3210\n-#define STM32F429_PD2_FUNC_ANALOG 0x3211\n-\n-#define STM32F429_PD3_FUNC_GPIO 0x3300\n-#define STM32F429_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306\n-#define STM32F429_PD3_FUNC_USART2_CTS 0x3308\n-#define STM32F429_PD3_FUNC_FMC_CLK 0x330d\n-#define STM32F429_PD3_FUNC_DCMI_D5 0x330e\n-#define STM32F429_PD3_FUNC_LCD_G7 0x330f\n-#define STM32F429_PD3_FUNC_EVENTOUT 0x3310\n-#define STM32F429_PD3_FUNC_ANALOG 0x3311\n-\n-#define STM32F429_PD4_FUNC_GPIO 0x3400\n-#define STM32F429_PD4_FUNC_USART2_RTS 0x3408\n-#define STM32F429_PD4_FUNC_FMC_NOE 0x340d\n-#define STM32F429_PD4_FUNC_EVENTOUT 0x3410\n-#define STM32F429_PD4_FUNC_ANALOG 0x3411\n-\n-#define STM32F429_PD5_FUNC_GPIO 0x3500\n-#define STM32F429_PD5_FUNC_USART2_TX 0x3508\n-#define STM32F429_PD5_FUNC_FMC_NWE 0x350d\n-#define STM32F429_PD5_FUNC_EVENTOUT 0x3510\n-#define STM32F429_PD5_FUNC_ANALOG 0x3511\n-\n-#define STM32F429_PD6_FUNC_GPIO 0x3600\n-#define STM32F429_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606\n-#define STM32F429_PD6_FUNC_SAI1_SD_A 0x3607\n-#define STM32F429_PD6_FUNC_USART2_RX 0x3608\n-#define STM32F429_PD6_FUNC_FMC_NWAIT 0x360d\n-#define STM32F429_PD6_FUNC_DCMI_D10 0x360e\n-#define STM32F429_PD6_FUNC_LCD_B2 0x360f\n-#define STM32F429_PD6_FUNC_EVENTOUT 0x3610\n-#define STM32F429_PD6_FUNC_ANALOG 0x3611\n-\n-#define STM32F429_PD7_FUNC_GPIO 0x3700\n-#define STM32F429_PD7_FUNC_USART2_CK 0x3708\n-#define STM32F429_PD7_FUNC_FMC_NE1_FMC_NCE2 0x370d\n-#define STM32F429_PD7_FUNC_EVENTOUT 0x3710\n-#define STM32F429_PD7_FUNC_ANALOG 0x3711\n-\n-#define STM32F429_PD8_FUNC_GPIO 0x3800\n-#define STM32F429_PD8_FUNC_USART3_TX 0x3808\n-#define STM32F429_PD8_FUNC_FMC_D13 0x380d\n-#define STM32F429_PD8_FUNC_EVENTOUT 0x3810\n-#define STM32F429_PD8_FUNC_ANALOG 0x3811\n-\n-#define STM32F429_PD9_FUNC_GPIO 0x3900\n-#define STM32F429_PD9_FUNC_USART3_RX 0x3908\n-#define STM32F429_PD9_FUNC_FMC_D14 0x390d\n-#define STM32F429_PD9_FUNC_EVENTOUT 0x3910\n-#define STM32F429_PD9_FUNC_ANALOG 0x3911\n-\n-#define STM32F429_PD10_FUNC_GPIO 0x3a00\n-#define STM32F429_PD10_FUNC_USART3_CK 0x3a08\n-#define STM32F429_PD10_FUNC_FMC_D15 0x3a0d\n-#define STM32F429_PD10_FUNC_LCD_B3 0x3a0f\n-#define STM32F429_PD10_FUNC_EVENTOUT 0x3a10\n-#define STM32F429_PD10_FUNC_ANALOG 0x3a11\n-\n-#define STM32F429_PD11_FUNC_GPIO 0x3b00\n-#define STM32F429_PD11_FUNC_USART3_CTS 0x3b08\n-#define STM32F429_PD11_FUNC_FMC_A16 0x3b0d\n-#define STM32F429_PD11_FUNC_EVENTOUT 0x3b10\n-#define STM32F429_PD11_FUNC_ANALOG 0x3b11\n-\n-#define STM32F429_PD12_FUNC_GPIO 0x3c00\n-#define STM32F429_PD12_FUNC_TIM4_CH1 0x3c03\n-#define STM32F429_PD12_FUNC_USART3_RTS 0x3c08\n-#define STM32F429_PD12_FUNC_FMC_A17 0x3c0d\n-#define STM32F429_PD12_FUNC_EVENTOUT 0x3c10\n-#define STM32F429_PD12_FUNC_ANALOG 0x3c11\n-\n-#define STM32F429_PD13_FUNC_GPIO 0x3d00\n-#define STM32F429_PD13_FUNC_TIM4_CH2 0x3d03\n-#define STM32F429_PD13_FUNC_FMC_A18 0x3d0d\n-#define STM32F429_PD13_FUNC_EVENTOUT 0x3d10\n-#define STM32F429_PD13_FUNC_ANALOG 0x3d11\n-\n-#define STM32F429_PD14_FUNC_GPIO 0x3e00\n-#define STM32F429_PD14_FUNC_TIM4_CH3 0x3e03\n-#define STM32F429_PD14_FUNC_FMC_D0 0x3e0d\n-#define STM32F429_PD14_FUNC_EVENTOUT 0x3e10\n-#define STM32F429_PD14_FUNC_ANALOG 0x3e11\n-\n-#define STM32F429_PD15_FUNC_GPIO 0x3f00\n-#define STM32F429_PD15_FUNC_TIM4_CH4 0x3f03\n-#define STM32F429_PD15_FUNC_FMC_D1 0x3f0d\n-#define STM32F429_PD15_FUNC_EVENTOUT 0x3f10\n-#define STM32F429_PD15_FUNC_ANALOG 0x3f11\n-\n-\n-\n-#define STM32F429_PE0_FUNC_GPIO 0x4000\n-#define STM32F429_PE0_FUNC_TIM4_ETR 0x4003\n-#define STM32F429_PE0_FUNC_UART8_RX 0x4009\n-#define STM32F429_PE0_FUNC_FMC_NBL0 0x400d\n-#define STM32F429_PE0_FUNC_DCMI_D2 0x400e\n-#define STM32F429_PE0_FUNC_EVENTOUT 0x4010\n-#define STM32F429_PE0_FUNC_ANALOG 0x4011\n-\n-#define STM32F429_PE1_FUNC_GPIO 0x4100\n-#define STM32F429_PE1_FUNC_UART8_TX 0x4109\n-#define STM32F429_PE1_FUNC_FMC_NBL1 0x410d\n-#define STM32F429_PE1_FUNC_DCMI_D3 0x410e\n-#define STM32F429_PE1_FUNC_EVENTOUT 0x4110\n-#define STM32F429_PE1_FUNC_ANALOG 0x4111\n-\n-#define STM32F429_PE2_FUNC_GPIO 0x4200\n-#define STM32F429_PE2_FUNC_TRACECLK 0x4201\n-#define STM32F429_PE2_FUNC_SPI4_SCK 0x4206\n-#define STM32F429_PE2_FUNC_SAI1_MCLK_A 0x4207\n-#define STM32F429_PE2_FUNC_ETH_MII_TXD3 0x420c\n-#define STM32F429_PE2_FUNC_FMC_A23 0x420d\n-#define STM32F429_PE2_FUNC_EVENTOUT 0x4210\n-#define STM32F429_PE2_FUNC_ANALOG 0x4211\n-\n-#define STM32F429_PE3_FUNC_GPIO 0x4300\n-#define STM32F429_PE3_FUNC_TRACED0 0x4301\n-#define STM32F429_PE3_FUNC_SAI1_SD_B 0x4307\n-#define STM32F429_PE3_FUNC_FMC_A19 0x430d\n-#define STM32F429_PE3_FUNC_EVENTOUT 0x4310\n-#define STM32F429_PE3_FUNC_ANALOG 0x4311\n-\n-#define STM32F429_PE4_FUNC_GPIO 0x4400\n-#define STM32F429_PE4_FUNC_TRACED1 0x4401\n-#define STM32F429_PE4_FUNC_SPI4_NSS 0x4406\n-#define STM32F429_PE4_FUNC_SAI1_FS_A 0x4407\n-#define STM32F429_PE4_FUNC_FMC_A20 0x440d\n-#define STM32F429_PE4_FUNC_DCMI_D4 0x440e\n-#define STM32F429_PE4_FUNC_LCD_B0 0x440f\n-#define STM32F429_PE4_FUNC_EVENTOUT 0x4410\n-#define STM32F429_PE4_FUNC_ANALOG 0x4411\n-\n-#define STM32F429_PE5_FUNC_GPIO 0x4500\n-#define STM32F429_PE5_FUNC_TRACED2 0x4501\n-#define STM32F429_PE5_FUNC_TIM9_CH1 0x4504\n-#define STM32F429_PE5_FUNC_SPI4_MISO 0x4506\n-#define STM32F429_PE5_FUNC_SAI1_SCK_A 0x4507\n-#define STM32F429_PE5_FUNC_FMC_A21 0x450d\n-#define STM32F429_PE5_FUNC_DCMI_D6 0x450e\n-#define STM32F429_PE5_FUNC_LCD_G0 0x450f\n-#define STM32F429_PE5_FUNC_EVENTOUT 0x4510\n-#define STM32F429_PE5_FUNC_ANALOG 0x4511\n-\n-#define STM32F429_PE6_FUNC_GPIO 0x4600\n-#define STM32F429_PE6_FUNC_TRACED3 0x4601\n-#define STM32F429_PE6_FUNC_TIM9_CH2 0x4604\n-#define STM32F429_PE6_FUNC_SPI4_MOSI 0x4606\n-#define STM32F429_PE6_FUNC_SAI1_SD_A 0x4607\n-#define STM32F429_PE6_FUNC_FMC_A22 0x460d\n-#define STM32F429_PE6_FUNC_DCMI_D7 0x460e\n-#define STM32F429_PE6_FUNC_LCD_G1 0x460f\n-#define STM32F429_PE6_FUNC_EVENTOUT 0x4610\n-#define STM32F429_PE6_FUNC_ANALOG 0x4611\n-\n-#define STM32F429_PE7_FUNC_GPIO 0x4700\n-#define STM32F429_PE7_FUNC_TIM1_ETR 0x4702\n-#define STM32F429_PE7_FUNC_UART7_RX 0x4709\n-#define STM32F429_PE7_FUNC_FMC_D4 0x470d\n-#define STM32F429_PE7_FUNC_EVENTOUT 0x4710\n-#define STM32F429_PE7_FUNC_ANALOG 0x4711\n-\n-#define STM32F429_PE8_FUNC_GPIO 0x4800\n-#define STM32F429_PE8_FUNC_TIM1_CH1N 0x4802\n-#define STM32F429_PE8_FUNC_UART7_TX 0x4809\n-#define STM32F429_PE8_FUNC_FMC_D5 0x480d\n-#define STM32F429_PE8_FUNC_EVENTOUT 0x4810\n-#define STM32F429_PE8_FUNC_ANALOG 0x4811\n-\n-#define STM32F429_PE9_FUNC_GPIO 0x4900\n-#define STM32F429_PE9_FUNC_TIM1_CH1 0x4902\n-#define STM32F429_PE9_FUNC_FMC_D6 0x490d\n-#define STM32F429_PE9_FUNC_EVENTOUT 0x4910\n-#define STM32F429_PE9_FUNC_ANALOG 0x4911\n-\n-#define STM32F429_PE10_FUNC_GPIO 0x4a00\n-#define STM32F429_PE10_FUNC_TIM1_CH2N 0x4a02\n-#define STM32F429_PE10_FUNC_FMC_D7 0x4a0d\n-#define STM32F429_PE10_FUNC_EVENTOUT 0x4a10\n-#define STM32F429_PE10_FUNC_ANALOG 0x4a11\n-\n-#define STM32F429_PE11_FUNC_GPIO 0x4b00\n-#define STM32F429_PE11_FUNC_TIM1_CH2 0x4b02\n-#define STM32F429_PE11_FUNC_SPI4_NSS 0x4b06\n-#define STM32F429_PE11_FUNC_FMC_D8 0x4b0d\n-#define STM32F429_PE11_FUNC_LCD_G3 0x4b0f\n-#define STM32F429_PE11_FUNC_EVENTOUT 0x4b10\n-#define STM32F429_PE11_FUNC_ANALOG 0x4b11\n-\n-#define STM32F429_PE12_FUNC_GPIO 0x4c00\n-#define STM32F429_PE12_FUNC_TIM1_CH3N 0x4c02\n-#define STM32F429_PE12_FUNC_SPI4_SCK 0x4c06\n-#define STM32F429_PE12_FUNC_FMC_D9 0x4c0d\n-#define STM32F429_PE12_FUNC_LCD_B4 0x4c0f\n-#define STM32F429_PE12_FUNC_EVENTOUT 0x4c10\n-#define STM32F429_PE12_FUNC_ANALOG 0x4c11\n-\n-#define STM32F429_PE13_FUNC_GPIO 0x4d00\n-#define STM32F429_PE13_FUNC_TIM1_CH3 0x4d02\n-#define STM32F429_PE13_FUNC_SPI4_MISO 0x4d06\n-#define STM32F429_PE13_FUNC_FMC_D10 0x4d0d\n-#define STM32F429_PE13_FUNC_LCD_DE 0x4d0f\n-#define STM32F429_PE13_FUNC_EVENTOUT 0x4d10\n-#define STM32F429_PE13_FUNC_ANALOG 0x4d11\n-\n-#define STM32F429_PE14_FUNC_GPIO 0x4e00\n-#define STM32F429_PE14_FUNC_TIM1_CH4 0x4e02\n-#define STM32F429_PE14_FUNC_SPI4_MOSI 0x4e06\n-#define STM32F429_PE14_FUNC_FMC_D11 0x4e0d\n-#define STM32F429_PE14_FUNC_LCD_CLK 0x4e0f\n-#define STM32F429_PE14_FUNC_EVENTOUT 0x4e10\n-#define STM32F429_PE14_FUNC_ANALOG 0x4e11\n-\n-#define STM32F429_PE15_FUNC_GPIO 0x4f00\n-#define STM32F429_PE15_FUNC_TIM1_BKIN 0x4f02\n-#define STM32F429_PE15_FUNC_FMC_D12 0x4f0d\n-#define STM32F429_PE15_FUNC_LCD_R7 0x4f0f\n-#define STM32F429_PE15_FUNC_EVENTOUT 0x4f10\n-#define STM32F429_PE15_FUNC_ANALOG 0x4f11\n-\n-\n-\n-#define STM32F429_PF0_FUNC_GPIO 0x5000\n-#define STM32F429_PF0_FUNC_I2C2_SDA 0x5005\n-#define STM32F429_PF0_FUNC_FMC_A0 0x500d\n-#define STM32F429_PF0_FUNC_EVENTOUT 0x5010\n-#define STM32F429_PF0_FUNC_ANALOG 0x5011\n-\n-#define STM32F429_PF1_FUNC_GPIO 0x5100\n-#define STM32F429_PF1_FUNC_I2C2_SCL 0x5105\n-#define STM32F429_PF1_FUNC_FMC_A1 0x510d\n-#define STM32F429_PF1_FUNC_EVENTOUT 0x5110\n-#define STM32F429_PF1_FUNC_ANALOG 0x5111\n-\n-#define STM32F429_PF2_FUNC_GPIO 0x5200\n-#define STM32F429_PF2_FUNC_I2C2_SMBA 0x5205\n-#define STM32F429_PF2_FUNC_FMC_A2 0x520d\n-#define STM32F429_PF2_FUNC_EVENTOUT 0x5210\n-#define STM32F429_PF2_FUNC_ANALOG 0x5211\n-\n-#define STM32F429_PF3_FUNC_GPIO 0x5300\n-#define STM32F429_PF3_FUNC_FMC_A3 0x530d\n-#define STM32F429_PF3_FUNC_EVENTOUT 0x5310\n-#define STM32F429_PF3_FUNC_ANALOG 0x5311\n-\n-#define STM32F429_PF4_FUNC_GPIO 0x5400\n-#define STM32F429_PF4_FUNC_FMC_A4 0x540d\n-#define STM32F429_PF4_FUNC_EVENTOUT 0x5410\n-#define STM32F429_PF4_FUNC_ANALOG 0x5411\n-\n-#define STM32F429_PF5_FUNC_GPIO 0x5500\n-#define STM32F429_PF5_FUNC_FMC_A5 0x550d\n-#define STM32F429_PF5_FUNC_EVENTOUT 0x5510\n-#define STM32F429_PF5_FUNC_ANALOG 0x5511\n-\n-#define STM32F429_PF6_FUNC_GPIO 0x5600\n-#define STM32F429_PF6_FUNC_TIM10_CH1 0x5604\n-#define STM32F429_PF6_FUNC_SPI5_NSS 0x5606\n-#define STM32F429_PF6_FUNC_SAI1_SD_B 0x5607\n-#define STM32F429_PF6_FUNC_UART7_RX 0x5609\n-#define STM32F429_PF6_FUNC_FMC_NIORD 0x560d\n-#define STM32F429_PF6_FUNC_EVENTOUT 0x5610\n-#define STM32F429_PF6_FUNC_ANALOG 0x5611\n-\n-#define STM32F429_PF7_FUNC_GPIO 0x5700\n-#define STM32F429_PF7_FUNC_TIM11_CH1 0x5704\n-#define STM32F429_PF7_FUNC_SPI5_SCK 0x5706\n-#define STM32F429_PF7_FUNC_SAI1_MCLK_B 0x5707\n-#define STM32F429_PF7_FUNC_UART7_TX 0x5709\n-#define STM32F429_PF7_FUNC_FMC_NREG 0x570d\n-#define STM32F429_PF7_FUNC_EVENTOUT 0x5710\n-#define STM32F429_PF7_FUNC_ANALOG 0x5711\n-\n-#define STM32F429_PF8_FUNC_GPIO 0x5800\n-#define STM32F429_PF8_FUNC_SPI5_MISO 0x5806\n-#define STM32F429_PF8_FUNC_SAI1_SCK_B 0x5807\n-#define STM32F429_PF8_FUNC_TIM13_CH1 0x580a\n-#define STM32F429_PF8_FUNC_FMC_NIOWR 0x580d\n-#define STM32F429_PF8_FUNC_EVENTOUT 0x5810\n-#define STM32F429_PF8_FUNC_ANALOG 0x5811\n-\n-#define STM32F429_PF9_FUNC_GPIO 0x5900\n-#define STM32F429_PF9_FUNC_SPI5_MOSI 0x5906\n-#define STM32F429_PF9_FUNC_SAI1_FS_B 0x5907\n-#define STM32F429_PF9_FUNC_TIM14_CH1 0x590a\n-#define STM32F429_PF9_FUNC_FMC_CD 0x590d\n-#define STM32F429_PF9_FUNC_EVENTOUT 0x5910\n-#define STM32F429_PF9_FUNC_ANALOG 0x5911\n-\n-#define STM32F429_PF10_FUNC_GPIO 0x5a00\n-#define STM32F429_PF10_FUNC_FMC_INTR 0x5a0d\n-#define STM32F429_PF10_FUNC_DCMI_D11 0x5a0e\n-#define STM32F429_PF10_FUNC_LCD_DE 0x5a0f\n-#define STM32F429_PF10_FUNC_EVENTOUT 0x5a10\n-#define STM32F429_PF10_FUNC_ANALOG 0x5a11\n-\n-#define STM32F429_PF11_FUNC_GPIO 0x5b00\n-#define STM32F429_PF11_FUNC_SPI5_MOSI 0x5b06\n-#define STM32F429_PF11_FUNC_FMC_SDNRAS 0x5b0d\n-#define STM32F429_PF11_FUNC_DCMI_D12 0x5b0e\n-#define STM32F429_PF11_FUNC_EVENTOUT 0x5b10\n-#define STM32F429_PF11_FUNC_ANALOG 0x5b11\n-\n-#define STM32F429_PF12_FUNC_GPIO 0x5c00\n-#define STM32F429_PF12_FUNC_FMC_A6 0x5c0d\n-#define STM32F429_PF12_FUNC_EVENTOUT 0x5c10\n-#define STM32F429_PF12_FUNC_ANALOG 0x5c11\n-\n-#define STM32F429_PF13_FUNC_GPIO 0x5d00\n-#define STM32F429_PF13_FUNC_FMC_A7 0x5d0d\n-#define STM32F429_PF13_FUNC_EVENTOUT 0x5d10\n-#define STM32F429_PF13_FUNC_ANALOG 0x5d11\n-\n-#define STM32F429_PF14_FUNC_GPIO 0x5e00\n-#define STM32F429_PF14_FUNC_FMC_A8 0x5e0d\n-#define STM32F429_PF14_FUNC_EVENTOUT 0x5e10\n-#define STM32F429_PF14_FUNC_ANALOG 0x5e11\n-\n-#define STM32F429_PF15_FUNC_GPIO 0x5f00\n-#define STM32F429_PF15_FUNC_FMC_A9 0x5f0d\n-#define STM32F429_PF15_FUNC_EVENTOUT 0x5f10\n-#define STM32F429_PF15_FUNC_ANALOG 0x5f11\n-\n-\n-\n-#define STM32F429_PG0_FUNC_GPIO 0x6000\n-#define STM32F429_PG0_FUNC_FMC_A10 0x600d\n-#define STM32F429_PG0_FUNC_EVENTOUT 0x6010\n-#define STM32F429_PG0_FUNC_ANALOG 0x6011\n-\n-#define STM32F429_PG1_FUNC_GPIO 0x6100\n-#define STM32F429_PG1_FUNC_FMC_A11 0x610d\n-#define STM32F429_PG1_FUNC_EVENTOUT 0x6110\n-#define STM32F429_PG1_FUNC_ANALOG 0x6111\n-\n-#define STM32F429_PG2_FUNC_GPIO 0x6200\n-#define STM32F429_PG2_FUNC_FMC_A12 0x620d\n-#define STM32F429_PG2_FUNC_EVENTOUT 0x6210\n-#define STM32F429_PG2_FUNC_ANALOG 0x6211\n-\n-#define STM32F429_PG3_FUNC_GPIO 0x6300\n-#define STM32F429_PG3_FUNC_FMC_A13 0x630d\n-#define STM32F429_PG3_FUNC_EVENTOUT 0x6310\n-#define STM32F429_PG3_FUNC_ANALOG 0x6311\n-\n-#define STM32F429_PG4_FUNC_GPIO 0x6400\n-#define STM32F429_PG4_FUNC_FMC_A14_FMC_BA0 0x640d\n-#define STM32F429_PG4_FUNC_EVENTOUT 0x6410\n-#define STM32F429_PG4_FUNC_ANALOG 0x6411\n-\n-#define STM32F429_PG5_FUNC_GPIO 0x6500\n-#define STM32F429_PG5_FUNC_FMC_A15_FMC_BA1 0x650d\n-#define STM32F429_PG5_FUNC_EVENTOUT 0x6510\n-#define STM32F429_PG5_FUNC_ANALOG 0x6511\n-\n-#define STM32F429_PG6_FUNC_GPIO 0x6600\n-#define STM32F429_PG6_FUNC_FMC_INT2 0x660d\n-#define STM32F429_PG6_FUNC_DCMI_D12 0x660e\n-#define STM32F429_PG6_FUNC_LCD_R7 0x660f\n-#define STM32F429_PG6_FUNC_EVENTOUT 0x6610\n-#define STM32F429_PG6_FUNC_ANALOG 0x6611\n-\n-#define STM32F429_PG7_FUNC_GPIO 0x6700\n-#define STM32F429_PG7_FUNC_USART6_CK 0x6709\n-#define STM32F429_PG7_FUNC_FMC_INT3 0x670d\n-#define STM32F429_PG7_FUNC_DCMI_D13 0x670e\n-#define STM32F429_PG7_FUNC_LCD_CLK 0x670f\n-#define STM32F429_PG7_FUNC_EVENTOUT 0x6710\n-#define STM32F429_PG7_FUNC_ANALOG 0x6711\n-\n-#define STM32F429_PG8_FUNC_GPIO 0x6800\n-#define STM32F429_PG8_FUNC_SPI6_NSS 0x6806\n-#define STM32F429_PG8_FUNC_USART6_RTS 0x6809\n-#define STM32F429_PG8_FUNC_ETH_PPS_OUT 0x680c\n-#define STM32F429_PG8_FUNC_FMC_SDCLK 0x680d\n-#define STM32F429_PG8_FUNC_EVENTOUT 0x6810\n-#define STM32F429_PG8_FUNC_ANALOG 0x6811\n-\n-#define STM32F429_PG9_FUNC_GPIO 0x6900\n-#define STM32F429_PG9_FUNC_USART6_RX 0x6909\n-#define STM32F429_PG9_FUNC_FMC_NE2_FMC_NCE3 0x690d\n-#define STM32F429_PG9_FUNC_DCMI_VSYNC 0x690e\n-#define STM32F429_PG9_FUNC_EVENTOUT 0x6910\n-#define STM32F429_PG9_FUNC_ANALOG 0x6911\n-\n-#define STM32F429_PG10_FUNC_GPIO 0x6a00\n-#define STM32F429_PG10_FUNC_LCD_G3 0x6a0a\n-#define STM32F429_PG10_FUNC_FMC_NCE4_1_FMC_NE3 0x6a0d\n-#define STM32F429_PG10_FUNC_DCMI_D2 0x6a0e\n-#define STM32F429_PG10_FUNC_LCD_B2 0x6a0f\n-#define STM32F429_PG10_FUNC_EVENTOUT 0x6a10\n-#define STM32F429_PG10_FUNC_ANALOG 0x6a11\n-\n-#define STM32F429_PG11_FUNC_GPIO 0x6b00\n-#define STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c\n-#define STM32F429_PG11_FUNC_FMC_NCE4_2 0x6b0d\n-#define STM32F429_PG11_FUNC_DCMI_D3 0x6b0e\n-#define STM32F429_PG11_FUNC_LCD_B3 0x6b0f\n-#define STM32F429_PG11_FUNC_EVENTOUT 0x6b10\n-#define STM32F429_PG11_FUNC_ANALOG 0x6b11\n-\n-#define STM32F429_PG12_FUNC_GPIO 0x6c00\n-#define STM32F429_PG12_FUNC_SPI6_MISO 0x6c06\n-#define STM32F429_PG12_FUNC_USART6_RTS 0x6c09\n-#define STM32F429_PG12_FUNC_LCD_B4 0x6c0a\n-#define STM32F429_PG12_FUNC_FMC_NE4 0x6c0d\n-#define STM32F429_PG12_FUNC_LCD_B1 0x6c0f\n-#define STM32F429_PG12_FUNC_EVENTOUT 0x6c10\n-#define STM32F429_PG12_FUNC_ANALOG 0x6c11\n-\n-#define STM32F429_PG13_FUNC_GPIO 0x6d00\n-#define STM32F429_PG13_FUNC_SPI6_SCK 0x6d06\n-#define STM32F429_PG13_FUNC_USART6_CTS 0x6d09\n-#define STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c\n-#define STM32F429_PG13_FUNC_FMC_A24 0x6d0d\n-#define STM32F429_PG13_FUNC_EVENTOUT 0x6d10\n-#define STM32F429_PG13_FUNC_ANALOG 0x6d11\n-\n-#define STM32F429_PG14_FUNC_GPIO 0x6e00\n-#define STM32F429_PG14_FUNC_SPI6_MOSI 0x6e06\n-#define STM32F429_PG14_FUNC_USART6_TX 0x6e09\n-#define STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c\n-#define STM32F429_PG14_FUNC_FMC_A25 0x6e0d\n-#define STM32F429_PG14_FUNC_EVENTOUT 0x6e10\n-#define STM32F429_PG14_FUNC_ANALOG 0x6e11\n-\n-#define STM32F429_PG15_FUNC_GPIO 0x6f00\n-#define STM32F429_PG15_FUNC_USART6_CTS 0x6f09\n-#define STM32F429_PG15_FUNC_FMC_SDNCAS 0x6f0d\n-#define STM32F429_PG15_FUNC_DCMI_D13 0x6f0e\n-#define STM32F429_PG15_FUNC_EVENTOUT 0x6f10\n-#define STM32F429_PG15_FUNC_ANALOG 0x6f11\n-\n-\n-\n-#define STM32F429_PH0_FUNC_GPIO 0x7000\n-#define STM32F429_PH0_FUNC_EVENTOUT 0x7010\n-#define STM32F429_PH0_FUNC_ANALOG 0x7011\n-\n-#define STM32F429_PH1_FUNC_GPIO 0x7100\n-#define STM32F429_PH1_FUNC_EVENTOUT 0x7110\n-#define STM32F429_PH1_FUNC_ANALOG 0x7111\n-\n-#define STM32F429_PH2_FUNC_GPIO 0x7200\n-#define STM32F429_PH2_FUNC_ETH_MII_CRS 0x720c\n-#define STM32F429_PH2_FUNC_FMC_SDCKE0 0x720d\n-#define STM32F429_PH2_FUNC_LCD_R0 0x720f\n-#define STM32F429_PH2_FUNC_EVENTOUT 0x7210\n-#define STM32F429_PH2_FUNC_ANALOG 0x7211\n-\n-#define STM32F429_PH3_FUNC_GPIO 0x7300\n-#define STM32F429_PH3_FUNC_ETH_MII_COL 0x730c\n-#define STM32F429_PH3_FUNC_FMC_SDNE0 0x730d\n-#define STM32F429_PH3_FUNC_LCD_R1 0x730f\n-#define STM32F429_PH3_FUNC_EVENTOUT 0x7310\n-#define STM32F429_PH3_FUNC_ANALOG 0x7311\n-\n-#define STM32F429_PH4_FUNC_GPIO 0x7400\n-#define STM32F429_PH4_FUNC_I2C2_SCL 0x7405\n-#define STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b\n-#define STM32F429_PH4_FUNC_EVENTOUT 0x7410\n-#define STM32F429_PH4_FUNC_ANALOG 0x7411\n-\n-#define STM32F429_PH5_FUNC_GPIO 0x7500\n-#define STM32F429_PH5_FUNC_I2C2_SDA 0x7505\n-#define STM32F429_PH5_FUNC_SPI5_NSS 0x7506\n-#define STM32F429_PH5_FUNC_FMC_SDNWE 0x750d\n-#define STM32F429_PH5_FUNC_EVENTOUT 0x7510\n-#define STM32F429_PH5_FUNC_ANALOG 0x7511\n-\n-#define STM32F429_PH6_FUNC_GPIO 0x7600\n-#define STM32F429_PH6_FUNC_I2C2_SMBA 0x7605\n-#define STM32F429_PH6_FUNC_SPI5_SCK 0x7606\n-#define STM32F429_PH6_FUNC_TIM12_CH1 0x760a\n-#define STM32F429_PH6_FUNC_ETH_MII_RXD2 0x760c\n-#define STM32F429_PH6_FUNC_FMC_SDNE1 0x760d\n-#define STM32F429_PH6_FUNC_DCMI_D8 0x760e\n-#define STM32F429_PH6_FUNC_EVENTOUT 0x7610\n-#define STM32F429_PH6_FUNC_ANALOG 0x7611\n-\n-#define STM32F429_PH7_FUNC_GPIO 0x7700\n-#define STM32F429_PH7_FUNC_I2C3_SCL 0x7705\n-#define STM32F429_PH7_FUNC_SPI5_MISO 0x7706\n-#define STM32F429_PH7_FUNC_ETH_MII_RXD3 0x770c\n-#define STM32F429_PH7_FUNC_FMC_SDCKE1 0x770d\n-#define STM32F429_PH7_FUNC_DCMI_D9 0x770e\n-#define STM32F429_PH7_FUNC_EVENTOUT 0x7710\n-#define STM32F429_PH7_FUNC_ANALOG 0x7711\n-\n-#define STM32F429_PH8_FUNC_GPIO 0x7800\n-#define STM32F429_PH8_FUNC_I2C3_SDA 0x7805\n-#define STM32F429_PH8_FUNC_FMC_D16 0x780d\n-#define STM32F429_PH8_FUNC_DCMI_HSYNC 0x780e\n-#define STM32F429_PH8_FUNC_LCD_R2 0x780f\n-#define STM32F429_PH8_FUNC_EVENTOUT 0x7810\n-#define STM32F429_PH8_FUNC_ANALOG 0x7811\n-\n-#define STM32F429_PH9_FUNC_GPIO 0x7900\n-#define STM32F429_PH9_FUNC_I2C3_SMBA 0x7905\n-#define STM32F429_PH9_FUNC_TIM12_CH2 0x790a\n-#define STM32F429_PH9_FUNC_FMC_D17 0x790d\n-#define STM32F429_PH9_FUNC_DCMI_D0 0x790e\n-#define STM32F429_PH9_FUNC_LCD_R3 0x790f\n-#define STM32F429_PH9_FUNC_EVENTOUT 0x7910\n-#define STM32F429_PH9_FUNC_ANALOG 0x7911\n-\n-#define STM32F429_PH10_FUNC_GPIO 0x7a00\n-#define STM32F429_PH10_FUNC_TIM5_CH1 0x7a03\n-#define STM32F429_PH10_FUNC_FMC_D18 0x7a0d\n-#define STM32F429_PH10_FUNC_DCMI_D1 0x7a0e\n-#define STM32F429_PH10_FUNC_LCD_R4 0x7a0f\n-#define STM32F429_PH10_FUNC_EVENTOUT 0x7a10\n-#define STM32F429_PH10_FUNC_ANALOG 0x7a11\n-\n-#define STM32F429_PH11_FUNC_GPIO 0x7b00\n-#define STM32F429_PH11_FUNC_TIM5_CH2 0x7b03\n-#define STM32F429_PH11_FUNC_FMC_D19 0x7b0d\n-#define STM32F429_PH11_FUNC_DCMI_D2 0x7b0e\n-#define STM32F429_PH11_FUNC_LCD_R5 0x7b0f\n-#define STM32F429_PH11_FUNC_EVENTOUT 0x7b10\n-#define STM32F429_PH11_FUNC_ANALOG 0x7b11\n-\n-#define STM32F429_PH12_FUNC_GPIO 0x7c00\n-#define STM32F429_PH12_FUNC_TIM5_CH3 0x7c03\n-#define STM32F429_PH12_FUNC_FMC_D20 0x7c0d\n-#define STM32F429_PH12_FUNC_DCMI_D3 0x7c0e\n-#define STM32F429_PH12_FUNC_LCD_R6 0x7c0f\n-#define STM32F429_PH12_FUNC_EVENTOUT 0x7c10\n-#define STM32F429_PH12_FUNC_ANALOG 0x7c11\n-\n-#define STM32F429_PH13_FUNC_GPIO 0x7d00\n-#define STM32F429_PH13_FUNC_TIM8_CH1N 0x7d04\n-#define STM32F429_PH13_FUNC_CAN1_TX 0x7d0a\n-#define STM32F429_PH13_FUNC_FMC_D21 0x7d0d\n-#define STM32F429_PH13_FUNC_LCD_G2 0x7d0f\n-#define STM32F429_PH13_FUNC_EVENTOUT 0x7d10\n-#define STM32F429_PH13_FUNC_ANALOG 0x7d11\n-\n-#define STM32F429_PH14_FUNC_GPIO 0x7e00\n-#define STM32F429_PH14_FUNC_TIM8_CH2N 0x7e04\n-#define STM32F429_PH14_FUNC_FMC_D22 0x7e0d\n-#define STM32F429_PH14_FUNC_DCMI_D4 0x7e0e\n-#define STM32F429_PH14_FUNC_LCD_G3 0x7e0f\n-#define STM32F429_PH14_FUNC_EVENTOUT 0x7e10\n-#define STM32F429_PH14_FUNC_ANALOG 0x7e11\n-\n-#define STM32F429_PH15_FUNC_GPIO 0x7f00\n-#define STM32F429_PH15_FUNC_TIM8_CH3N 0x7f04\n-#define STM32F429_PH15_FUNC_FMC_D23 0x7f0d\n-#define STM32F429_PH15_FUNC_DCMI_D11 0x7f0e\n-#define STM32F429_PH15_FUNC_LCD_G4 0x7f0f\n-#define STM32F429_PH15_FUNC_EVENTOUT 0x7f10\n-#define STM32F429_PH15_FUNC_ANALOG 0x7f11\n-\n-\n-\n-#define STM32F429_PI0_FUNC_GPIO 0x8000\n-#define STM32F429_PI0_FUNC_TIM5_CH4 0x8003\n-#define STM32F429_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006\n-#define STM32F429_PI0_FUNC_FMC_D24 0x800d\n-#define STM32F429_PI0_FUNC_DCMI_D13 0x800e\n-#define STM32F429_PI0_FUNC_LCD_G5 0x800f\n-#define STM32F429_PI0_FUNC_EVENTOUT 0x8010\n-#define STM32F429_PI0_FUNC_ANALOG 0x8011\n-\n-#define STM32F429_PI1_FUNC_GPIO 0x8100\n-#define STM32F429_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106\n-#define STM32F429_PI1_FUNC_FMC_D25 0x810d\n-#define STM32F429_PI1_FUNC_DCMI_D8 0x810e\n-#define STM32F429_PI1_FUNC_LCD_G6 0x810f\n-#define STM32F429_PI1_FUNC_EVENTOUT 0x8110\n-#define STM32F429_PI1_FUNC_ANALOG 0x8111\n-\n-#define STM32F429_PI2_FUNC_GPIO 0x8200\n-#define STM32F429_PI2_FUNC_TIM8_CH4 0x8204\n-#define STM32F429_PI2_FUNC_SPI2_MISO 0x8206\n-#define STM32F429_PI2_FUNC_I2S2EXT_SD 0x8207\n-#define STM32F429_PI2_FUNC_FMC_D26 0x820d\n-#define STM32F429_PI2_FUNC_DCMI_D9 0x820e\n-#define STM32F429_PI2_FUNC_LCD_G7 0x820f\n-#define STM32F429_PI2_FUNC_EVENTOUT 0x8210\n-#define STM32F429_PI2_FUNC_ANALOG 0x8211\n-\n-#define STM32F429_PI3_FUNC_GPIO 0x8300\n-#define STM32F429_PI3_FUNC_TIM8_ETR 0x8304\n-#define STM32F429_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306\n-#define STM32F429_PI3_FUNC_FMC_D27 0x830d\n-#define STM32F429_PI3_FUNC_DCMI_D10 0x830e\n-#define STM32F429_PI3_FUNC_EVENTOUT 0x8310\n-#define STM32F429_PI3_FUNC_ANALOG 0x8311\n-\n-#define STM32F429_PI4_FUNC_GPIO 0x8400\n-#define STM32F429_PI4_FUNC_TIM8_BKIN 0x8404\n-#define STM32F429_PI4_FUNC_FMC_NBL2 0x840d\n-#define STM32F429_PI4_FUNC_DCMI_D5 0x840e\n-#define STM32F429_PI4_FUNC_LCD_B4 0x840f\n-#define STM32F429_PI4_FUNC_EVENTOUT 0x8410\n-#define STM32F429_PI4_FUNC_ANALOG 0x8411\n-\n-#define STM32F429_PI5_FUNC_GPIO 0x8500\n-#define STM32F429_PI5_FUNC_TIM8_CH1 0x8504\n-#define STM32F429_PI5_FUNC_FMC_NBL3 0x850d\n-#define STM32F429_PI5_FUNC_DCMI_VSYNC 0x850e\n-#define STM32F429_PI5_FUNC_LCD_B5 0x850f\n-#define STM32F429_PI5_FUNC_EVENTOUT 0x8510\n-#define STM32F429_PI5_FUNC_ANALOG 0x8511\n-\n-#define STM32F429_PI6_FUNC_GPIO 0x8600\n-#define STM32F429_PI6_FUNC_TIM8_CH2 0x8604\n-#define STM32F429_PI6_FUNC_FMC_D28 0x860d\n-#define STM32F429_PI6_FUNC_DCMI_D6 0x860e\n-#define STM32F429_PI6_FUNC_LCD_B6 0x860f\n-#define STM32F429_PI6_FUNC_EVENTOUT 0x8610\n-#define STM32F429_PI6_FUNC_ANALOG 0x8611\n-\n-#define STM32F429_PI7_FUNC_GPIO 0x8700\n-#define STM32F429_PI7_FUNC_TIM8_CH3 0x8704\n-#define STM32F429_PI7_FUNC_FMC_D29 0x870d\n-#define STM32F429_PI7_FUNC_DCMI_D7 0x870e\n-#define STM32F429_PI7_FUNC_LCD_B7 0x870f\n-#define STM32F429_PI7_FUNC_EVENTOUT 0x8710\n-#define STM32F429_PI7_FUNC_ANALOG 0x8711\n-\n-#define STM32F429_PI8_FUNC_GPIO 0x8800\n-#define STM32F429_PI8_FUNC_EVENTOUT 0x8810\n-#define STM32F429_PI8_FUNC_ANALOG 0x8811\n-\n-#define STM32F429_PI9_FUNC_GPIO 0x8900\n-#define STM32F429_PI9_FUNC_CAN1_RX 0x890a\n-#define STM32F429_PI9_FUNC_FMC_D30 0x890d\n-#define STM32F429_PI9_FUNC_LCD_VSYNC 0x890f\n-#define STM32F429_PI9_FUNC_EVENTOUT 0x8910\n-#define STM32F429_PI9_FUNC_ANALOG 0x8911\n-\n-#define STM32F429_PI10_FUNC_GPIO 0x8a00\n-#define STM32F429_PI10_FUNC_ETH_MII_RX_ER 0x8a0c\n-#define STM32F429_PI10_FUNC_FMC_D31 0x8a0d\n-#define STM32F429_PI10_FUNC_LCD_HSYNC 0x8a0f\n-#define STM32F429_PI10_FUNC_EVENTOUT 0x8a10\n-#define STM32F429_PI10_FUNC_ANALOG 0x8a11\n-\n-#define STM32F429_PI11_FUNC_GPIO 0x8b00\n-#define STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b\n-#define STM32F429_PI11_FUNC_EVENTOUT 0x8b10\n-#define STM32F429_PI11_FUNC_ANALOG 0x8b11\n-\n-#define STM32F429_PI12_FUNC_GPIO 0x8c00\n-#define STM32F429_PI12_FUNC_LCD_HSYNC 0x8c0f\n-#define STM32F429_PI12_FUNC_EVENTOUT 0x8c10\n-#define STM32F429_PI12_FUNC_ANALOG 0x8c11\n-\n-#define STM32F429_PI13_FUNC_GPIO 0x8d00\n-#define STM32F429_PI13_FUNC_LCD_VSYNC 0x8d0f\n-#define STM32F429_PI13_FUNC_EVENTOUT 0x8d10\n-#define STM32F429_PI13_FUNC_ANALOG 0x8d11\n-\n-#define STM32F429_PI14_FUNC_GPIO 0x8e00\n-#define STM32F429_PI14_FUNC_LCD_CLK 0x8e0f\n-#define STM32F429_PI14_FUNC_EVENTOUT 0x8e10\n-#define STM32F429_PI14_FUNC_ANALOG 0x8e11\n-\n-#define STM32F429_PI15_FUNC_GPIO 0x8f00\n-#define STM32F429_PI15_FUNC_LCD_R0 0x8f0f\n-#define STM32F429_PI15_FUNC_EVENTOUT 0x8f10\n-#define STM32F429_PI15_FUNC_ANALOG 0x8f11\n-\n-\n-\n-#define STM32F429_PJ0_FUNC_GPIO 0x9000\n-#define STM32F429_PJ0_FUNC_LCD_R1 0x900f\n-#define STM32F429_PJ0_FUNC_EVENTOUT 0x9010\n-#define STM32F429_PJ0_FUNC_ANALOG 0x9011\n-\n-#define STM32F429_PJ1_FUNC_GPIO 0x9100\n-#define STM32F429_PJ1_FUNC_LCD_R2 0x910f\n-#define STM32F429_PJ1_FUNC_EVENTOUT 0x9110\n-#define STM32F429_PJ1_FUNC_ANALOG 0x9111\n-\n-#define STM32F429_PJ2_FUNC_GPIO 0x9200\n-#define STM32F429_PJ2_FUNC_LCD_R3 0x920f\n-#define STM32F429_PJ2_FUNC_EVENTOUT 0x9210\n-#define STM32F429_PJ2_FUNC_ANALOG 0x9211\n-\n-#define STM32F429_PJ3_FUNC_GPIO 0x9300\n-#define STM32F429_PJ3_FUNC_LCD_R4 0x930f\n-#define STM32F429_PJ3_FUNC_EVENTOUT 0x9310\n-#define STM32F429_PJ3_FUNC_ANALOG 0x9311\n-\n-#define STM32F429_PJ4_FUNC_GPIO 0x9400\n-#define STM32F429_PJ4_FUNC_LCD_R5 0x940f\n-#define STM32F429_PJ4_FUNC_EVENTOUT 0x9410\n-#define STM32F429_PJ4_FUNC_ANALOG 0x9411\n-\n-#define STM32F429_PJ5_FUNC_GPIO 0x9500\n-#define STM32F429_PJ5_FUNC_LCD_R6 0x950f\n-#define STM32F429_PJ5_FUNC_EVENTOUT 0x9510\n-#define STM32F429_PJ5_FUNC_ANALOG 0x9511\n-\n-#define STM32F429_PJ6_FUNC_GPIO 0x9600\n-#define STM32F429_PJ6_FUNC_LCD_R7 0x960f\n-#define STM32F429_PJ6_FUNC_EVENTOUT 0x9610\n-#define STM32F429_PJ6_FUNC_ANALOG 0x9611\n-\n-#define STM32F429_PJ7_FUNC_GPIO 0x9700\n-#define STM32F429_PJ7_FUNC_LCD_G0 0x970f\n-#define STM32F429_PJ7_FUNC_EVENTOUT 0x9710\n-#define STM32F429_PJ7_FUNC_ANALOG 0x9711\n-\n-#define STM32F429_PJ8_FUNC_GPIO 0x9800\n-#define STM32F429_PJ8_FUNC_LCD_G1 0x980f\n-#define STM32F429_PJ8_FUNC_EVENTOUT 0x9810\n-#define STM32F429_PJ8_FUNC_ANALOG 0x9811\n-\n-#define STM32F429_PJ9_FUNC_GPIO 0x9900\n-#define STM32F429_PJ9_FUNC_LCD_G2 0x990f\n-#define STM32F429_PJ9_FUNC_EVENTOUT 0x9910\n-#define STM32F429_PJ9_FUNC_ANALOG 0x9911\n-\n-#define STM32F429_PJ10_FUNC_GPIO 0x9a00\n-#define STM32F429_PJ10_FUNC_LCD_G3 0x9a0f\n-#define STM32F429_PJ10_FUNC_EVENTOUT 0x9a10\n-#define STM32F429_PJ10_FUNC_ANALOG 0x9a11\n-\n-#define STM32F429_PJ11_FUNC_GPIO 0x9b00\n-#define STM32F429_PJ11_FUNC_LCD_G4 0x9b0f\n-#define STM32F429_PJ11_FUNC_EVENTOUT 0x9b10\n-#define STM32F429_PJ11_FUNC_ANALOG 0x9b11\n-\n-#define STM32F429_PJ12_FUNC_GPIO 0x9c00\n-#define STM32F429_PJ12_FUNC_LCD_B0 0x9c0f\n-#define STM32F429_PJ12_FUNC_EVENTOUT 0x9c10\n-#define STM32F429_PJ12_FUNC_ANALOG 0x9c11\n-\n-#define STM32F429_PJ13_FUNC_GPIO 0x9d00\n-#define STM32F429_PJ13_FUNC_LCD_B1 0x9d0f\n-#define STM32F429_PJ13_FUNC_EVENTOUT 0x9d10\n-#define STM32F429_PJ13_FUNC_ANALOG 0x9d11\n-\n-#define STM32F429_PJ14_FUNC_GPIO 0x9e00\n-#define STM32F429_PJ14_FUNC_LCD_B2 0x9e0f\n-#define STM32F429_PJ14_FUNC_EVENTOUT 0x9e10\n-#define STM32F429_PJ14_FUNC_ANALOG 0x9e11\n-\n-#define STM32F429_PJ15_FUNC_GPIO 0x9f00\n-#define STM32F429_PJ15_FUNC_LCD_B3 0x9f0f\n-#define STM32F429_PJ15_FUNC_EVENTOUT 0x9f10\n-#define STM32F429_PJ15_FUNC_ANALOG 0x9f11\n-\n-\n-\n-#define STM32F429_PK0_FUNC_GPIO 0xa000\n-#define STM32F429_PK0_FUNC_LCD_G5 0xa00f\n-#define STM32F429_PK0_FUNC_EVENTOUT 0xa010\n-#define STM32F429_PK0_FUNC_ANALOG 0xa011\n-\n-#define STM32F429_PK1_FUNC_GPIO 0xa100\n-#define STM32F429_PK1_FUNC_LCD_G6 0xa10f\n-#define STM32F429_PK1_FUNC_EVENTOUT 0xa110\n-#define STM32F429_PK1_FUNC_ANALOG 0xa111\n-\n-#define STM32F429_PK2_FUNC_GPIO 0xa200\n-#define STM32F429_PK2_FUNC_LCD_G7 0xa20f\n-#define STM32F429_PK2_FUNC_EVENTOUT 0xa210\n-#define STM32F429_PK2_FUNC_ANALOG 0xa211\n-\n-#define STM32F429_PK3_FUNC_GPIO 0xa300\n-#define STM32F429_PK3_FUNC_LCD_B4 0xa30f\n-#define STM32F429_PK3_FUNC_EVENTOUT 0xa310\n-#define STM32F429_PK3_FUNC_ANALOG 0xa311\n-\n-#define STM32F429_PK4_FUNC_GPIO 0xa400\n-#define STM32F429_PK4_FUNC_LCD_B5 0xa40f\n-#define STM32F429_PK4_FUNC_EVENTOUT 0xa410\n-#define STM32F429_PK4_FUNC_ANALOG 0xa411\n-\n-#define STM32F429_PK5_FUNC_GPIO 0xa500\n-#define STM32F429_PK5_FUNC_LCD_B6 0xa50f\n-#define STM32F429_PK5_FUNC_EVENTOUT 0xa510\n-#define STM32F429_PK5_FUNC_ANALOG 0xa511\n-\n-#define STM32F429_PK6_FUNC_GPIO 0xa600\n-#define STM32F429_PK6_FUNC_LCD_B7 0xa60f\n-#define STM32F429_PK6_FUNC_EVENTOUT 0xa610\n-#define STM32F429_PK6_FUNC_ANALOG 0xa611\n-\n-#define STM32F429_PK7_FUNC_GPIO 0xa700\n-#define STM32F429_PK7_FUNC_LCD_DE 0xa70f\n-#define STM32F429_PK7_FUNC_EVENTOUT 0xa710\n-#define STM32F429_PK7_FUNC_ANALOG 0xa711\n-\n-#endif /* _DT_BINDINGS_STM32F429_PINFUNC_H */\ndiff --git a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h b/include/dt-bindings/pinctrl/stm32f746-pinfunc.h\ndeleted file mode 100644\nindex 6348c6a..0000000\n--- a/include/dt-bindings/pinctrl/stm32f746-pinfunc.h\n+++ /dev/null\n@@ -1,1324 +0,0 @@\n-#ifndef _DT_BINDINGS_STM32F746_PINFUNC_H\n-#define _DT_BINDINGS_STM32F746_PINFUNC_H\n-\n-#define STM32F746_PA0_FUNC_GPIO 0x0\n-#define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2\n-#define STM32F746_PA0_FUNC_TIM5_CH1 0x3\n-#define STM32F746_PA0_FUNC_TIM8_ETR 0x4\n-#define STM32F746_PA0_FUNC_USART2_CTS 0x8\n-#define STM32F746_PA0_FUNC_UART4_TX 0x9\n-#define STM32F746_PA0_FUNC_SAI2_SD_B 0xb\n-#define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc\n-#define STM32F746_PA0_FUNC_EVENTOUT 0x10\n-#define STM32F746_PA0_FUNC_ANALOG 0x11\n-\n-#define STM32F746_PA1_FUNC_GPIO 0x100\n-#define STM32F746_PA1_FUNC_TIM2_CH2 0x102\n-#define STM32F746_PA1_FUNC_TIM5_CH2 0x103\n-#define STM32F746_PA1_FUNC_USART2_RTS 0x108\n-#define STM32F746_PA1_FUNC_UART4_RX 0x109\n-#define STM32F746_PA1_FUNC_QUADSPI_BK1_IO3 0x10a\n-#define STM32F746_PA1_FUNC_SAI2_MCLK_B 0x10b\n-#define STM32F746_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c\n-#define STM32F746_PA1_FUNC_LCD_R2 0x10f\n-#define STM32F746_PA1_FUNC_EVENTOUT 0x110\n-#define STM32F746_PA1_FUNC_ANALOG 0x111\n-\n-#define STM32F746_PA2_FUNC_GPIO 0x200\n-#define STM32F746_PA2_FUNC_TIM2_CH3 0x202\n-#define STM32F746_PA2_FUNC_TIM5_CH3 0x203\n-#define STM32F746_PA2_FUNC_TIM9_CH1 0x204\n-#define STM32F746_PA2_FUNC_USART2_TX 0x208\n-#define STM32F746_PA2_FUNC_SAI2_SCK_B 0x209\n-#define STM32F746_PA2_FUNC_ETH_MDIO 0x20c\n-#define STM32F746_PA2_FUNC_LCD_R1 0x20f\n-#define STM32F746_PA2_FUNC_EVENTOUT 0x210\n-#define STM32F746_PA2_FUNC_ANALOG 0x211\n-\n-#define STM32F746_PA3_FUNC_GPIO 0x300\n-#define STM32F746_PA3_FUNC_TIM2_CH4 0x302\n-#define STM32F746_PA3_FUNC_TIM5_CH4 0x303\n-#define STM32F746_PA3_FUNC_TIM9_CH2 0x304\n-#define STM32F746_PA3_FUNC_USART2_RX 0x308\n-#define STM32F746_PA3_FUNC_OTG_HS_ULPI_D0 0x30b\n-#define STM32F746_PA3_FUNC_ETH_MII_COL 0x30c\n-#define STM32F746_PA3_FUNC_LCD_B5 0x30f\n-#define STM32F746_PA3_FUNC_EVENTOUT 0x310\n-#define STM32F746_PA3_FUNC_ANALOG 0x311\n-\n-#define STM32F746_PA4_FUNC_GPIO 0x400\n-#define STM32F746_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406\n-#define STM32F746_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407\n-#define STM32F746_PA4_FUNC_USART2_CK 0x408\n-#define STM32F746_PA4_FUNC_OTG_HS_SOF 0x40d\n-#define STM32F746_PA4_FUNC_DCMI_HSYNC 0x40e\n-#define STM32F746_PA4_FUNC_LCD_VSYNC 0x40f\n-#define STM32F746_PA4_FUNC_EVENTOUT 0x410\n-#define STM32F746_PA4_FUNC_ANALOG 0x411\n-\n-#define STM32F746_PA5_FUNC_GPIO 0x500\n-#define STM32F746_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502\n-#define STM32F746_PA5_FUNC_TIM8_CH1N 0x504\n-#define STM32F746_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506\n-#define STM32F746_PA5_FUNC_OTG_HS_ULPI_CK 0x50b\n-#define STM32F746_PA5_FUNC_LCD_R4 0x50f\n-#define STM32F746_PA5_FUNC_EVENTOUT 0x510\n-#define STM32F746_PA5_FUNC_ANALOG 0x511\n-\n-#define STM32F746_PA6_FUNC_GPIO 0x600\n-#define STM32F746_PA6_FUNC_TIM1_BKIN 0x602\n-#define STM32F746_PA6_FUNC_TIM3_CH1 0x603\n-#define STM32F746_PA6_FUNC_TIM8_BKIN 0x604\n-#define STM32F746_PA6_FUNC_SPI1_MISO 0x606\n-#define STM32F746_PA6_FUNC_TIM13_CH1 0x60a\n-#define STM32F746_PA6_FUNC_DCMI_PIXCLK 0x60e\n-#define STM32F746_PA6_FUNC_LCD_G2 0x60f\n-#define STM32F746_PA6_FUNC_EVENTOUT 0x610\n-#define STM32F746_PA6_FUNC_ANALOG 0x611\n-\n-#define STM32F746_PA7_FUNC_GPIO 0x700\n-#define STM32F746_PA7_FUNC_TIM1_CH1N 0x702\n-#define STM32F746_PA7_FUNC_TIM3_CH2 0x703\n-#define STM32F746_PA7_FUNC_TIM8_CH1N 0x704\n-#define STM32F746_PA7_FUNC_SPI1_MOSI_I2S1_SD 0x706\n-#define STM32F746_PA7_FUNC_TIM14_CH1 0x70a\n-#define STM32F746_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c\n-#define STM32F746_PA7_FUNC_FMC_SDNWE 0x70d\n-#define STM32F746_PA7_FUNC_EVENTOUT 0x710\n-#define STM32F746_PA7_FUNC_ANALOG 0x711\n-\n-#define STM32F746_PA8_FUNC_GPIO 0x800\n-#define STM32F746_PA8_FUNC_MCO1 0x801\n-#define STM32F746_PA8_FUNC_TIM1_CH1 0x802\n-#define STM32F746_PA8_FUNC_TIM8_BKIN2 0x804\n-#define STM32F746_PA8_FUNC_I2C3_SCL 0x805\n-#define STM32F746_PA8_FUNC_USART1_CK 0x808\n-#define STM32F746_PA8_FUNC_OTG_FS_SOF 0x80b\n-#define STM32F746_PA8_FUNC_LCD_R6 0x80f\n-#define STM32F746_PA8_FUNC_EVENTOUT 0x810\n-#define STM32F746_PA8_FUNC_ANALOG 0x811\n-\n-#define STM32F746_PA9_FUNC_GPIO 0x900\n-#define STM32F746_PA9_FUNC_TIM1_CH2 0x902\n-#define STM32F746_PA9_FUNC_I2C3_SMBA 0x905\n-#define STM32F746_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906\n-#define STM32F746_PA9_FUNC_USART1_TX 0x908\n-#define STM32F746_PA9_FUNC_DCMI_D0 0x90e\n-#define STM32F746_PA9_FUNC_EVENTOUT 0x910\n-#define STM32F746_PA9_FUNC_ANALOG 0x911\n-\n-#define STM32F746_PA10_FUNC_GPIO 0xa00\n-#define STM32F746_PA10_FUNC_TIM1_CH3 0xa02\n-#define STM32F746_PA10_FUNC_USART1_RX 0xa08\n-#define STM32F746_PA10_FUNC_OTG_FS_ID 0xa0b\n-#define STM32F746_PA10_FUNC_DCMI_D1 0xa0e\n-#define STM32F746_PA10_FUNC_EVENTOUT 0xa10\n-#define STM32F746_PA10_FUNC_ANALOG 0xa11\n-\n-#define STM32F746_PA11_FUNC_GPIO 0xb00\n-#define STM32F746_PA11_FUNC_TIM1_CH4 0xb02\n-#define STM32F746_PA11_FUNC_USART1_CTS 0xb08\n-#define STM32F746_PA11_FUNC_CAN1_RX 0xb0a\n-#define STM32F746_PA11_FUNC_OTG_FS_DM 0xb0b\n-#define STM32F746_PA11_FUNC_LCD_R4 0xb0f\n-#define STM32F746_PA11_FUNC_EVENTOUT 0xb10\n-#define STM32F746_PA11_FUNC_ANALOG 0xb11\n-\n-#define STM32F746_PA12_FUNC_GPIO 0xc00\n-#define STM32F746_PA12_FUNC_TIM1_ETR 0xc02\n-#define STM32F746_PA12_FUNC_USART1_RTS 0xc08\n-#define STM32F746_PA12_FUNC_SAI2_FS_B 0xc09\n-#define STM32F746_PA12_FUNC_CAN1_TX 0xc0a\n-#define STM32F746_PA12_FUNC_OTG_FS_DP 0xc0b\n-#define STM32F746_PA12_FUNC_LCD_R5 0xc0f\n-#define STM32F746_PA12_FUNC_EVENTOUT 0xc10\n-#define STM32F746_PA12_FUNC_ANALOG 0xc11\n-\n-#define STM32F746_PA13_FUNC_GPIO 0xd00\n-#define STM32F746_PA13_FUNC_JTMS_SWDIO 0xd01\n-#define STM32F746_PA13_FUNC_EVENTOUT 0xd10\n-#define STM32F746_PA13_FUNC_ANALOG 0xd11\n-\n-#define STM32F746_PA14_FUNC_GPIO 0xe00\n-#define STM32F746_PA14_FUNC_JTCK_SWCLK 0xe01\n-#define STM32F746_PA14_FUNC_EVENTOUT 0xe10\n-#define STM32F746_PA14_FUNC_ANALOG 0xe11\n-\n-#define STM32F746_PA15_FUNC_GPIO 0xf00\n-#define STM32F746_PA15_FUNC_JTDI 0xf01\n-#define STM32F746_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02\n-#define STM32F746_PA15_FUNC_HDMI_CEC 0xf05\n-#define STM32F746_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06\n-#define STM32F746_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07\n-#define STM32F746_PA15_FUNC_UART4_RTS 0xf09\n-#define STM32F746_PA15_FUNC_EVENTOUT 0xf10\n-#define STM32F746_PA15_FUNC_ANALOG 0xf11\n-\n-\n-#define STM32F746_PB0_FUNC_GPIO 0x1000\n-#define STM32F746_PB0_FUNC_TIM1_CH2N 0x1002\n-#define STM32F746_PB0_FUNC_TIM3_CH3 0x1003\n-#define STM32F746_PB0_FUNC_TIM8_CH2N 0x1004\n-#define STM32F746_PB0_FUNC_UART4_CTS 0x1009\n-#define STM32F746_PB0_FUNC_LCD_R3 0x100a\n-#define STM32F746_PB0_FUNC_OTG_HS_ULPI_D1 0x100b\n-#define STM32F746_PB0_FUNC_ETH_MII_RXD2 0x100c\n-#define STM32F746_PB0_FUNC_EVENTOUT 0x1010\n-#define STM32F746_PB0_FUNC_ANALOG 0x1011\n-\n-#define STM32F746_PB1_FUNC_GPIO 0x1100\n-#define STM32F746_PB1_FUNC_TIM1_CH3N 0x1102\n-#define STM32F746_PB1_FUNC_TIM3_CH4 0x1103\n-#define STM32F746_PB1_FUNC_TIM8_CH3N 0x1104\n-#define STM32F746_PB1_FUNC_LCD_R6 0x110a\n-#define STM32F746_PB1_FUNC_OTG_HS_ULPI_D2 0x110b\n-#define STM32F746_PB1_FUNC_ETH_MII_RXD3 0x110c\n-#define STM32F746_PB1_FUNC_EVENTOUT 0x1110\n-#define STM32F746_PB1_FUNC_ANALOG 0x1111\n-\n-#define STM32F746_PB2_FUNC_GPIO 0x1200\n-#define STM32F746_PB2_FUNC_SAI1_SD_A 0x1207\n-#define STM32F746_PB2_FUNC_SPI3_MOSI_I2S3_SD 0x1208\n-#define STM32F746_PB2_FUNC_QUADSPI_CLK 0x120a\n-#define STM32F746_PB2_FUNC_EVENTOUT 0x1210\n-#define STM32F746_PB2_FUNC_ANALOG 0x1211\n-\n-#define STM32F746_PB3_FUNC_GPIO 0x1300\n-#define STM32F746_PB3_FUNC_JTDO_TRACESWO 0x1301\n-#define STM32F746_PB3_FUNC_TIM2_CH2 0x1302\n-#define STM32F746_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306\n-#define STM32F746_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307\n-#define STM32F746_PB3_FUNC_EVENTOUT 0x1310\n-#define STM32F746_PB3_FUNC_ANALOG 0x1311\n-\n-#define STM32F746_PB4_FUNC_GPIO 0x1400\n-#define STM32F746_PB4_FUNC_NJTRST 0x1401\n-#define STM32F746_PB4_FUNC_TIM3_CH1 0x1403\n-#define STM32F746_PB4_FUNC_SPI1_MISO 0x1406\n-#define STM32F746_PB4_FUNC_SPI3_MISO 0x1407\n-#define STM32F746_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408\n-#define STM32F746_PB4_FUNC_EVENTOUT 0x1410\n-#define STM32F746_PB4_FUNC_ANALOG 0x1411\n-\n-#define STM32F746_PB5_FUNC_GPIO 0x1500\n-#define STM32F746_PB5_FUNC_TIM3_CH2 0x1503\n-#define STM32F746_PB5_FUNC_I2C1_SMBA 0x1505\n-#define STM32F746_PB5_FUNC_SPI1_MOSI_I2S1_SD 0x1506\n-#define STM32F746_PB5_FUNC_SPI3_MOSI_I2S3_SD 0x1507\n-#define STM32F746_PB5_FUNC_CAN2_RX 0x150a\n-#define STM32F746_PB5_FUNC_OTG_HS_ULPI_D7 0x150b\n-#define STM32F746_PB5_FUNC_ETH_PPS_OUT 0x150c\n-#define STM32F746_PB5_FUNC_FMC_SDCKE1 0x150d\n-#define STM32F746_PB5_FUNC_DCMI_D10 0x150e\n-#define STM32F746_PB5_FUNC_EVENTOUT 0x1510\n-#define STM32F746_PB5_FUNC_ANALOG 0x1511\n-\n-#define STM32F746_PB6_FUNC_GPIO 0x1600\n-#define STM32F746_PB6_FUNC_TIM4_CH1 0x1603\n-#define STM32F746_PB6_FUNC_HDMI_CEC 0x1604\n-#define STM32F746_PB6_FUNC_I2C1_SCL 0x1605\n-#define STM32F746_PB6_FUNC_USART1_TX 0x1608\n-#define STM32F746_PB6_FUNC_CAN2_TX 0x160a\n-#define STM32F746_PB6_FUNC_QUADSPI_BK1_NCS 0x160b\n-#define STM32F746_PB6_FUNC_FMC_SDNE1 0x160d\n-#define STM32F746_PB6_FUNC_DCMI_D5 0x160e\n-#define STM32F746_PB6_FUNC_EVENTOUT 0x1610\n-#define STM32F746_PB6_FUNC_ANALOG 0x1611\n-\n-#define STM32F746_PB7_FUNC_GPIO 0x1700\n-#define STM32F746_PB7_FUNC_TIM4_CH2 0x1703\n-#define STM32F746_PB7_FUNC_I2C1_SDA 0x1705\n-#define STM32F746_PB7_FUNC_USART1_RX 0x1708\n-#define STM32F746_PB7_FUNC_FMC_NL 0x170d\n-#define STM32F746_PB7_FUNC_DCMI_VSYNC 0x170e\n-#define STM32F746_PB7_FUNC_EVENTOUT 0x1710\n-#define STM32F746_PB7_FUNC_ANALOG 0x1711\n-\n-#define STM32F746_PB8_FUNC_GPIO 0x1800\n-#define STM32F746_PB8_FUNC_TIM4_CH3 0x1803\n-#define STM32F746_PB8_FUNC_TIM10_CH1 0x1804\n-#define STM32F746_PB8_FUNC_I2C1_SCL 0x1805\n-#define STM32F746_PB8_FUNC_CAN1_RX 0x180a\n-#define STM32F746_PB8_FUNC_ETH_MII_TXD3 0x180c\n-#define STM32F746_PB8_FUNC_SDMMC1_D4 0x180d\n-#define STM32F746_PB8_FUNC_DCMI_D6 0x180e\n-#define STM32F746_PB8_FUNC_LCD_B6 0x180f\n-#define STM32F746_PB8_FUNC_EVENTOUT 0x1810\n-#define STM32F746_PB8_FUNC_ANALOG 0x1811\n-\n-#define STM32F746_PB9_FUNC_GPIO 0x1900\n-#define STM32F746_PB9_FUNC_TIM4_CH4 0x1903\n-#define STM32F746_PB9_FUNC_TIM11_CH1 0x1904\n-#define STM32F746_PB9_FUNC_I2C1_SDA 0x1905\n-#define STM32F746_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906\n-#define STM32F746_PB9_FUNC_CAN1_TX 0x190a\n-#define STM32F746_PB9_FUNC_SDMMC1_D5 0x190d\n-#define STM32F746_PB9_FUNC_DCMI_D7 0x190e\n-#define STM32F746_PB9_FUNC_LCD_B7 0x190f\n-#define STM32F746_PB9_FUNC_EVENTOUT 0x1910\n-#define STM32F746_PB9_FUNC_ANALOG 0x1911\n-\n-#define STM32F746_PB10_FUNC_GPIO 0x1a00\n-#define STM32F746_PB10_FUNC_TIM2_CH3 0x1a02\n-#define STM32F746_PB10_FUNC_I2C2_SCL 0x1a05\n-#define STM32F746_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06\n-#define STM32F746_PB10_FUNC_USART3_TX 0x1a08\n-#define STM32F746_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b\n-#define STM32F746_PB10_FUNC_ETH_MII_RX_ER 0x1a0c\n-#define STM32F746_PB10_FUNC_LCD_G4 0x1a0f\n-#define STM32F746_PB10_FUNC_EVENTOUT 0x1a10\n-#define STM32F746_PB10_FUNC_ANALOG 0x1a11\n-\n-#define STM32F746_PB11_FUNC_GPIO 0x1b00\n-#define STM32F746_PB11_FUNC_TIM2_CH4 0x1b02\n-#define STM32F746_PB11_FUNC_I2C2_SDA 0x1b05\n-#define STM32F746_PB11_FUNC_USART3_RX 0x1b08\n-#define STM32F746_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b\n-#define STM32F746_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c\n-#define STM32F746_PB11_FUNC_LCD_G5 0x1b0f\n-#define STM32F746_PB11_FUNC_EVENTOUT 0x1b10\n-#define STM32F746_PB11_FUNC_ANALOG 0x1b11\n-\n-#define STM32F746_PB12_FUNC_GPIO 0x1c00\n-#define STM32F746_PB12_FUNC_TIM1_BKIN 0x1c02\n-#define STM32F746_PB12_FUNC_I2C2_SMBA 0x1c05\n-#define STM32F746_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06\n-#define STM32F746_PB12_FUNC_USART3_CK 0x1c08\n-#define STM32F746_PB12_FUNC_CAN2_RX 0x1c0a\n-#define STM32F746_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b\n-#define STM32F746_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c\n-#define STM32F746_PB12_FUNC_OTG_HS_ID 0x1c0d\n-#define STM32F746_PB12_FUNC_EVENTOUT 0x1c10\n-#define STM32F746_PB12_FUNC_ANALOG 0x1c11\n-\n-#define STM32F746_PB13_FUNC_GPIO 0x1d00\n-#define STM32F746_PB13_FUNC_TIM1_CH1N 0x1d02\n-#define STM32F746_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06\n-#define STM32F746_PB13_FUNC_USART3_CTS 0x1d08\n-#define STM32F746_PB13_FUNC_CAN2_TX 0x1d0a\n-#define STM32F746_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b\n-#define STM32F746_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c\n-#define STM32F746_PB13_FUNC_EVENTOUT 0x1d10\n-#define STM32F746_PB13_FUNC_ANALOG 0x1d11\n-\n-#define STM32F746_PB14_FUNC_GPIO 0x1e00\n-#define STM32F746_PB14_FUNC_TIM1_CH2N 0x1e02\n-#define STM32F746_PB14_FUNC_TIM8_CH2N 0x1e04\n-#define STM32F746_PB14_FUNC_SPI2_MISO 0x1e06\n-#define STM32F746_PB14_FUNC_USART3_RTS 0x1e08\n-#define STM32F746_PB14_FUNC_TIM12_CH1 0x1e0a\n-#define STM32F746_PB14_FUNC_OTG_HS_DM 0x1e0d\n-#define STM32F746_PB14_FUNC_EVENTOUT 0x1e10\n-#define STM32F746_PB14_FUNC_ANALOG 0x1e11\n-\n-#define STM32F746_PB15_FUNC_GPIO 0x1f00\n-#define STM32F746_PB15_FUNC_RTC_REFIN 0x1f01\n-#define STM32F746_PB15_FUNC_TIM1_CH3N 0x1f02\n-#define STM32F746_PB15_FUNC_TIM8_CH3N 0x1f04\n-#define STM32F746_PB15_FUNC_SPI2_MOSI_I2S2_SD 0x1f06\n-#define STM32F746_PB15_FUNC_TIM12_CH2 0x1f0a\n-#define STM32F746_PB15_FUNC_OTG_HS_DP 0x1f0d\n-#define STM32F746_PB15_FUNC_EVENTOUT 0x1f10\n-#define STM32F746_PB15_FUNC_ANALOG 0x1f11\n-\n-\n-#define STM32F746_PC0_FUNC_GPIO 0x2000\n-#define STM32F746_PC0_FUNC_SAI2_FS_B 0x2009\n-#define STM32F746_PC0_FUNC_OTG_HS_ULPI_STP 0x200b\n-#define STM32F746_PC0_FUNC_FMC_SDNWE 0x200d\n-#define STM32F746_PC0_FUNC_LCD_R5 0x200f\n-#define STM32F746_PC0_FUNC_EVENTOUT 0x2010\n-#define STM32F746_PC0_FUNC_ANALOG 0x2011\n-\n-#define STM32F746_PC1_FUNC_GPIO 0x2100\n-#define STM32F746_PC1_FUNC_TRACED0 0x2101\n-#define STM32F746_PC1_FUNC_SPI2_MOSI_I2S2_SD 0x2106\n-#define STM32F746_PC1_FUNC_SAI1_SD_A 0x2107\n-#define STM32F746_PC1_FUNC_ETH_MDC 0x210c\n-#define STM32F746_PC1_FUNC_EVENTOUT 0x2110\n-#define STM32F746_PC1_FUNC_ANALOG 0x2111\n-\n-#define STM32F746_PC2_FUNC_GPIO 0x2200\n-#define STM32F746_PC2_FUNC_SPI2_MISO 0x2206\n-#define STM32F746_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b\n-#define STM32F746_PC2_FUNC_ETH_MII_TXD2 0x220c\n-#define STM32F746_PC2_FUNC_FMC_SDNE0 0x220d\n-#define STM32F746_PC2_FUNC_EVENTOUT 0x2210\n-#define STM32F746_PC2_FUNC_ANALOG 0x2211\n-\n-#define STM32F746_PC3_FUNC_GPIO 0x2300\n-#define STM32F746_PC3_FUNC_SPI2_MOSI_I2S2_SD 0x2306\n-#define STM32F746_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b\n-#define STM32F746_PC3_FUNC_ETH_MII_TX_CLK 0x230c\n-#define STM32F746_PC3_FUNC_FMC_SDCKE0 0x230d\n-#define STM32F746_PC3_FUNC_EVENTOUT 0x2310\n-#define STM32F746_PC3_FUNC_ANALOG 0x2311\n-\n-#define STM32F746_PC4_FUNC_GPIO 0x2400\n-#define STM32F746_PC4_FUNC_I2S1_MCK 0x2406\n-#define STM32F746_PC4_FUNC_SPDIFRX_IN2 0x2409\n-#define STM32F746_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c\n-#define STM32F746_PC4_FUNC_FMC_SDNE0 0x240d\n-#define STM32F746_PC4_FUNC_EVENTOUT 0x2410\n-#define STM32F746_PC4_FUNC_ANALOG 0x2411\n-\n-#define STM32F746_PC5_FUNC_GPIO 0x2500\n-#define STM32F746_PC5_FUNC_SPDIFRX_IN3 0x2509\n-#define STM32F746_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c\n-#define STM32F746_PC5_FUNC_FMC_SDCKE0 0x250d\n-#define STM32F746_PC5_FUNC_EVENTOUT 0x2510\n-#define STM32F746_PC5_FUNC_ANALOG 0x2511\n-\n-#define STM32F746_PC6_FUNC_GPIO 0x2600\n-#define STM32F746_PC6_FUNC_TIM3_CH1 0x2603\n-#define STM32F746_PC6_FUNC_TIM8_CH1 0x2604\n-#define STM32F746_PC6_FUNC_I2S2_MCK 0x2606\n-#define STM32F746_PC6_FUNC_USART6_TX 0x2609\n-#define STM32F746_PC6_FUNC_SDMMC1_D6 0x260d\n-#define STM32F746_PC6_FUNC_DCMI_D0 0x260e\n-#define STM32F746_PC6_FUNC_LCD_HSYNC 0x260f\n-#define STM32F746_PC6_FUNC_EVENTOUT 0x2610\n-#define STM32F746_PC6_FUNC_ANALOG 0x2611\n-\n-#define STM32F746_PC7_FUNC_GPIO 0x2700\n-#define STM32F746_PC7_FUNC_TIM3_CH2 0x2703\n-#define STM32F746_PC7_FUNC_TIM8_CH2 0x2704\n-#define STM32F746_PC7_FUNC_I2S3_MCK 0x2707\n-#define STM32F746_PC7_FUNC_USART6_RX 0x2709\n-#define STM32F746_PC7_FUNC_SDMMC1_D7 0x270d\n-#define STM32F746_PC7_FUNC_DCMI_D1 0x270e\n-#define STM32F746_PC7_FUNC_LCD_G6 0x270f\n-#define STM32F746_PC7_FUNC_EVENTOUT 0x2710\n-#define STM32F746_PC7_FUNC_ANALOG 0x2711\n-\n-#define STM32F746_PC8_FUNC_GPIO 0x2800\n-#define STM32F746_PC8_FUNC_TRACED1 0x2801\n-#define STM32F746_PC8_FUNC_TIM3_CH3 0x2803\n-#define STM32F746_PC8_FUNC_TIM8_CH3 0x2804\n-#define STM32F746_PC8_FUNC_UART5_RTS 0x2808\n-#define STM32F746_PC8_FUNC_USART6_CK 0x2809\n-#define STM32F746_PC8_FUNC_SDMMC1_D0 0x280d\n-#define STM32F746_PC8_FUNC_DCMI_D2 0x280e\n-#define STM32F746_PC8_FUNC_EVENTOUT 0x2810\n-#define STM32F746_PC8_FUNC_ANALOG 0x2811\n-\n-#define STM32F746_PC9_FUNC_GPIO 0x2900\n-#define STM32F746_PC9_FUNC_MCO2 0x2901\n-#define STM32F746_PC9_FUNC_TIM3_CH4 0x2903\n-#define STM32F746_PC9_FUNC_TIM8_CH4 0x2904\n-#define STM32F746_PC9_FUNC_I2C3_SDA 0x2905\n-#define STM32F746_PC9_FUNC_I2S_CKIN 0x2906\n-#define STM32F746_PC9_FUNC_UART5_CTS 0x2908\n-#define STM32F746_PC9_FUNC_QUADSPI_BK1_IO0 0x290a\n-#define STM32F746_PC9_FUNC_SDMMC1_D1 0x290d\n-#define STM32F746_PC9_FUNC_DCMI_D3 0x290e\n-#define STM32F746_PC9_FUNC_EVENTOUT 0x2910\n-#define STM32F746_PC9_FUNC_ANALOG 0x2911\n-\n-#define STM32F746_PC10_FUNC_GPIO 0x2a00\n-#define STM32F746_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07\n-#define STM32F746_PC10_FUNC_USART3_TX 0x2a08\n-#define STM32F746_PC10_FUNC_UART4_TX 0x2a09\n-#define STM32F746_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a\n-#define STM32F746_PC10_FUNC_SDMMC1_D2 0x2a0d\n-#define STM32F746_PC10_FUNC_DCMI_D8 0x2a0e\n-#define STM32F746_PC10_FUNC_LCD_R2 0x2a0f\n-#define STM32F746_PC10_FUNC_EVENTOUT 0x2a10\n-#define STM32F746_PC10_FUNC_ANALOG 0x2a11\n-\n-#define STM32F746_PC11_FUNC_GPIO 0x2b00\n-#define STM32F746_PC11_FUNC_SPI3_MISO 0x2b07\n-#define STM32F746_PC11_FUNC_USART3_RX 0x2b08\n-#define STM32F746_PC11_FUNC_UART4_RX 0x2b09\n-#define STM32F746_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a\n-#define STM32F746_PC11_FUNC_SDMMC1_D3 0x2b0d\n-#define STM32F746_PC11_FUNC_DCMI_D4 0x2b0e\n-#define STM32F746_PC11_FUNC_EVENTOUT 0x2b10\n-#define STM32F746_PC11_FUNC_ANALOG 0x2b11\n-\n-#define STM32F746_PC12_FUNC_GPIO 0x2c00\n-#define STM32F746_PC12_FUNC_TRACED3 0x2c01\n-#define STM32F746_PC12_FUNC_SPI3_MOSI_I2S3_SD 0x2c07\n-#define STM32F746_PC12_FUNC_USART3_CK 0x2c08\n-#define STM32F746_PC12_FUNC_UART5_TX 0x2c09\n-#define STM32F746_PC12_FUNC_SDMMC1_CK 0x2c0d\n-#define STM32F746_PC12_FUNC_DCMI_D9 0x2c0e\n-#define STM32F746_PC12_FUNC_EVENTOUT 0x2c10\n-#define STM32F746_PC12_FUNC_ANALOG 0x2c11\n-\n-#define STM32F746_PC13_FUNC_GPIO 0x2d00\n-#define STM32F746_PC13_FUNC_EVENTOUT 0x2d10\n-#define STM32F746_PC13_FUNC_ANALOG 0x2d11\n-\n-#define STM32F746_PC14_FUNC_GPIO 0x2e00\n-#define STM32F746_PC14_FUNC_EVENTOUT 0x2e10\n-#define STM32F746_PC14_FUNC_ANALOG 0x2e11\n-\n-#define STM32F746_PC15_FUNC_GPIO 0x2f00\n-#define STM32F746_PC15_FUNC_EVENTOUT 0x2f10\n-#define STM32F746_PC15_FUNC_ANALOG 0x2f11\n-\n-\n-#define STM32F746_PD0_FUNC_GPIO 0x3000\n-#define STM32F746_PD0_FUNC_CAN1_RX 0x300a\n-#define STM32F746_PD0_FUNC_FMC_D2 0x300d\n-#define STM32F746_PD0_FUNC_EVENTOUT 0x3010\n-#define STM32F746_PD0_FUNC_ANALOG 0x3011\n-\n-#define STM32F746_PD1_FUNC_GPIO 0x3100\n-#define STM32F746_PD1_FUNC_CAN1_TX 0x310a\n-#define STM32F746_PD1_FUNC_FMC_D3 0x310d\n-#define STM32F746_PD1_FUNC_EVENTOUT 0x3110\n-#define STM32F746_PD1_FUNC_ANALOG 0x3111\n-\n-#define STM32F746_PD2_FUNC_GPIO 0x3200\n-#define STM32F746_PD2_FUNC_TRACED2 0x3201\n-#define STM32F746_PD2_FUNC_TIM3_ETR 0x3203\n-#define STM32F746_PD2_FUNC_UART5_RX 0x3209\n-#define STM32F746_PD2_FUNC_SDMMC1_CMD 0x320d\n-#define STM32F746_PD2_FUNC_DCMI_D11 0x320e\n-#define STM32F746_PD2_FUNC_EVENTOUT 0x3210\n-#define STM32F746_PD2_FUNC_ANALOG 0x3211\n-\n-#define STM32F746_PD3_FUNC_GPIO 0x3300\n-#define STM32F746_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306\n-#define STM32F746_PD3_FUNC_USART2_CTS 0x3308\n-#define STM32F746_PD3_FUNC_FMC_CLK 0x330d\n-#define STM32F746_PD3_FUNC_DCMI_D5 0x330e\n-#define STM32F746_PD3_FUNC_LCD_G7 0x330f\n-#define STM32F746_PD3_FUNC_EVENTOUT 0x3310\n-#define STM32F746_PD3_FUNC_ANALOG 0x3311\n-\n-#define STM32F746_PD4_FUNC_GPIO 0x3400\n-#define STM32F746_PD4_FUNC_USART2_RTS 0x3408\n-#define STM32F746_PD4_FUNC_FMC_NOE 0x340d\n-#define STM32F746_PD4_FUNC_EVENTOUT 0x3410\n-#define STM32F746_PD4_FUNC_ANALOG 0x3411\n-\n-#define STM32F746_PD5_FUNC_GPIO 0x3500\n-#define STM32F746_PD5_FUNC_USART2_TX 0x3508\n-#define STM32F746_PD5_FUNC_FMC_NWE 0x350d\n-#define STM32F746_PD5_FUNC_EVENTOUT 0x3510\n-#define STM32F746_PD5_FUNC_ANALOG 0x3511\n-\n-#define STM32F746_PD6_FUNC_GPIO 0x3600\n-#define STM32F746_PD6_FUNC_SPI3_MOSI_I2S3_SD 0x3606\n-#define STM32F746_PD6_FUNC_SAI1_SD_A 0x3607\n-#define STM32F746_PD6_FUNC_USART2_RX 0x3608\n-#define STM32F746_PD6_FUNC_FMC_NWAIT 0x360d\n-#define STM32F746_PD6_FUNC_DCMI_D10 0x360e\n-#define STM32F746_PD6_FUNC_LCD_B2 0x360f\n-#define STM32F746_PD6_FUNC_EVENTOUT 0x3610\n-#define STM32F746_PD6_FUNC_ANALOG 0x3611\n-\n-#define STM32F746_PD7_FUNC_GPIO 0x3700\n-#define STM32F746_PD7_FUNC_USART2_CK 0x3708\n-#define STM32F746_PD7_FUNC_SPDIFRX_IN0 0x3709\n-#define STM32F746_PD7_FUNC_FMC_NE1 0x370d\n-#define STM32F746_PD7_FUNC_EVENTOUT 0x3710\n-#define STM32F746_PD7_FUNC_ANALOG 0x3711\n-\n-#define STM32F746_PD8_FUNC_GPIO 0x3800\n-#define STM32F746_PD8_FUNC_USART3_TX 0x3808\n-#define STM32F746_PD8_FUNC_SPDIFRX_IN1 0x3809\n-#define STM32F746_PD8_FUNC_FMC_D13 0x380d\n-#define STM32F746_PD8_FUNC_EVENTOUT 0x3810\n-#define STM32F746_PD8_FUNC_ANALOG 0x3811\n-\n-#define STM32F746_PD9_FUNC_GPIO 0x3900\n-#define STM32F746_PD9_FUNC_USART3_RX 0x3908\n-#define STM32F746_PD9_FUNC_FMC_D14 0x390d\n-#define STM32F746_PD9_FUNC_EVENTOUT 0x3910\n-#define STM32F746_PD9_FUNC_ANALOG 0x3911\n-\n-#define STM32F746_PD10_FUNC_GPIO 0x3a00\n-#define STM32F746_PD10_FUNC_USART3_CK 0x3a08\n-#define STM32F746_PD10_FUNC_FMC_D15 0x3a0d\n-#define STM32F746_PD10_FUNC_LCD_B3 0x3a0f\n-#define STM32F746_PD10_FUNC_EVENTOUT 0x3a10\n-#define STM32F746_PD10_FUNC_ANALOG 0x3a11\n-\n-#define STM32F746_PD11_FUNC_GPIO 0x3b00\n-#define STM32F746_PD11_FUNC_I2C4_SMBA 0x3b05\n-#define STM32F746_PD11_FUNC_USART3_CTS 0x3b08\n-#define STM32F746_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a\n-#define STM32F746_PD11_FUNC_SAI2_SD_A 0x3b0b\n-#define STM32F746_PD11_FUNC_FMC_A16_FMC_CLE 0x3b0d\n-#define STM32F746_PD11_FUNC_EVENTOUT 0x3b10\n-#define STM32F746_PD11_FUNC_ANALOG 0x3b11\n-\n-#define STM32F746_PD12_FUNC_GPIO 0x3c00\n-#define STM32F746_PD12_FUNC_TIM4_CH1 0x3c03\n-#define STM32F746_PD12_FUNC_LPTIM1_IN1 0x3c04\n-#define STM32F746_PD12_FUNC_I2C4_SCL 0x3c05\n-#define STM32F746_PD12_FUNC_USART3_RTS 0x3c08\n-#define STM32F746_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a\n-#define STM32F746_PD12_FUNC_SAI2_FS_A 0x3c0b\n-#define STM32F746_PD12_FUNC_FMC_A17_FMC_ALE 0x3c0d\n-#define STM32F746_PD12_FUNC_EVENTOUT 0x3c10\n-#define STM32F746_PD12_FUNC_ANALOG 0x3c11\n-\n-#define STM32F746_PD13_FUNC_GPIO 0x3d00\n-#define STM32F746_PD13_FUNC_TIM4_CH2 0x3d03\n-#define STM32F746_PD13_FUNC_LPTIM1_OUT 0x3d04\n-#define STM32F746_PD13_FUNC_I2C4_SDA 0x3d05\n-#define STM32F746_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a\n-#define STM32F746_PD13_FUNC_SAI2_SCK_A 0x3d0b\n-#define STM32F746_PD13_FUNC_FMC_A18 0x3d0d\n-#define STM32F746_PD13_FUNC_EVENTOUT 0x3d10\n-#define STM32F746_PD13_FUNC_ANALOG 0x3d11\n-\n-#define STM32F746_PD14_FUNC_GPIO 0x3e00\n-#define STM32F746_PD14_FUNC_TIM4_CH3 0x3e03\n-#define STM32F746_PD14_FUNC_UART8_CTS 0x3e09\n-#define STM32F746_PD14_FUNC_FMC_D0 0x3e0d\n-#define STM32F746_PD14_FUNC_EVENTOUT 0x3e10\n-#define STM32F746_PD14_FUNC_ANALOG 0x3e11\n-\n-#define STM32F746_PD15_FUNC_GPIO 0x3f00\n-#define STM32F746_PD15_FUNC_TIM4_CH4 0x3f03\n-#define STM32F746_PD15_FUNC_UART8_RTS 0x3f09\n-#define STM32F746_PD15_FUNC_FMC_D1 0x3f0d\n-#define STM32F746_PD15_FUNC_EVENTOUT 0x3f10\n-#define STM32F746_PD15_FUNC_ANALOG 0x3f11\n-\n-\n-#define STM32F746_PE0_FUNC_GPIO 0x4000\n-#define STM32F746_PE0_FUNC_TIM4_ETR 0x4003\n-#define STM32F746_PE0_FUNC_LPTIM1_ETR 0x4004\n-#define STM32F746_PE0_FUNC_UART8_RX 0x4009\n-#define STM32F746_PE0_FUNC_SAI2_MCLK_A 0x400b\n-#define STM32F746_PE0_FUNC_FMC_NBL0 0x400d\n-#define STM32F746_PE0_FUNC_DCMI_D2 0x400e\n-#define STM32F746_PE0_FUNC_EVENTOUT 0x4010\n-#define STM32F746_PE0_FUNC_ANALOG 0x4011\n-\n-#define STM32F746_PE1_FUNC_GPIO 0x4100\n-#define STM32F746_PE1_FUNC_LPTIM1_IN2 0x4104\n-#define STM32F746_PE1_FUNC_UART8_TX 0x4109\n-#define STM32F746_PE1_FUNC_FMC_NBL1 0x410d\n-#define STM32F746_PE1_FUNC_DCMI_D3 0x410e\n-#define STM32F746_PE1_FUNC_EVENTOUT 0x4110\n-#define STM32F746_PE1_FUNC_ANALOG 0x4111\n-\n-#define STM32F746_PE2_FUNC_GPIO 0x4200\n-#define STM32F746_PE2_FUNC_TRACECLK 0x4201\n-#define STM32F746_PE2_FUNC_SPI4_SCK 0x4206\n-#define STM32F746_PE2_FUNC_SAI1_MCLK_A 0x4207\n-#define STM32F746_PE2_FUNC_QUADSPI_BK1_IO2 0x420a\n-#define STM32F746_PE2_FUNC_ETH_MII_TXD3 0x420c\n-#define STM32F746_PE2_FUNC_FMC_A23 0x420d\n-#define STM32F746_PE2_FUNC_EVENTOUT 0x4210\n-#define STM32F746_PE2_FUNC_ANALOG 0x4211\n-\n-#define STM32F746_PE3_FUNC_GPIO 0x4300\n-#define STM32F746_PE3_FUNC_TRACED0 0x4301\n-#define STM32F746_PE3_FUNC_SAI1_SD_B 0x4307\n-#define STM32F746_PE3_FUNC_FMC_A19 0x430d\n-#define STM32F746_PE3_FUNC_EVENTOUT 0x4310\n-#define STM32F746_PE3_FUNC_ANALOG 0x4311\n-\n-#define STM32F746_PE4_FUNC_GPIO 0x4400\n-#define STM32F746_PE4_FUNC_TRACED1 0x4401\n-#define STM32F746_PE4_FUNC_SPI4_NSS 0x4406\n-#define STM32F746_PE4_FUNC_SAI1_FS_A 0x4407\n-#define STM32F746_PE4_FUNC_FMC_A20 0x440d\n-#define STM32F746_PE4_FUNC_DCMI_D4 0x440e\n-#define STM32F746_PE4_FUNC_LCD_B0 0x440f\n-#define STM32F746_PE4_FUNC_EVENTOUT 0x4410\n-#define STM32F746_PE4_FUNC_ANALOG 0x4411\n-\n-#define STM32F746_PE5_FUNC_GPIO 0x4500\n-#define STM32F746_PE5_FUNC_TRACED2 0x4501\n-#define STM32F746_PE5_FUNC_TIM9_CH1 0x4504\n-#define STM32F746_PE5_FUNC_SPI4_MISO 0x4506\n-#define STM32F746_PE5_FUNC_SAI1_SCK_A 0x4507\n-#define STM32F746_PE5_FUNC_FMC_A21 0x450d\n-#define STM32F746_PE5_FUNC_DCMI_D6 0x450e\n-#define STM32F746_PE5_FUNC_LCD_G0 0x450f\n-#define STM32F746_PE5_FUNC_EVENTOUT 0x4510\n-#define STM32F746_PE5_FUNC_ANALOG 0x4511\n-\n-#define STM32F746_PE6_FUNC_GPIO 0x4600\n-#define STM32F746_PE6_FUNC_TRACED3 0x4601\n-#define STM32F746_PE6_FUNC_TIM1_BKIN2 0x4602\n-#define STM32F746_PE6_FUNC_TIM9_CH2 0x4604\n-#define STM32F746_PE6_FUNC_SPI4_MOSI 0x4606\n-#define STM32F746_PE6_FUNC_SAI1_SD_A 0x4607\n-#define STM32F746_PE6_FUNC_SAI2_MCLK_B 0x460b\n-#define STM32F746_PE6_FUNC_FMC_A22 0x460d\n-#define STM32F746_PE6_FUNC_DCMI_D7 0x460e\n-#define STM32F746_PE6_FUNC_LCD_G1 0x460f\n-#define STM32F746_PE6_FUNC_EVENTOUT 0x4610\n-#define STM32F746_PE6_FUNC_ANALOG 0x4611\n-\n-#define STM32F746_PE7_FUNC_GPIO 0x4700\n-#define STM32F746_PE7_FUNC_TIM1_ETR 0x4702\n-#define STM32F746_PE7_FUNC_UART7_RX 0x4709\n-#define STM32F746_PE7_FUNC_QUADSPI_BK2_IO0 0x470b\n-#define STM32F746_PE7_FUNC_FMC_D4 0x470d\n-#define STM32F746_PE7_FUNC_EVENTOUT 0x4710\n-#define STM32F746_PE7_FUNC_ANALOG 0x4711\n-\n-#define STM32F746_PE8_FUNC_GPIO 0x4800\n-#define STM32F746_PE8_FUNC_TIM1_CH1N 0x4802\n-#define STM32F746_PE8_FUNC_UART7_TX 0x4809\n-#define STM32F746_PE8_FUNC_QUADSPI_BK2_IO1 0x480b\n-#define STM32F746_PE8_FUNC_FMC_D5 0x480d\n-#define STM32F746_PE8_FUNC_EVENTOUT 0x4810\n-#define STM32F746_PE8_FUNC_ANALOG 0x4811\n-\n-#define STM32F746_PE9_FUNC_GPIO 0x4900\n-#define STM32F746_PE9_FUNC_TIM1_CH1 0x4902\n-#define STM32F746_PE9_FUNC_UART7_RTS 0x4909\n-#define STM32F746_PE9_FUNC_QUADSPI_BK2_IO2 0x490b\n-#define STM32F746_PE9_FUNC_FMC_D6 0x490d\n-#define STM32F746_PE9_FUNC_EVENTOUT 0x4910\n-#define STM32F746_PE9_FUNC_ANALOG 0x4911\n-\n-#define STM32F746_PE10_FUNC_GPIO 0x4a00\n-#define STM32F746_PE10_FUNC_TIM1_CH2N 0x4a02\n-#define STM32F746_PE10_FUNC_UART7_CTS 0x4a09\n-#define STM32F746_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b\n-#define STM32F746_PE10_FUNC_FMC_D7 0x4a0d\n-#define STM32F746_PE10_FUNC_EVENTOUT 0x4a10\n-#define STM32F746_PE10_FUNC_ANALOG 0x4a11\n-\n-#define STM32F746_PE11_FUNC_GPIO 0x4b00\n-#define STM32F746_PE11_FUNC_TIM1_CH2 0x4b02\n-#define STM32F746_PE11_FUNC_SPI4_NSS 0x4b06\n-#define STM32F746_PE11_FUNC_SAI2_SD_B 0x4b0b\n-#define STM32F746_PE11_FUNC_FMC_D8 0x4b0d\n-#define STM32F746_PE11_FUNC_LCD_G3 0x4b0f\n-#define STM32F746_PE11_FUNC_EVENTOUT 0x4b10\n-#define STM32F746_PE11_FUNC_ANALOG 0x4b11\n-\n-#define STM32F746_PE12_FUNC_GPIO 0x4c00\n-#define STM32F746_PE12_FUNC_TIM1_CH3N 0x4c02\n-#define STM32F746_PE12_FUNC_SPI4_SCK 0x4c06\n-#define STM32F746_PE12_FUNC_SAI2_SCK_B 0x4c0b\n-#define STM32F746_PE12_FUNC_FMC_D9 0x4c0d\n-#define STM32F746_PE12_FUNC_LCD_B4 0x4c0f\n-#define STM32F746_PE12_FUNC_EVENTOUT 0x4c10\n-#define STM32F746_PE12_FUNC_ANALOG 0x4c11\n-\n-#define STM32F746_PE13_FUNC_GPIO 0x4d00\n-#define STM32F746_PE13_FUNC_TIM1_CH3 0x4d02\n-#define STM32F746_PE13_FUNC_SPI4_MISO 0x4d06\n-#define STM32F746_PE13_FUNC_SAI2_FS_B 0x4d0b\n-#define STM32F746_PE13_FUNC_FMC_D10 0x4d0d\n-#define STM32F746_PE13_FUNC_LCD_DE 0x4d0f\n-#define STM32F746_PE13_FUNC_EVENTOUT 0x4d10\n-#define STM32F746_PE13_FUNC_ANALOG 0x4d11\n-\n-#define STM32F746_PE14_FUNC_GPIO 0x4e00\n-#define STM32F746_PE14_FUNC_TIM1_CH4 0x4e02\n-#define STM32F746_PE14_FUNC_SPI4_MOSI 0x4e06\n-#define STM32F746_PE14_FUNC_SAI2_MCLK_B 0x4e0b\n-#define STM32F746_PE14_FUNC_FMC_D11 0x4e0d\n-#define STM32F746_PE14_FUNC_LCD_CLK 0x4e0f\n-#define STM32F746_PE14_FUNC_EVENTOUT 0x4e10\n-#define STM32F746_PE14_FUNC_ANALOG 0x4e11\n-\n-#define STM32F746_PE15_FUNC_GPIO 0x4f00\n-#define STM32F746_PE15_FUNC_TIM1_BKIN 0x4f02\n-#define STM32F746_PE15_FUNC_FMC_D12 0x4f0d\n-#define STM32F746_PE15_FUNC_LCD_R7 0x4f0f\n-#define STM32F746_PE15_FUNC_EVENTOUT 0x4f10\n-#define STM32F746_PE15_FUNC_ANALOG 0x4f11\n-\n-\n-#define STM32F746_PF0_FUNC_GPIO 0x5000\n-#define STM32F746_PF0_FUNC_I2C2_SDA 0x5005\n-#define STM32F746_PF0_FUNC_FMC_A0 0x500d\n-#define STM32F746_PF0_FUNC_EVENTOUT 0x5010\n-#define STM32F746_PF0_FUNC_ANALOG 0x5011\n-\n-#define STM32F746_PF1_FUNC_GPIO 0x5100\n-#define STM32F746_PF1_FUNC_I2C2_SCL 0x5105\n-#define STM32F746_PF1_FUNC_FMC_A1 0x510d\n-#define STM32F746_PF1_FUNC_EVENTOUT 0x5110\n-#define STM32F746_PF1_FUNC_ANALOG 0x5111\n-\n-#define STM32F746_PF2_FUNC_GPIO 0x5200\n-#define STM32F746_PF2_FUNC_I2C2_SMBA 0x5205\n-#define STM32F746_PF2_FUNC_FMC_A2 0x520d\n-#define STM32F746_PF2_FUNC_EVENTOUT 0x5210\n-#define STM32F746_PF2_FUNC_ANALOG 0x5211\n-\n-#define STM32F746_PF3_FUNC_GPIO 0x5300\n-#define STM32F746_PF3_FUNC_FMC_A3 0x530d\n-#define STM32F746_PF3_FUNC_EVENTOUT 0x5310\n-#define STM32F746_PF3_FUNC_ANALOG 0x5311\n-\n-#define STM32F746_PF4_FUNC_GPIO 0x5400\n-#define STM32F746_PF4_FUNC_FMC_A4 0x540d\n-#define STM32F746_PF4_FUNC_EVENTOUT 0x5410\n-#define STM32F746_PF4_FUNC_ANALOG 0x5411\n-\n-#define STM32F746_PF5_FUNC_GPIO 0x5500\n-#define STM32F746_PF5_FUNC_FMC_A5 0x550d\n-#define STM32F746_PF5_FUNC_EVENTOUT 0x5510\n-#define STM32F746_PF5_FUNC_ANALOG 0x5511\n-\n-#define STM32F746_PF6_FUNC_GPIO 0x5600\n-#define STM32F746_PF6_FUNC_TIM10_CH1 0x5604\n-#define STM32F746_PF6_FUNC_SPI5_NSS 0x5606\n-#define STM32F746_PF6_FUNC_SAI1_SD_B 0x5607\n-#define STM32F746_PF6_FUNC_UART7_RX 0x5609\n-#define STM32F746_PF6_FUNC_QUADSPI_BK1_IO3 0x560a\n-#define STM32F746_PF6_FUNC_EVENTOUT 0x5610\n-#define STM32F746_PF6_FUNC_ANALOG 0x5611\n-\n-#define STM32F746_PF7_FUNC_GPIO 0x5700\n-#define STM32F746_PF7_FUNC_TIM11_CH1 0x5704\n-#define STM32F746_PF7_FUNC_SPI5_SCK 0x5706\n-#define STM32F746_PF7_FUNC_SAI1_MCLK_B 0x5707\n-#define STM32F746_PF7_FUNC_UART7_TX 0x5709\n-#define STM32F746_PF7_FUNC_QUADSPI_BK1_IO2 0x570a\n-#define STM32F746_PF7_FUNC_EVENTOUT 0x5710\n-#define STM32F746_PF7_FUNC_ANALOG 0x5711\n-\n-#define STM32F746_PF8_FUNC_GPIO 0x5800\n-#define STM32F746_PF8_FUNC_SPI5_MISO 0x5806\n-#define STM32F746_PF8_FUNC_SAI1_SCK_B 0x5807\n-#define STM32F746_PF8_FUNC_UART7_RTS 0x5809\n-#define STM32F746_PF8_FUNC_TIM13_CH1 0x580a\n-#define STM32F746_PF8_FUNC_QUADSPI_BK1_IO0 0x580b\n-#define STM32F746_PF8_FUNC_EVENTOUT 0x5810\n-#define STM32F746_PF8_FUNC_ANALOG 0x5811\n-\n-#define STM32F746_PF9_FUNC_GPIO 0x5900\n-#define STM32F746_PF9_FUNC_SPI5_MOSI 0x5906\n-#define STM32F746_PF9_FUNC_SAI1_FS_B 0x5907\n-#define STM32F746_PF9_FUNC_UART7_CTS 0x5909\n-#define STM32F746_PF9_FUNC_TIM14_CH1 0x590a\n-#define STM32F746_PF9_FUNC_QUADSPI_BK1_IO1 0x590b\n-#define STM32F746_PF9_FUNC_EVENTOUT 0x5910\n-#define STM32F746_PF9_FUNC_ANALOG 0x5911\n-\n-#define STM32F746_PF10_FUNC_GPIO 0x5a00\n-#define STM32F746_PF10_FUNC_DCMI_D11 0x5a0e\n-#define STM32F746_PF10_FUNC_LCD_DE 0x5a0f\n-#define STM32F746_PF10_FUNC_EVENTOUT 0x5a10\n-#define STM32F746_PF10_FUNC_ANALOG 0x5a11\n-\n-#define STM32F746_PF11_FUNC_GPIO 0x5b00\n-#define STM32F746_PF11_FUNC_SPI5_MOSI 0x5b06\n-#define STM32F746_PF11_FUNC_SAI2_SD_B 0x5b0b\n-#define STM32F746_PF11_FUNC_FMC_SDNRAS 0x5b0d\n-#define STM32F746_PF11_FUNC_DCMI_D12 0x5b0e\n-#define STM32F746_PF11_FUNC_EVENTOUT 0x5b10\n-#define STM32F746_PF11_FUNC_ANALOG 0x5b11\n-\n-#define STM32F746_PF12_FUNC_GPIO 0x5c00\n-#define STM32F746_PF12_FUNC_FMC_A6 0x5c0d\n-#define STM32F746_PF12_FUNC_EVENTOUT 0x5c10\n-#define STM32F746_PF12_FUNC_ANALOG 0x5c11\n-\n-#define STM32F746_PF13_FUNC_GPIO 0x5d00\n-#define STM32F746_PF13_FUNC_I2C4_SMBA 0x5d05\n-#define STM32F746_PF13_FUNC_FMC_A7 0x5d0d\n-#define STM32F746_PF13_FUNC_EVENTOUT 0x5d10\n-#define STM32F746_PF13_FUNC_ANALOG 0x5d11\n-\n-#define STM32F746_PF14_FUNC_GPIO 0x5e00\n-#define STM32F746_PF14_FUNC_I2C4_SCL 0x5e05\n-#define STM32F746_PF14_FUNC_FMC_A8 0x5e0d\n-#define STM32F746_PF14_FUNC_EVENTOUT 0x5e10\n-#define STM32F746_PF14_FUNC_ANALOG 0x5e11\n-\n-#define STM32F746_PF15_FUNC_GPIO 0x5f00\n-#define STM32F746_PF15_FUNC_I2C4_SDA 0x5f05\n-#define STM32F746_PF15_FUNC_FMC_A9 0x5f0d\n-#define STM32F746_PF15_FUNC_EVENTOUT 0x5f10\n-#define STM32F746_PF15_FUNC_ANALOG 0x5f11\n-\n-\n-#define STM32F746_PG0_FUNC_GPIO 0x6000\n-#define STM32F746_PG0_FUNC_FMC_A10 0x600d\n-#define STM32F746_PG0_FUNC_EVENTOUT 0x6010\n-#define STM32F746_PG0_FUNC_ANALOG 0x6011\n-\n-#define STM32F746_PG1_FUNC_GPIO 0x6100\n-#define STM32F746_PG1_FUNC_FMC_A11 0x610d\n-#define STM32F746_PG1_FUNC_EVENTOUT 0x6110\n-#define STM32F746_PG1_FUNC_ANALOG 0x6111\n-\n-#define STM32F746_PG2_FUNC_GPIO 0x6200\n-#define STM32F746_PG2_FUNC_FMC_A12 0x620d\n-#define STM32F746_PG2_FUNC_EVENTOUT 0x6210\n-#define STM32F746_PG2_FUNC_ANALOG 0x6211\n-\n-#define STM32F746_PG3_FUNC_GPIO 0x6300\n-#define STM32F746_PG3_FUNC_FMC_A13 0x630d\n-#define STM32F746_PG3_FUNC_EVENTOUT 0x6310\n-#define STM32F746_PG3_FUNC_ANALOG 0x6311\n-\n-#define STM32F746_PG4_FUNC_GPIO 0x6400\n-#define STM32F746_PG4_FUNC_FMC_A14_FMC_BA0 0x640d\n-#define STM32F746_PG4_FUNC_EVENTOUT 0x6410\n-#define STM32F746_PG4_FUNC_ANALOG 0x6411\n-\n-#define STM32F746_PG5_FUNC_GPIO 0x6500\n-#define STM32F746_PG5_FUNC_FMC_A15_FMC_BA1 0x650d\n-#define STM32F746_PG5_FUNC_EVENTOUT 0x6510\n-#define STM32F746_PG5_FUNC_ANALOG 0x6511\n-\n-#define STM32F746_PG6_FUNC_GPIO 0x6600\n-#define STM32F746_PG6_FUNC_DCMI_D12 0x660e\n-#define STM32F746_PG6_FUNC_LCD_R7 0x660f\n-#define STM32F746_PG6_FUNC_EVENTOUT 0x6610\n-#define STM32F746_PG6_FUNC_ANALOG 0x6611\n-\n-#define STM32F746_PG7_FUNC_GPIO 0x6700\n-#define STM32F746_PG7_FUNC_USART6_CK 0x6709\n-#define STM32F746_PG7_FUNC_FMC_INT 0x670d\n-#define STM32F746_PG7_FUNC_DCMI_D13 0x670e\n-#define STM32F746_PG7_FUNC_LCD_CLK 0x670f\n-#define STM32F746_PG7_FUNC_EVENTOUT 0x6710\n-#define STM32F746_PG7_FUNC_ANALOG 0x6711\n-\n-#define STM32F746_PG8_FUNC_GPIO 0x6800\n-#define STM32F746_PG8_FUNC_SPI6_NSS 0x6806\n-#define STM32F746_PG8_FUNC_SPDIFRX_IN2 0x6808\n-#define STM32F746_PG8_FUNC_USART6_RTS 0x6809\n-#define STM32F746_PG8_FUNC_ETH_PPS_OUT 0x680c\n-#define STM32F746_PG8_FUNC_FMC_SDCLK 0x680d\n-#define STM32F746_PG8_FUNC_EVENTOUT 0x6810\n-#define STM32F746_PG8_FUNC_ANALOG 0x6811\n-\n-#define STM32F746_PG9_FUNC_GPIO 0x6900\n-#define STM32F746_PG9_FUNC_SPDIFRX_IN3 0x6908\n-#define STM32F746_PG9_FUNC_USART6_RX 0x6909\n-#define STM32F746_PG9_FUNC_QUADSPI_BK2_IO2 0x690a\n-#define STM32F746_PG9_FUNC_SAI2_FS_B 0x690b\n-#define STM32F746_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d\n-#define STM32F746_PG9_FUNC_DCMI_VSYNC 0x690e\n-#define STM32F746_PG9_FUNC_EVENTOUT 0x6910\n-#define STM32F746_PG9_FUNC_ANALOG 0x6911\n-\n-#define STM32F746_PG10_FUNC_GPIO 0x6a00\n-#define STM32F746_PG10_FUNC_LCD_G3 0x6a0a\n-#define STM32F746_PG10_FUNC_SAI2_SD_B 0x6a0b\n-#define STM32F746_PG10_FUNC_FMC_NE3 0x6a0d\n-#define STM32F746_PG10_FUNC_DCMI_D2 0x6a0e\n-#define STM32F746_PG10_FUNC_LCD_B2 0x6a0f\n-#define STM32F746_PG10_FUNC_EVENTOUT 0x6a10\n-#define STM32F746_PG10_FUNC_ANALOG 0x6a11\n-\n-#define STM32F746_PG11_FUNC_GPIO 0x6b00\n-#define STM32F746_PG11_FUNC_SPDIFRX_IN0 0x6b08\n-#define STM32F746_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c\n-#define STM32F746_PG11_FUNC_DCMI_D3 0x6b0e\n-#define STM32F746_PG11_FUNC_LCD_B3 0x6b0f\n-#define STM32F746_PG11_FUNC_EVENTOUT 0x6b10\n-#define STM32F746_PG11_FUNC_ANALOG 0x6b11\n-\n-#define STM32F746_PG12_FUNC_GPIO 0x6c00\n-#define STM32F746_PG12_FUNC_LPTIM1_IN1 0x6c04\n-#define STM32F746_PG12_FUNC_SPI6_MISO 0x6c06\n-#define STM32F746_PG12_FUNC_SPDIFRX_IN1 0x6c08\n-#define STM32F746_PG12_FUNC_USART6_RTS 0x6c09\n-#define STM32F746_PG12_FUNC_LCD_B4 0x6c0a\n-#define STM32F746_PG12_FUNC_FMC_NE4 0x6c0d\n-#define STM32F746_PG12_FUNC_LCD_B1 0x6c0f\n-#define STM32F746_PG12_FUNC_EVENTOUT 0x6c10\n-#define STM32F746_PG12_FUNC_ANALOG 0x6c11\n-\n-#define STM32F746_PG13_FUNC_GPIO 0x6d00\n-#define STM32F746_PG13_FUNC_TRACED0 0x6d01\n-#define STM32F746_PG13_FUNC_LPTIM1_OUT 0x6d04\n-#define STM32F746_PG13_FUNC_SPI6_SCK 0x6d06\n-#define STM32F746_PG13_FUNC_USART6_CTS 0x6d09\n-#define STM32F746_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c\n-#define STM32F746_PG13_FUNC_FMC_A24 0x6d0d\n-#define STM32F746_PG13_FUNC_LCD_R0 0x6d0f\n-#define STM32F746_PG13_FUNC_EVENTOUT 0x6d10\n-#define STM32F746_PG13_FUNC_ANALOG 0x6d11\n-\n-#define STM32F746_PG14_FUNC_GPIO 0x6e00\n-#define STM32F746_PG14_FUNC_TRACED1 0x6e01\n-#define STM32F746_PG14_FUNC_LPTIM1_ETR 0x6e04\n-#define STM32F746_PG14_FUNC_SPI6_MOSI 0x6e06\n-#define STM32F746_PG14_FUNC_USART6_TX 0x6e09\n-#define STM32F746_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a\n-#define STM32F746_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c\n-#define STM32F746_PG14_FUNC_FMC_A25 0x6e0d\n-#define STM32F746_PG14_FUNC_LCD_B0 0x6e0f\n-#define STM32F746_PG14_FUNC_EVENTOUT 0x6e10\n-#define STM32F746_PG14_FUNC_ANALOG 0x6e11\n-\n-#define STM32F746_PG15_FUNC_GPIO 0x6f00\n-#define STM32F746_PG15_FUNC_USART6_CTS 0x6f09\n-#define STM32F746_PG15_FUNC_FMC_SDNCAS 0x6f0d\n-#define STM32F746_PG15_FUNC_DCMI_D13 0x6f0e\n-#define STM32F746_PG15_FUNC_EVENTOUT 0x6f10\n-#define STM32F746_PG15_FUNC_ANALOG 0x6f11\n-\n-\n-#define STM32F746_PH0_FUNC_GPIO 0x7000\n-#define STM32F746_PH0_FUNC_EVENTOUT 0x7010\n-#define STM32F746_PH0_FUNC_ANALOG 0x7011\n-\n-#define STM32F746_PH1_FUNC_GPIO 0x7100\n-#define STM32F746_PH1_FUNC_EVENTOUT 0x7110\n-#define STM32F746_PH1_FUNC_ANALOG 0x7111\n-\n-#define STM32F746_PH2_FUNC_GPIO 0x7200\n-#define STM32F746_PH2_FUNC_LPTIM1_IN2 0x7204\n-#define STM32F746_PH2_FUNC_QUADSPI_BK2_IO0 0x720a\n-#define STM32F746_PH2_FUNC_SAI2_SCK_B 0x720b\n-#define STM32F746_PH2_FUNC_ETH_MII_CRS 0x720c\n-#define STM32F746_PH2_FUNC_FMC_SDCKE0 0x720d\n-#define STM32F746_PH2_FUNC_LCD_R0 0x720f\n-#define STM32F746_PH2_FUNC_EVENTOUT 0x7210\n-#define STM32F746_PH2_FUNC_ANALOG 0x7211\n-\n-#define STM32F746_PH3_FUNC_GPIO 0x7300\n-#define STM32F746_PH3_FUNC_QUADSPI_BK2_IO1 0x730a\n-#define STM32F746_PH3_FUNC_SAI2_MCLK_B 0x730b\n-#define STM32F746_PH3_FUNC_ETH_MII_COL 0x730c\n-#define STM32F746_PH3_FUNC_FMC_SDNE0 0x730d\n-#define STM32F746_PH3_FUNC_LCD_R1 0x730f\n-#define STM32F746_PH3_FUNC_EVENTOUT 0x7310\n-#define STM32F746_PH3_FUNC_ANALOG 0x7311\n-\n-#define STM32F746_PH4_FUNC_GPIO 0x7400\n-#define STM32F746_PH4_FUNC_I2C2_SCL 0x7405\n-#define STM32F746_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b\n-#define STM32F746_PH4_FUNC_EVENTOUT 0x7410\n-#define STM32F746_PH4_FUNC_ANALOG 0x7411\n-\n-#define STM32F746_PH5_FUNC_GPIO 0x7500\n-#define STM32F746_PH5_FUNC_I2C2_SDA 0x7505\n-#define STM32F746_PH5_FUNC_SPI5_NSS 0x7506\n-#define STM32F746_PH5_FUNC_FMC_SDNWE 0x750d\n-#define STM32F746_PH5_FUNC_EVENTOUT 0x7510\n-#define STM32F746_PH5_FUNC_ANALOG 0x7511\n-\n-#define STM32F746_PH6_FUNC_GPIO 0x7600\n-#define STM32F746_PH6_FUNC_I2C2_SMBA 0x7605\n-#define STM32F746_PH6_FUNC_SPI5_SCK 0x7606\n-#define STM32F746_PH6_FUNC_TIM12_CH1 0x760a\n-#define STM32F746_PH6_FUNC_ETH_MII_RXD2 0x760c\n-#define STM32F746_PH6_FUNC_FMC_SDNE1 0x760d\n-#define STM32F746_PH6_FUNC_DCMI_D8 0x760e\n-#define STM32F746_PH6_FUNC_EVENTOUT 0x7610\n-#define STM32F746_PH6_FUNC_ANALOG 0x7611\n-\n-#define STM32F746_PH7_FUNC_GPIO 0x7700\n-#define STM32F746_PH7_FUNC_I2C3_SCL 0x7705\n-#define STM32F746_PH7_FUNC_SPI5_MISO 0x7706\n-#define STM32F746_PH7_FUNC_ETH_MII_RXD3 0x770c\n-#define STM32F746_PH7_FUNC_FMC_SDCKE1 0x770d\n-#define STM32F746_PH7_FUNC_DCMI_D9 0x770e\n-#define STM32F746_PH7_FUNC_EVENTOUT 0x7710\n-#define STM32F746_PH7_FUNC_ANALOG 0x7711\n-\n-#define STM32F746_PH8_FUNC_GPIO 0x7800\n-#define STM32F746_PH8_FUNC_I2C3_SDA 0x7805\n-#define STM32F746_PH8_FUNC_FMC_D16 0x780d\n-#define STM32F746_PH8_FUNC_DCMI_HSYNC 0x780e\n-#define STM32F746_PH8_FUNC_LCD_R2 0x780f\n-#define STM32F746_PH8_FUNC_EVENTOUT 0x7810\n-#define STM32F746_PH8_FUNC_ANALOG 0x7811\n-\n-#define STM32F746_PH9_FUNC_GPIO 0x7900\n-#define STM32F746_PH9_FUNC_I2C3_SMBA 0x7905\n-#define STM32F746_PH9_FUNC_TIM12_CH2 0x790a\n-#define STM32F746_PH9_FUNC_FMC_D17 0x790d\n-#define STM32F746_PH9_FUNC_DCMI_D0 0x790e\n-#define STM32F746_PH9_FUNC_LCD_R3 0x790f\n-#define STM32F746_PH9_FUNC_EVENTOUT 0x7910\n-#define STM32F746_PH9_FUNC_ANALOG 0x7911\n-\n-#define STM32F746_PH10_FUNC_GPIO 0x7a00\n-#define STM32F746_PH10_FUNC_TIM5_CH1 0x7a03\n-#define STM32F746_PH10_FUNC_I2C4_SMBA 0x7a05\n-#define STM32F746_PH10_FUNC_FMC_D18 0x7a0d\n-#define STM32F746_PH10_FUNC_DCMI_D1 0x7a0e\n-#define STM32F746_PH10_FUNC_LCD_R4 0x7a0f\n-#define STM32F746_PH10_FUNC_EVENTOUT 0x7a10\n-#define STM32F746_PH10_FUNC_ANALOG 0x7a11\n-\n-#define STM32F746_PH11_FUNC_GPIO 0x7b00\n-#define STM32F746_PH11_FUNC_TIM5_CH2 0x7b03\n-#define STM32F746_PH11_FUNC_I2C4_SCL 0x7b05\n-#define STM32F746_PH11_FUNC_FMC_D19 0x7b0d\n-#define STM32F746_PH11_FUNC_DCMI_D2 0x7b0e\n-#define STM32F746_PH11_FUNC_LCD_R5 0x7b0f\n-#define STM32F746_PH11_FUNC_EVENTOUT 0x7b10\n-#define STM32F746_PH11_FUNC_ANALOG 0x7b11\n-\n-#define STM32F746_PH12_FUNC_GPIO 0x7c00\n-#define STM32F746_PH12_FUNC_TIM5_CH3 0x7c03\n-#define STM32F746_PH12_FUNC_I2C4_SDA 0x7c05\n-#define STM32F746_PH12_FUNC_FMC_D20 0x7c0d\n-#define STM32F746_PH12_FUNC_DCMI_D3 0x7c0e\n-#define STM32F746_PH12_FUNC_LCD_R6 0x7c0f\n-#define STM32F746_PH12_FUNC_EVENTOUT 0x7c10\n-#define STM32F746_PH12_FUNC_ANALOG 0x7c11\n-\n-#define STM32F746_PH13_FUNC_GPIO 0x7d00\n-#define STM32F746_PH13_FUNC_TIM8_CH1N 0x7d04\n-#define STM32F746_PH13_FUNC_CAN1_TX 0x7d0a\n-#define STM32F746_PH13_FUNC_FMC_D21 0x7d0d\n-#define STM32F746_PH13_FUNC_LCD_G2 0x7d0f\n-#define STM32F746_PH13_FUNC_EVENTOUT 0x7d10\n-#define STM32F746_PH13_FUNC_ANALOG 0x7d11\n-\n-#define STM32F746_PH14_FUNC_GPIO 0x7e00\n-#define STM32F746_PH14_FUNC_TIM8_CH2N 0x7e04\n-#define STM32F746_PH14_FUNC_FMC_D22 0x7e0d\n-#define STM32F746_PH14_FUNC_DCMI_D4 0x7e0e\n-#define STM32F746_PH14_FUNC_LCD_G3 0x7e0f\n-#define STM32F746_PH14_FUNC_EVENTOUT 0x7e10\n-#define STM32F746_PH14_FUNC_ANALOG 0x7e11\n-\n-#define STM32F746_PH15_FUNC_GPIO 0x7f00\n-#define STM32F746_PH15_FUNC_TIM8_CH3N 0x7f04\n-#define STM32F746_PH15_FUNC_FMC_D23 0x7f0d\n-#define STM32F746_PH15_FUNC_DCMI_D11 0x7f0e\n-#define STM32F746_PH15_FUNC_LCD_G4 0x7f0f\n-#define STM32F746_PH15_FUNC_EVENTOUT 0x7f10\n-#define STM32F746_PH15_FUNC_ANALOG 0x7f11\n-\n-\n-#define STM32F746_PI0_FUNC_GPIO 0x8000\n-#define STM32F746_PI0_FUNC_TIM5_CH4 0x8003\n-#define STM32F746_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006\n-#define STM32F746_PI0_FUNC_FMC_D24 0x800d\n-#define STM32F746_PI0_FUNC_DCMI_D13 0x800e\n-#define STM32F746_PI0_FUNC_LCD_G5 0x800f\n-#define STM32F746_PI0_FUNC_EVENTOUT 0x8010\n-#define STM32F746_PI0_FUNC_ANALOG 0x8011\n-\n-#define STM32F746_PI1_FUNC_GPIO 0x8100\n-#define STM32F746_PI1_FUNC_TIM8_BKIN2 0x8104\n-#define STM32F746_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106\n-#define STM32F746_PI1_FUNC_FMC_D25 0x810d\n-#define STM32F746_PI1_FUNC_DCMI_D8 0x810e\n-#define STM32F746_PI1_FUNC_LCD_G6 0x810f\n-#define STM32F746_PI1_FUNC_EVENTOUT 0x8110\n-#define STM32F746_PI1_FUNC_ANALOG 0x8111\n-\n-#define STM32F746_PI2_FUNC_GPIO 0x8200\n-#define STM32F746_PI2_FUNC_TIM8_CH4 0x8204\n-#define STM32F746_PI2_FUNC_SPI2_MISO 0x8206\n-#define STM32F746_PI2_FUNC_FMC_D26 0x820d\n-#define STM32F746_PI2_FUNC_DCMI_D9 0x820e\n-#define STM32F746_PI2_FUNC_LCD_G7 0x820f\n-#define STM32F746_PI2_FUNC_EVENTOUT 0x8210\n-#define STM32F746_PI2_FUNC_ANALOG 0x8211\n-\n-#define STM32F746_PI3_FUNC_GPIO 0x8300\n-#define STM32F746_PI3_FUNC_TIM8_ETR 0x8304\n-#define STM32F746_PI3_FUNC_SPI2_MOSI_I2S2_SD 0x8306\n-#define STM32F746_PI3_FUNC_FMC_D27 0x830d\n-#define STM32F746_PI3_FUNC_DCMI_D10 0x830e\n-#define STM32F746_PI3_FUNC_EVENTOUT 0x8310\n-#define STM32F746_PI3_FUNC_ANALOG 0x8311\n-\n-#define STM32F746_PI4_FUNC_GPIO 0x8400\n-#define STM32F746_PI4_FUNC_TIM8_BKIN 0x8404\n-#define STM32F746_PI4_FUNC_SAI2_MCLK_A 0x840b\n-#define STM32F746_PI4_FUNC_FMC_NBL2 0x840d\n-#define STM32F746_PI4_FUNC_DCMI_D5 0x840e\n-#define STM32F746_PI4_FUNC_LCD_B4 0x840f\n-#define STM32F746_PI4_FUNC_EVENTOUT 0x8410\n-#define STM32F746_PI4_FUNC_ANALOG 0x8411\n-\n-#define STM32F746_PI5_FUNC_GPIO 0x8500\n-#define STM32F746_PI5_FUNC_TIM8_CH1 0x8504\n-#define STM32F746_PI5_FUNC_SAI2_SCK_A 0x850b\n-#define STM32F746_PI5_FUNC_FMC_NBL3 0x850d\n-#define STM32F746_PI5_FUNC_DCMI_VSYNC 0x850e\n-#define STM32F746_PI5_FUNC_LCD_B5 0x850f\n-#define STM32F746_PI5_FUNC_EVENTOUT 0x8510\n-#define STM32F746_PI5_FUNC_ANALOG 0x8511\n-\n-#define STM32F746_PI6_FUNC_GPIO 0x8600\n-#define STM32F746_PI6_FUNC_TIM8_CH2 0x8604\n-#define STM32F746_PI6_FUNC_SAI2_SD_A 0x860b\n-#define STM32F746_PI6_FUNC_FMC_D28 0x860d\n-#define STM32F746_PI6_FUNC_DCMI_D6 0x860e\n-#define STM32F746_PI6_FUNC_LCD_B6 0x860f\n-#define STM32F746_PI6_FUNC_EVENTOUT 0x8610\n-#define STM32F746_PI6_FUNC_ANALOG 0x8611\n-\n-#define STM32F746_PI7_FUNC_GPIO 0x8700\n-#define STM32F746_PI7_FUNC_TIM8_CH3 0x8704\n-#define STM32F746_PI7_FUNC_SAI2_FS_A 0x870b\n-#define STM32F746_PI7_FUNC_FMC_D29 0x870d\n-#define STM32F746_PI7_FUNC_DCMI_D7 0x870e\n-#define STM32F746_PI7_FUNC_LCD_B7 0x870f\n-#define STM32F746_PI7_FUNC_EVENTOUT 0x8710\n-#define STM32F746_PI7_FUNC_ANALOG 0x8711\n-\n-#define STM32F746_PI8_FUNC_GPIO 0x8800\n-#define STM32F746_PI8_FUNC_EVENTOUT 0x8810\n-#define STM32F746_PI8_FUNC_ANALOG 0x8811\n-\n-#define STM32F746_PI9_FUNC_GPIO 0x8900\n-#define STM32F746_PI9_FUNC_CAN1_RX 0x890a\n-#define STM32F746_PI9_FUNC_FMC_D30 0x890d\n-#define STM32F746_PI9_FUNC_LCD_VSYNC 0x890f\n-#define STM32F746_PI9_FUNC_EVENTOUT 0x8910\n-#define STM32F746_PI9_FUNC_ANALOG 0x8911\n-\n-#define STM32F746_PI10_FUNC_GPIO 0x8a00\n-#define STM32F746_PI10_FUNC_ETH_MII_RX_ER 0x8a0c\n-#define STM32F746_PI10_FUNC_FMC_D31 0x8a0d\n-#define STM32F746_PI10_FUNC_LCD_HSYNC 0x8a0f\n-#define STM32F746_PI10_FUNC_EVENTOUT 0x8a10\n-#define STM32F746_PI10_FUNC_ANALOG 0x8a11\n-\n-#define STM32F746_PI11_FUNC_GPIO 0x8b00\n-#define STM32F746_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b\n-#define STM32F746_PI11_FUNC_EVENTOUT 0x8b10\n-#define STM32F746_PI11_FUNC_ANALOG 0x8b11\n-\n-#define STM32F746_PI12_FUNC_GPIO 0x8c00\n-#define STM32F746_PI12_FUNC_LCD_HSYNC 0x8c0f\n-#define STM32F746_PI12_FUNC_EVENTOUT 0x8c10\n-#define STM32F746_PI12_FUNC_ANALOG 0x8c11\n-\n-#define STM32F746_PI13_FUNC_GPIO 0x8d00\n-#define STM32F746_PI13_FUNC_LCD_VSYNC 0x8d0f\n-#define STM32F746_PI13_FUNC_EVENTOUT 0x8d10\n-#define STM32F746_PI13_FUNC_ANALOG 0x8d11\n-\n-#define STM32F746_PI14_FUNC_GPIO 0x8e00\n-#define STM32F746_PI14_FUNC_LCD_CLK 0x8e0f\n-#define STM32F746_PI14_FUNC_EVENTOUT 0x8e10\n-#define STM32F746_PI14_FUNC_ANALOG 0x8e11\n-\n-#define STM32F746_PI15_FUNC_GPIO 0x8f00\n-#define STM32F746_PI15_FUNC_LCD_R0 0x8f0f\n-#define STM32F746_PI15_FUNC_EVENTOUT 0x8f10\n-#define STM32F746_PI15_FUNC_ANALOG 0x8f11\n-\n-\n-#define STM32F746_PJ0_FUNC_GPIO 0x9000\n-#define STM32F746_PJ0_FUNC_LCD_R1 0x900f\n-#define STM32F746_PJ0_FUNC_EVENTOUT 0x9010\n-#define STM32F746_PJ0_FUNC_ANALOG 0x9011\n-\n-#define STM32F746_PJ1_FUNC_GPIO 0x9100\n-#define STM32F746_PJ1_FUNC_LCD_R2 0x910f\n-#define STM32F746_PJ1_FUNC_EVENTOUT 0x9110\n-#define STM32F746_PJ1_FUNC_ANALOG 0x9111\n-\n-#define STM32F746_PJ2_FUNC_GPIO 0x9200\n-#define STM32F746_PJ2_FUNC_LCD_R3 0x920f\n-#define STM32F746_PJ2_FUNC_EVENTOUT 0x9210\n-#define STM32F746_PJ2_FUNC_ANALOG 0x9211\n-\n-#define STM32F746_PJ3_FUNC_GPIO 0x9300\n-#define STM32F746_PJ3_FUNC_LCD_R4 0x930f\n-#define STM32F746_PJ3_FUNC_EVENTOUT 0x9310\n-#define STM32F746_PJ3_FUNC_ANALOG 0x9311\n-\n-#define STM32F746_PJ4_FUNC_GPIO 0x9400\n-#define STM32F746_PJ4_FUNC_LCD_R5 0x940f\n-#define STM32F746_PJ4_FUNC_EVENTOUT 0x9410\n-#define STM32F746_PJ4_FUNC_ANALOG 0x9411\n-\n-#define STM32F746_PJ5_FUNC_GPIO 0x9500\n-#define STM32F746_PJ5_FUNC_LCD_R6 0x950f\n-#define STM32F746_PJ5_FUNC_EVENTOUT 0x9510\n-#define STM32F746_PJ5_FUNC_ANALOG 0x9511\n-\n-#define STM32F746_PJ6_FUNC_GPIO 0x9600\n-#define STM32F746_PJ6_FUNC_LCD_R7 0x960f\n-#define STM32F746_PJ6_FUNC_EVENTOUT 0x9610\n-#define STM32F746_PJ6_FUNC_ANALOG 0x9611\n-\n-#define STM32F746_PJ7_FUNC_GPIO 0x9700\n-#define STM32F746_PJ7_FUNC_LCD_G0 0x970f\n-#define STM32F746_PJ7_FUNC_EVENTOUT 0x9710\n-#define STM32F746_PJ7_FUNC_ANALOG 0x9711\n-\n-#define STM32F746_PJ8_FUNC_GPIO 0x9800\n-#define STM32F746_PJ8_FUNC_LCD_G1 0x980f\n-#define STM32F746_PJ8_FUNC_EVENTOUT 0x9810\n-#define STM32F746_PJ8_FUNC_ANALOG 0x9811\n-\n-#define STM32F746_PJ9_FUNC_GPIO 0x9900\n-#define STM32F746_PJ9_FUNC_LCD_G2 0x990f\n-#define STM32F746_PJ9_FUNC_EVENTOUT 0x9910\n-#define STM32F746_PJ9_FUNC_ANALOG 0x9911\n-\n-#define STM32F746_PJ10_FUNC_GPIO 0x9a00\n-#define STM32F746_PJ10_FUNC_LCD_G3 0x9a0f\n-#define STM32F746_PJ10_FUNC_EVENTOUT 0x9a10\n-#define STM32F746_PJ10_FUNC_ANALOG 0x9a11\n-\n-#define STM32F746_PJ11_FUNC_GPIO 0x9b00\n-#define STM32F746_PJ11_FUNC_LCD_G4 0x9b0f\n-#define STM32F746_PJ11_FUNC_EVENTOUT 0x9b10\n-#define STM32F746_PJ11_FUNC_ANALOG 0x9b11\n-\n-#define STM32F746_PJ12_FUNC_GPIO 0x9c00\n-#define STM32F746_PJ12_FUNC_LCD_B0 0x9c0f\n-#define STM32F746_PJ12_FUNC_EVENTOUT 0x9c10\n-#define STM32F746_PJ12_FUNC_ANALOG 0x9c11\n-\n-#define STM32F746_PJ13_FUNC_GPIO 0x9d00\n-#define STM32F746_PJ13_FUNC_LCD_B1 0x9d0f\n-#define STM32F746_PJ13_FUNC_EVENTOUT 0x9d10\n-#define STM32F746_PJ13_FUNC_ANALOG 0x9d11\n-\n-#define STM32F746_PJ14_FUNC_GPIO 0x9e00\n-#define STM32F746_PJ14_FUNC_LCD_B2 0x9e0f\n-#define STM32F746_PJ14_FUNC_EVENTOUT 0x9e10\n-#define STM32F746_PJ14_FUNC_ANALOG 0x9e11\n-\n-#define STM32F746_PJ15_FUNC_GPIO 0x9f00\n-#define STM32F746_PJ15_FUNC_LCD_B3 0x9f0f\n-#define STM32F746_PJ15_FUNC_EVENTOUT 0x9f10\n-#define STM32F746_PJ15_FUNC_ANALOG 0x9f11\n-\n-\n-#define STM32F746_PK0_FUNC_GPIO 0xa000\n-#define STM32F746_PK0_FUNC_LCD_G5 0xa00f\n-#define STM32F746_PK0_FUNC_EVENTOUT 0xa010\n-#define STM32F746_PK0_FUNC_ANALOG 0xa011\n-\n-#define STM32F746_PK1_FUNC_GPIO 0xa100\n-#define STM32F746_PK1_FUNC_LCD_G6 0xa10f\n-#define STM32F746_PK1_FUNC_EVENTOUT 0xa110\n-#define STM32F746_PK1_FUNC_ANALOG 0xa111\n-\n-#define STM32F746_PK2_FUNC_GPIO 0xa200\n-#define STM32F746_PK2_FUNC_LCD_G7 0xa20f\n-#define STM32F746_PK2_FUNC_EVENTOUT 0xa210\n-#define STM32F746_PK2_FUNC_ANALOG 0xa211\n-\n-#define STM32F746_PK3_FUNC_GPIO 0xa300\n-#define STM32F746_PK3_FUNC_LCD_B4 0xa30f\n-#define STM32F746_PK3_FUNC_EVENTOUT 0xa310\n-#define STM32F746_PK3_FUNC_ANALOG 0xa311\n-\n-#define STM32F746_PK4_FUNC_GPIO 0xa400\n-#define STM32F746_PK4_FUNC_LCD_B5 0xa40f\n-#define STM32F746_PK4_FUNC_EVENTOUT 0xa410\n-#define STM32F746_PK4_FUNC_ANALOG 0xa411\n-\n-#define STM32F746_PK5_FUNC_GPIO 0xa500\n-#define STM32F746_PK5_FUNC_LCD_B6 0xa50f\n-#define STM32F746_PK5_FUNC_EVENTOUT 0xa510\n-#define STM32F746_PK5_FUNC_ANALOG 0xa511\n-\n-#define STM32F746_PK6_FUNC_GPIO 0xa600\n-#define STM32F746_PK6_FUNC_LCD_B7 0xa60f\n-#define STM32F746_PK6_FUNC_EVENTOUT 0xa610\n-#define STM32F746_PK6_FUNC_ANALOG 0xa611\n-\n-#define STM32F746_PK7_FUNC_GPIO 0xa700\n-#define STM32F746_PK7_FUNC_LCD_DE 0xa70f\n-#define STM32F746_PK7_FUNC_EVENTOUT 0xa710\n-#define STM32F746_PK7_FUNC_ANALOG 0xa711\n-\n-#endif /* _DT_BINDINGS_STM32F746_PINFUNC_H */\ndiff --git a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h b/include/dt-bindings/pinctrl/stm32h7-pinfunc.h\ndeleted file mode 100644\nindex cb673b5..0000000\n--- a/include/dt-bindings/pinctrl/stm32h7-pinfunc.h\n+++ /dev/null\n@@ -1,1612 +0,0 @@\n-#ifndef _DT_BINDINGS_STM32H7_PINFUNC_H\n-#define _DT_BINDINGS_STM32H7_PINFUNC_H\n-\n-#define STM32H7_PA0_FUNC_GPIO 0x0\n-#define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2\n-#define STM32H7_PA0_FUNC_TIM5_CH1 0x3\n-#define STM32H7_PA0_FUNC_TIM8_ETR 0x4\n-#define STM32H7_PA0_FUNC_TIM15_BKIN 0x5\n-#define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8\n-#define STM32H7_PA0_FUNC_UART4_TX 0x9\n-#define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa\n-#define STM32H7_PA0_FUNC_SAI2_SD_B 0xb\n-#define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc\n-#define STM32H7_PA0_FUNC_EVENTOUT 0x10\n-#define STM32H7_PA0_FUNC_ANALOG 0x11\n-\n-#define STM32H7_PA1_FUNC_GPIO 0x100\n-#define STM32H7_PA1_FUNC_TIM2_CH2 0x102\n-#define STM32H7_PA1_FUNC_TIM5_CH2 0x103\n-#define STM32H7_PA1_FUNC_LPTIM3_OUT 0x104\n-#define STM32H7_PA1_FUNC_TIM15_CH1N 0x105\n-#define STM32H7_PA1_FUNC_USART2_RTS 0x108\n-#define STM32H7_PA1_FUNC_UART4_RX 0x109\n-#define STM32H7_PA1_FUNC_QUADSPI_BK1_IO3 0x10a\n-#define STM32H7_PA1_FUNC_SAI2_MCK_B 0x10b\n-#define STM32H7_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK 0x10c\n-#define STM32H7_PA1_FUNC_LCD_R2 0x10f\n-#define STM32H7_PA1_FUNC_EVENTOUT 0x110\n-#define STM32H7_PA1_FUNC_ANALOG 0x111\n-\n-#define STM32H7_PA2_FUNC_GPIO 0x200\n-#define STM32H7_PA2_FUNC_TIM2_CH3 0x202\n-#define STM32H7_PA2_FUNC_TIM5_CH3 0x203\n-#define STM32H7_PA2_FUNC_LPTIM4_OUT 0x204\n-#define STM32H7_PA2_FUNC_TIM15_CH1 0x205\n-#define STM32H7_PA2_FUNC_USART2_TX 0x208\n-#define STM32H7_PA2_FUNC_SAI2_SCK_B 0x209\n-#define STM32H7_PA2_FUNC_ETH_MDIO 0x20c\n-#define STM32H7_PA2_FUNC_MDIOS_MDIO 0x20d\n-#define STM32H7_PA2_FUNC_LCD_R1 0x20f\n-#define STM32H7_PA2_FUNC_EVENTOUT 0x210\n-#define STM32H7_PA2_FUNC_ANALOG 0x211\n-\n-#define STM32H7_PA3_FUNC_GPIO 0x300\n-#define STM32H7_PA3_FUNC_TIM2_CH4 0x302\n-#define STM32H7_PA3_FUNC_TIM5_CH4 0x303\n-#define STM32H7_PA3_FUNC_LPTIM5_OUT 0x304\n-#define STM32H7_PA3_FUNC_TIM15_CH2 0x305\n-#define STM32H7_PA3_FUNC_USART2_RX 0x308\n-#define STM32H7_PA3_FUNC_LCD_B2 0x30a\n-#define STM32H7_PA3_FUNC_OTG_HS_ULPI_D0 0x30b\n-#define STM32H7_PA3_FUNC_ETH_MII_COL 0x30c\n-#define STM32H7_PA3_FUNC_LCD_B5 0x30f\n-#define STM32H7_PA3_FUNC_EVENTOUT 0x310\n-#define STM32H7_PA3_FUNC_ANALOG 0x311\n-\n-#define STM32H7_PA4_FUNC_GPIO 0x400\n-#define STM32H7_PA4_FUNC_TIM5_ETR 0x403\n-#define STM32H7_PA4_FUNC_SPI1_NSS_I2S1_WS 0x406\n-#define STM32H7_PA4_FUNC_SPI3_NSS_I2S3_WS 0x407\n-#define STM32H7_PA4_FUNC_USART2_CK 0x408\n-#define STM32H7_PA4_FUNC_SPI6_NSS 0x409\n-#define STM32H7_PA4_FUNC_OTG_HS_SOF 0x40d\n-#define STM32H7_PA4_FUNC_DCMI_HSYNC 0x40e\n-#define STM32H7_PA4_FUNC_LCD_VSYNC 0x40f\n-#define STM32H7_PA4_FUNC_EVENTOUT 0x410\n-#define STM32H7_PA4_FUNC_ANALOG 0x411\n-\n-#define STM32H7_PA5_FUNC_GPIO 0x500\n-#define STM32H7_PA5_FUNC_TIM2_CH1_TIM2_ETR 0x502\n-#define STM32H7_PA5_FUNC_TIM8_CH1N 0x504\n-#define STM32H7_PA5_FUNC_SPI1_SCK_I2S1_CK 0x506\n-#define STM32H7_PA5_FUNC_SPI6_SCK 0x509\n-#define STM32H7_PA5_FUNC_OTG_HS_ULPI_CK 0x50b\n-#define STM32H7_PA5_FUNC_LCD_R4 0x50f\n-#define STM32H7_PA5_FUNC_EVENTOUT 0x510\n-#define STM32H7_PA5_FUNC_ANALOG 0x511\n-\n-#define STM32H7_PA6_FUNC_GPIO 0x600\n-#define STM32H7_PA6_FUNC_TIM1_BKIN 0x602\n-#define STM32H7_PA6_FUNC_TIM3_CH1 0x603\n-#define STM32H7_PA6_FUNC_TIM8_BKIN 0x604\n-#define STM32H7_PA6_FUNC_SPI1_MISO_I2S1_SDI 0x606\n-#define STM32H7_PA6_FUNC_SPI6_MISO 0x609\n-#define STM32H7_PA6_FUNC_TIM13_CH1 0x60a\n-#define STM32H7_PA6_FUNC_TIM8_BKIN_COMP12 0x60b\n-#define STM32H7_PA6_FUNC_MDIOS_MDC 0x60c\n-#define STM32H7_PA6_FUNC_TIM1_BKIN_COMP12 0x60d\n-#define STM32H7_PA6_FUNC_DCMI_PIXCLK 0x60e\n-#define STM32H7_PA6_FUNC_LCD_G2 0x60f\n-#define STM32H7_PA6_FUNC_EVENTOUT 0x610\n-#define STM32H7_PA6_FUNC_ANALOG 0x611\n-\n-#define STM32H7_PA7_FUNC_GPIO 0x700\n-#define STM32H7_PA7_FUNC_TIM1_CH1N 0x702\n-#define STM32H7_PA7_FUNC_TIM3_CH2 0x703\n-#define STM32H7_PA7_FUNC_TIM8_CH1N 0x704\n-#define STM32H7_PA7_FUNC_SPI1_MOSI_I2S1_SDO 0x706\n-#define STM32H7_PA7_FUNC_SPI6_MOSI 0x709\n-#define STM32H7_PA7_FUNC_TIM14_CH1 0x70a\n-#define STM32H7_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV 0x70c\n-#define STM32H7_PA7_FUNC_FMC_SDNWE 0x70d\n-#define STM32H7_PA7_FUNC_EVENTOUT 0x710\n-#define STM32H7_PA7_FUNC_ANALOG 0x711\n-\n-#define STM32H7_PA8_FUNC_GPIO 0x800\n-#define STM32H7_PA8_FUNC_MCO1 0x801\n-#define STM32H7_PA8_FUNC_TIM1_CH1 0x802\n-#define STM32H7_PA8_FUNC_HRTIM_CHB2 0x803\n-#define STM32H7_PA8_FUNC_TIM8_BKIN2 0x804\n-#define STM32H7_PA8_FUNC_I2C3_SCL 0x805\n-#define STM32H7_PA8_FUNC_USART1_CK 0x808\n-#define STM32H7_PA8_FUNC_OTG_FS_SOF 0x80b\n-#define STM32H7_PA8_FUNC_UART7_RX 0x80c\n-#define STM32H7_PA8_FUNC_TIM8_BKIN2_COMP12 0x80d\n-#define STM32H7_PA8_FUNC_LCD_B3 0x80e\n-#define STM32H7_PA8_FUNC_LCD_R6 0x80f\n-#define STM32H7_PA8_FUNC_EVENTOUT 0x810\n-#define STM32H7_PA8_FUNC_ANALOG 0x811\n-\n-#define STM32H7_PA9_FUNC_GPIO 0x900\n-#define STM32H7_PA9_FUNC_TIM1_CH2 0x902\n-#define STM32H7_PA9_FUNC_HRTIM_CHC1 0x903\n-#define STM32H7_PA9_FUNC_LPUART1_TX 0x904\n-#define STM32H7_PA9_FUNC_I2C3_SMBA 0x905\n-#define STM32H7_PA9_FUNC_SPI2_SCK_I2S2_CK 0x906\n-#define STM32H7_PA9_FUNC_USART1_TX 0x908\n-#define STM32H7_PA9_FUNC_CAN1_RXFD 0x90a\n-#define STM32H7_PA9_FUNC_ETH_TX_ER 0x90c\n-#define STM32H7_PA9_FUNC_DCMI_D0 0x90e\n-#define STM32H7_PA9_FUNC_LCD_R5 0x90f\n-#define STM32H7_PA9_FUNC_EVENTOUT 0x910\n-#define STM32H7_PA9_FUNC_ANALOG 0x911\n-\n-#define STM32H7_PA10_FUNC_GPIO 0xa00\n-#define STM32H7_PA10_FUNC_TIM1_CH3 0xa02\n-#define STM32H7_PA10_FUNC_HRTIM_CHC2 0xa03\n-#define STM32H7_PA10_FUNC_LPUART1_RX 0xa04\n-#define STM32H7_PA10_FUNC_USART1_RX 0xa08\n-#define STM32H7_PA10_FUNC_CAN1_TXFD 0xa0a\n-#define STM32H7_PA10_FUNC_OTG_FS_ID 0xa0b\n-#define STM32H7_PA10_FUNC_MDIOS_MDIO 0xa0c\n-#define STM32H7_PA10_FUNC_LCD_B4 0xa0d\n-#define STM32H7_PA10_FUNC_DCMI_D1 0xa0e\n-#define STM32H7_PA10_FUNC_LCD_B1 0xa0f\n-#define STM32H7_PA10_FUNC_EVENTOUT 0xa10\n-#define STM32H7_PA10_FUNC_ANALOG 0xa11\n-\n-#define STM32H7_PA11_FUNC_GPIO 0xb00\n-#define STM32H7_PA11_FUNC_TIM1_CH4 0xb02\n-#define STM32H7_PA11_FUNC_HRTIM_CHD1 0xb03\n-#define STM32H7_PA11_FUNC_LPUART1_CTS 0xb04\n-#define STM32H7_PA11_FUNC_SPI2_NSS_I2S2_WS 0xb06\n-#define STM32H7_PA11_FUNC_UART4_RX 0xb07\n-#define STM32H7_PA11_FUNC_USART1_CTS_NSS 0xb08\n-#define STM32H7_PA11_FUNC_CAN1_RX 0xb0a\n-#define STM32H7_PA11_FUNC_OTG_FS_DM 0xb0b\n-#define STM32H7_PA11_FUNC_LCD_R4 0xb0f\n-#define STM32H7_PA11_FUNC_EVENTOUT 0xb10\n-#define STM32H7_PA11_FUNC_ANALOG 0xb11\n-\n-#define STM32H7_PA12_FUNC_GPIO 0xc00\n-#define STM32H7_PA12_FUNC_TIM1_ETR 0xc02\n-#define STM32H7_PA12_FUNC_HRTIM_CHD2 0xc03\n-#define STM32H7_PA12_FUNC_LPUART1_RTS 0xc04\n-#define STM32H7_PA12_FUNC_SPI2_SCK_I2S2_CK 0xc06\n-#define STM32H7_PA12_FUNC_UART4_TX 0xc07\n-#define STM32H7_PA12_FUNC_USART1_RTS 0xc08\n-#define STM32H7_PA12_FUNC_SAI2_FS_B 0xc09\n-#define STM32H7_PA12_FUNC_CAN1_TX 0xc0a\n-#define STM32H7_PA12_FUNC_OTG_FS_DP 0xc0b\n-#define STM32H7_PA12_FUNC_LCD_R5 0xc0f\n-#define STM32H7_PA12_FUNC_EVENTOUT 0xc10\n-#define STM32H7_PA12_FUNC_ANALOG 0xc11\n-\n-#define STM32H7_PA13_FUNC_GPIO 0xd00\n-#define STM32H7_PA13_FUNC_JTMS_SWDIO 0xd01\n-#define STM32H7_PA13_FUNC_EVENTOUT 0xd10\n-#define STM32H7_PA13_FUNC_ANALOG 0xd11\n-\n-#define STM32H7_PA14_FUNC_GPIO 0xe00\n-#define STM32H7_PA14_FUNC_JTCK_SWCLK 0xe01\n-#define STM32H7_PA14_FUNC_EVENTOUT 0xe10\n-#define STM32H7_PA14_FUNC_ANALOG 0xe11\n-\n-#define STM32H7_PA15_FUNC_GPIO 0xf00\n-#define STM32H7_PA15_FUNC_JTDI 0xf01\n-#define STM32H7_PA15_FUNC_TIM2_CH1_TIM2_ETR 0xf02\n-#define STM32H7_PA15_FUNC_HRTIM_FLT1 0xf03\n-#define STM32H7_PA15_FUNC_HDMI_CEC 0xf05\n-#define STM32H7_PA15_FUNC_SPI1_NSS_I2S1_WS 0xf06\n-#define STM32H7_PA15_FUNC_SPI3_NSS_I2S3_WS 0xf07\n-#define STM32H7_PA15_FUNC_SPI6_NSS 0xf08\n-#define STM32H7_PA15_FUNC_UART4_RTS 0xf09\n-#define STM32H7_PA15_FUNC_UART7_TX 0xf0c\n-#define STM32H7_PA15_FUNC_DSI_TE 0xf0e\n-#define STM32H7_PA15_FUNC_EVENTOUT 0xf10\n-#define STM32H7_PA15_FUNC_ANALOG 0xf11\n-\n-#define STM32H7_PB0_FUNC_GPIO 0x1000\n-#define STM32H7_PB0_FUNC_TIM1_CH2N 0x1002\n-#define STM32H7_PB0_FUNC_TIM3_CH3 0x1003\n-#define STM32H7_PB0_FUNC_TIM8_CH2N 0x1004\n-#define STM32H7_PB0_FUNC_DFSDM_CKOUT 0x1007\n-#define STM32H7_PB0_FUNC_UART4_CTS 0x1009\n-#define STM32H7_PB0_FUNC_LCD_R3 0x100a\n-#define STM32H7_PB0_FUNC_OTG_HS_ULPI_D1 0x100b\n-#define STM32H7_PB0_FUNC_ETH_MII_RXD2 0x100c\n-#define STM32H7_PB0_FUNC_LCD_G1 0x100f\n-#define STM32H7_PB0_FUNC_EVENTOUT 0x1010\n-#define STM32H7_PB0_FUNC_ANALOG 0x1011\n-\n-#define STM32H7_PB1_FUNC_GPIO 0x1100\n-#define STM32H7_PB1_FUNC_TIM1_CH3N 0x1102\n-#define STM32H7_PB1_FUNC_TIM3_CH4 0x1103\n-#define STM32H7_PB1_FUNC_TIM8_CH3N 0x1104\n-#define STM32H7_PB1_FUNC_DFSDM_DATIN1 0x1107\n-#define STM32H7_PB1_FUNC_LCD_R6 0x110a\n-#define STM32H7_PB1_FUNC_OTG_HS_ULPI_D2 0x110b\n-#define STM32H7_PB1_FUNC_ETH_MII_RXD3 0x110c\n-#define STM32H7_PB1_FUNC_LCD_G0 0x110f\n-#define STM32H7_PB1_FUNC_EVENTOUT 0x1110\n-#define STM32H7_PB1_FUNC_ANALOG 0x1111\n-\n-#define STM32H7_PB2_FUNC_GPIO 0x1200\n-#define STM32H7_PB2_FUNC_SAI1_D1 0x1203\n-#define STM32H7_PB2_FUNC_DFSDM_CKIN1 0x1205\n-#define STM32H7_PB2_FUNC_SAI1_SD_A 0x1207\n-#define STM32H7_PB2_FUNC_SPI3_MOSI_I2S3_SDO 0x1208\n-#define STM32H7_PB2_FUNC_SAI4_SD_A 0x1209\n-#define STM32H7_PB2_FUNC_QUADSPI_CLK 0x120a\n-#define STM32H7_PB2_FUNC_SAI4_D1 0x120b\n-#define STM32H7_PB2_FUNC_ETH_TX_ER 0x120c\n-#define STM32H7_PB2_FUNC_EVENTOUT 0x1210\n-#define STM32H7_PB2_FUNC_ANALOG 0x1211\n-\n-#define STM32H7_PB3_FUNC_GPIO 0x1300\n-#define STM32H7_PB3_FUNC_JTDO_TRACESWO 0x1301\n-#define STM32H7_PB3_FUNC_TIM2_CH2 0x1302\n-#define STM32H7_PB3_FUNC_HRTIM_FLT4 0x1303\n-#define STM32H7_PB3_FUNC_SPI1_SCK_I2S1_CK 0x1306\n-#define STM32H7_PB3_FUNC_SPI3_SCK_I2S3_CK 0x1307\n-#define STM32H7_PB3_FUNC_SPI6_SCK 0x1309\n-#define STM32H7_PB3_FUNC_SDMMC2_D2 0x130a\n-#define STM32H7_PB3_FUNC_UART7_RX 0x130c\n-#define STM32H7_PB3_FUNC_EVENTOUT 0x1310\n-#define STM32H7_PB3_FUNC_ANALOG 0x1311\n-\n-#define STM32H7_PB4_FUNC_GPIO 0x1400\n-#define STM32H7_PB4_FUNC_NJTRST 0x1401\n-#define STM32H7_PB4_FUNC_TIM16_BKIN 0x1402\n-#define STM32H7_PB4_FUNC_TIM3_CH1 0x1403\n-#define STM32H7_PB4_FUNC_HRTIM_EEV6 0x1404\n-#define STM32H7_PB4_FUNC_SPI1_MISO_I2S1_SDI 0x1406\n-#define STM32H7_PB4_FUNC_SPI3_MISO_I2S3_SDI 0x1407\n-#define STM32H7_PB4_FUNC_SPI2_NSS_I2S2_WS 0x1408\n-#define STM32H7_PB4_FUNC_SPI6_MISO 0x1409\n-#define STM32H7_PB4_FUNC_SDMMC2_D3 0x140a\n-#define STM32H7_PB4_FUNC_UART7_TX 0x140c\n-#define STM32H7_PB4_FUNC_EVENTOUT 0x1410\n-#define STM32H7_PB4_FUNC_ANALOG 0x1411\n-\n-#define STM32H7_PB5_FUNC_GPIO 0x1500\n-#define STM32H7_PB5_FUNC_TIM17_BKIN 0x1502\n-#define STM32H7_PB5_FUNC_TIM3_CH2 0x1503\n-#define STM32H7_PB5_FUNC_HRTIM_EEV7 0x1504\n-#define STM32H7_PB5_FUNC_I2C1_SMBA 0x1505\n-#define STM32H7_PB5_FUNC_SPI1_MOSI_I2S1_SDO 0x1506\n-#define STM32H7_PB5_FUNC_I2C4_SMBA 0x1507\n-#define STM32H7_PB5_FUNC_SPI3_MOSI_I2S3_SDO 0x1508\n-#define STM32H7_PB5_FUNC_SPI6_MOSI 0x1509\n-#define STM32H7_PB5_FUNC_CAN2_RX 0x150a\n-#define STM32H7_PB5_FUNC_OTG_HS_ULPI_D7 0x150b\n-#define STM32H7_PB5_FUNC_ETH_PPS_OUT 0x150c\n-#define STM32H7_PB5_FUNC_FMC_SDCKE1 0x150d\n-#define STM32H7_PB5_FUNC_DCMI_D10 0x150e\n-#define STM32H7_PB5_FUNC_UART5_RX 0x150f\n-#define STM32H7_PB5_FUNC_EVENTOUT 0x1510\n-#define STM32H7_PB5_FUNC_ANALOG 0x1511\n-\n-#define STM32H7_PB6_FUNC_GPIO 0x1600\n-#define STM32H7_PB6_FUNC_TIM16_CH1N 0x1602\n-#define STM32H7_PB6_FUNC_TIM4_CH1 0x1603\n-#define STM32H7_PB6_FUNC_HRTIM_EEV8 0x1604\n-#define STM32H7_PB6_FUNC_I2C1_SCL 0x1605\n-#define STM32H7_PB6_FUNC_HDMI_CEC 0x1606\n-#define STM32H7_PB6_FUNC_I2C4_SCL 0x1607\n-#define STM32H7_PB6_FUNC_USART1_TX 0x1608\n-#define STM32H7_PB6_FUNC_LPUART1_TX 0x1609\n-#define STM32H7_PB6_FUNC_CAN2_TX 0x160a\n-#define STM32H7_PB6_FUNC_QUADSPI_BK1_NCS 0x160b\n-#define STM32H7_PB6_FUNC_DFSDM_DATIN5 0x160c\n-#define STM32H7_PB6_FUNC_FMC_SDNE1 0x160d\n-#define STM32H7_PB6_FUNC_DCMI_D5 0x160e\n-#define STM32H7_PB6_FUNC_UART5_TX 0x160f\n-#define STM32H7_PB6_FUNC_EVENTOUT 0x1610\n-#define STM32H7_PB6_FUNC_ANALOG 0x1611\n-\n-#define STM32H7_PB7_FUNC_GPIO 0x1700\n-#define STM32H7_PB7_FUNC_TIM17_CH1N 0x1702\n-#define STM32H7_PB7_FUNC_TIM4_CH2 0x1703\n-#define STM32H7_PB7_FUNC_HRTIM_EEV9 0x1704\n-#define STM32H7_PB7_FUNC_I2C1_SDA 0x1705\n-#define STM32H7_PB7_FUNC_I2C4_SDA 0x1707\n-#define STM32H7_PB7_FUNC_USART1_RX 0x1708\n-#define STM32H7_PB7_FUNC_LPUART1_RX 0x1709\n-#define STM32H7_PB7_FUNC_CAN2_TXFD 0x170a\n-#define STM32H7_PB7_FUNC_DFSDM_CKIN5 0x170c\n-#define STM32H7_PB7_FUNC_FMC_NL 0x170d\n-#define STM32H7_PB7_FUNC_DCMI_VSYNC 0x170e\n-#define STM32H7_PB7_FUNC_EVENTOUT 0x1710\n-#define STM32H7_PB7_FUNC_ANALOG 0x1711\n-\n-#define STM32H7_PB8_FUNC_GPIO 0x1800\n-#define STM32H7_PB8_FUNC_TIM16_CH1 0x1802\n-#define STM32H7_PB8_FUNC_TIM4_CH3 0x1803\n-#define STM32H7_PB8_FUNC_DFSDM_CKIN7 0x1804\n-#define STM32H7_PB8_FUNC_I2C1_SCL 0x1805\n-#define STM32H7_PB8_FUNC_I2C4_SCL 0x1807\n-#define STM32H7_PB8_FUNC_SDMMC1_CKIN 0x1808\n-#define STM32H7_PB8_FUNC_UART4_RX 0x1809\n-#define STM32H7_PB8_FUNC_CAN1_RX 0x180a\n-#define STM32H7_PB8_FUNC_SDMMC2_D4 0x180b\n-#define STM32H7_PB8_FUNC_ETH_MII_TXD3 0x180c\n-#define STM32H7_PB8_FUNC_SDMMC1_D4 0x180d\n-#define STM32H7_PB8_FUNC_DCMI_D6 0x180e\n-#define STM32H7_PB8_FUNC_LCD_B6 0x180f\n-#define STM32H7_PB8_FUNC_EVENTOUT 0x1810\n-#define STM32H7_PB8_FUNC_ANALOG 0x1811\n-\n-#define STM32H7_PB9_FUNC_GPIO 0x1900\n-#define STM32H7_PB9_FUNC_TIM17_CH1 0x1902\n-#define STM32H7_PB9_FUNC_TIM4_CH4 0x1903\n-#define STM32H7_PB9_FUNC_DFSDM_DATIN7 0x1904\n-#define STM32H7_PB9_FUNC_I2C1_SDA 0x1905\n-#define STM32H7_PB9_FUNC_SPI2_NSS_I2S2_WS 0x1906\n-#define STM32H7_PB9_FUNC_I2C4_SDA 0x1907\n-#define STM32H7_PB9_FUNC_SDMMC1_CDIR 0x1908\n-#define STM32H7_PB9_FUNC_UART4_TX 0x1909\n-#define STM32H7_PB9_FUNC_CAN1_TX 0x190a\n-#define STM32H7_PB9_FUNC_SDMMC2_D5 0x190b\n-#define STM32H7_PB9_FUNC_I2C4_SMBA 0x190c\n-#define STM32H7_PB9_FUNC_SDMMC1_D5 0x190d\n-#define STM32H7_PB9_FUNC_DCMI_D7 0x190e\n-#define STM32H7_PB9_FUNC_LCD_B7 0x190f\n-#define STM32H7_PB9_FUNC_EVENTOUT 0x1910\n-#define STM32H7_PB9_FUNC_ANALOG 0x1911\n-\n-#define STM32H7_PB10_FUNC_GPIO 0x1a00\n-#define STM32H7_PB10_FUNC_TIM2_CH3 0x1a02\n-#define STM32H7_PB10_FUNC_HRTIM_SCOUT 0x1a03\n-#define STM32H7_PB10_FUNC_LPTIM2_IN1 0x1a04\n-#define STM32H7_PB10_FUNC_I2C2_SCL 0x1a05\n-#define STM32H7_PB10_FUNC_SPI2_SCK_I2S2_CK 0x1a06\n-#define STM32H7_PB10_FUNC_DFSDM_DATIN7 0x1a07\n-#define STM32H7_PB10_FUNC_USART3_TX 0x1a08\n-#define STM32H7_PB10_FUNC_QUADSPI_BK1_NCS 0x1a0a\n-#define STM32H7_PB10_FUNC_OTG_HS_ULPI_D3 0x1a0b\n-#define STM32H7_PB10_FUNC_ETH_MII_RX_ER 0x1a0c\n-#define STM32H7_PB10_FUNC_LCD_G4 0x1a0f\n-#define STM32H7_PB10_FUNC_EVENTOUT 0x1a10\n-#define STM32H7_PB10_FUNC_ANALOG 0x1a11\n-\n-#define STM32H7_PB11_FUNC_GPIO 0x1b00\n-#define STM32H7_PB11_FUNC_TIM2_CH4 0x1b02\n-#define STM32H7_PB11_FUNC_HRTIM_SCIN 0x1b03\n-#define STM32H7_PB11_FUNC_LPTIM2_ETR 0x1b04\n-#define STM32H7_PB11_FUNC_I2C2_SDA 0x1b05\n-#define STM32H7_PB11_FUNC_DFSDM_CKIN7 0x1b07\n-#define STM32H7_PB11_FUNC_USART3_RX 0x1b08\n-#define STM32H7_PB11_FUNC_OTG_HS_ULPI_D4 0x1b0b\n-#define STM32H7_PB11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x1b0c\n-#define STM32H7_PB11_FUNC_DSI_TE 0x1b0e\n-#define STM32H7_PB11_FUNC_LCD_G5 0x1b0f\n-#define STM32H7_PB11_FUNC_EVENTOUT 0x1b10\n-#define STM32H7_PB11_FUNC_ANALOG 0x1b11\n-\n-#define STM32H7_PB12_FUNC_GPIO 0x1c00\n-#define STM32H7_PB12_FUNC_TIM1_BKIN 0x1c02\n-#define STM32H7_PB12_FUNC_I2C2_SMBA 0x1c05\n-#define STM32H7_PB12_FUNC_SPI2_NSS_I2S2_WS 0x1c06\n-#define STM32H7_PB12_FUNC_DFSDM_DATIN1 0x1c07\n-#define STM32H7_PB12_FUNC_USART3_CK 0x1c08\n-#define STM32H7_PB12_FUNC_CAN2_RX 0x1c0a\n-#define STM32H7_PB12_FUNC_OTG_HS_ULPI_D5 0x1c0b\n-#define STM32H7_PB12_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x1c0c\n-#define STM32H7_PB12_FUNC_OTG_HS_ID 0x1c0d\n-#define STM32H7_PB12_FUNC_TIM1_BKIN_COMP12 0x1c0e\n-#define STM32H7_PB12_FUNC_UART5_RX 0x1c0f\n-#define STM32H7_PB12_FUNC_EVENTOUT 0x1c10\n-#define STM32H7_PB12_FUNC_ANALOG 0x1c11\n-\n-#define STM32H7_PB13_FUNC_GPIO 0x1d00\n-#define STM32H7_PB13_FUNC_TIM1_CH1N 0x1d02\n-#define STM32H7_PB13_FUNC_LPTIM2_OUT 0x1d04\n-#define STM32H7_PB13_FUNC_SPI2_SCK_I2S2_CK 0x1d06\n-#define STM32H7_PB13_FUNC_DFSDM_CKIN1 0x1d07\n-#define STM32H7_PB13_FUNC_USART3_CTS_NSS 0x1d08\n-#define STM32H7_PB13_FUNC_CAN2_TX 0x1d0a\n-#define STM32H7_PB13_FUNC_OTG_HS_ULPI_D6 0x1d0b\n-#define STM32H7_PB13_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x1d0c\n-#define STM32H7_PB13_FUNC_UART5_TX 0x1d0f\n-#define STM32H7_PB13_FUNC_EVENTOUT 0x1d10\n-#define STM32H7_PB13_FUNC_ANALOG 0x1d11\n-\n-#define STM32H7_PB14_FUNC_GPIO 0x1e00\n-#define STM32H7_PB14_FUNC_TIM1_CH2N 0x1e02\n-#define STM32H7_PB14_FUNC_TIM8_CH2N 0x1e04\n-#define STM32H7_PB14_FUNC_USART1_TX 0x1e05\n-#define STM32H7_PB14_FUNC_SPI2_MISO_I2S2_SDI 0x1e06\n-#define STM32H7_PB14_FUNC_DFSDM_DATIN2 0x1e07\n-#define STM32H7_PB14_FUNC_USART3_RTS 0x1e08\n-#define STM32H7_PB14_FUNC_UART4_RTS 0x1e09\n-#define STM32H7_PB14_FUNC_SDMMC2_D0 0x1e0a\n-#define STM32H7_PB14_FUNC_OTG_HS_DM 0x1e0d\n-#define STM32H7_PB14_FUNC_EVENTOUT 0x1e10\n-#define STM32H7_PB14_FUNC_ANALOG 0x1e11\n-\n-#define STM32H7_PB15_FUNC_GPIO 0x1f00\n-#define STM32H7_PB15_FUNC_RTC_REFIN 0x1f01\n-#define STM32H7_PB15_FUNC_TIM1_CH3N 0x1f02\n-#define STM32H7_PB15_FUNC_TIM8_CH3N 0x1f04\n-#define STM32H7_PB15_FUNC_USART1_RX 0x1f05\n-#define STM32H7_PB15_FUNC_SPI2_MOSI_I2S2_SDO 0x1f06\n-#define STM32H7_PB15_FUNC_DFSDM_CKIN2 0x1f07\n-#define STM32H7_PB15_FUNC_UART4_CTS 0x1f09\n-#define STM32H7_PB15_FUNC_SDMMC2_D1 0x1f0a\n-#define STM32H7_PB15_FUNC_OTG_HS_DP 0x1f0d\n-#define STM32H7_PB15_FUNC_EVENTOUT 0x1f10\n-#define STM32H7_PB15_FUNC_ANALOG 0x1f11\n-\n-#define STM32H7_PC0_FUNC_GPIO 0x2000\n-#define STM32H7_PC0_FUNC_DFSDM_CKIN0 0x2004\n-#define STM32H7_PC0_FUNC_DFSDM_DATIN4 0x2007\n-#define STM32H7_PC0_FUNC_SAI2_FS_B 0x2009\n-#define STM32H7_PC0_FUNC_OTG_HS_ULPI_STP 0x200b\n-#define STM32H7_PC0_FUNC_FMC_SDNWE 0x200d\n-#define STM32H7_PC0_FUNC_LCD_R5 0x200f\n-#define STM32H7_PC0_FUNC_EVENTOUT 0x2010\n-#define STM32H7_PC0_FUNC_ANALOG 0x2011\n-\n-#define STM32H7_PC1_FUNC_GPIO 0x2100\n-#define STM32H7_PC1_FUNC_TRACED0 0x2101\n-#define STM32H7_PC1_FUNC_SAI1_D1 0x2103\n-#define STM32H7_PC1_FUNC_DFSDM_DATIN0 0x2104\n-#define STM32H7_PC1_FUNC_DFSDM_CKIN4 0x2105\n-#define STM32H7_PC1_FUNC_SPI2_MOSI_I2S2_SDO 0x2106\n-#define STM32H7_PC1_FUNC_SAI1_SD_A 0x2107\n-#define STM32H7_PC1_FUNC_SAI4_SD_A 0x2109\n-#define STM32H7_PC1_FUNC_SDMMC2_CK 0x210a\n-#define STM32H7_PC1_FUNC_SAI4_D1 0x210b\n-#define STM32H7_PC1_FUNC_ETH_MDC 0x210c\n-#define STM32H7_PC1_FUNC_MDIOS_MDC 0x210d\n-#define STM32H7_PC1_FUNC_EVENTOUT 0x2110\n-#define STM32H7_PC1_FUNC_ANALOG 0x2111\n-\n-#define STM32H7_PC2_FUNC_GPIO 0x2200\n-#define STM32H7_PC2_FUNC_DFSDM_CKIN1 0x2204\n-#define STM32H7_PC2_FUNC_SPI2_MISO_I2S2_SDI 0x2206\n-#define STM32H7_PC2_FUNC_DFSDM_CKOUT 0x2207\n-#define STM32H7_PC2_FUNC_OTG_HS_ULPI_DIR 0x220b\n-#define STM32H7_PC2_FUNC_ETH_MII_TXD2 0x220c\n-#define STM32H7_PC2_FUNC_FMC_SDNE0 0x220d\n-#define STM32H7_PC2_FUNC_EVENTOUT 0x2210\n-#define STM32H7_PC2_FUNC_ANALOG 0x2211\n-\n-#define STM32H7_PC3_FUNC_GPIO 0x2300\n-#define STM32H7_PC3_FUNC_DFSDM_DATIN1 0x2304\n-#define STM32H7_PC3_FUNC_SPI2_MOSI_I2S2_SDO 0x2306\n-#define STM32H7_PC3_FUNC_OTG_HS_ULPI_NXT 0x230b\n-#define STM32H7_PC3_FUNC_ETH_MII_TX_CLK 0x230c\n-#define STM32H7_PC3_FUNC_FMC_SDCKE0 0x230d\n-#define STM32H7_PC3_FUNC_EVENTOUT 0x2310\n-#define STM32H7_PC3_FUNC_ANALOG 0x2311\n-\n-#define STM32H7_PC4_FUNC_GPIO 0x2400\n-#define STM32H7_PC4_FUNC_DFSDM_CKIN2 0x2404\n-#define STM32H7_PC4_FUNC_I2S1_MCK 0x2406\n-#define STM32H7_PC4_FUNC_SPDIFRX_IN2 0x240a\n-#define STM32H7_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0 0x240c\n-#define STM32H7_PC4_FUNC_FMC_SDNE0 0x240d\n-#define STM32H7_PC4_FUNC_EVENTOUT 0x2410\n-#define STM32H7_PC4_FUNC_ANALOG 0x2411\n-\n-#define STM32H7_PC5_FUNC_GPIO 0x2500\n-#define STM32H7_PC5_FUNC_SAI1_D3 0x2503\n-#define STM32H7_PC5_FUNC_DFSDM_DATIN2 0x2504\n-#define STM32H7_PC5_FUNC_SPDIFRX_IN3 0x250a\n-#define STM32H7_PC5_FUNC_SAI4_D3 0x250b\n-#define STM32H7_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1 0x250c\n-#define STM32H7_PC5_FUNC_FMC_SDCKE0 0x250d\n-#define STM32H7_PC5_FUNC_COMP_1_OUT 0x250e\n-#define STM32H7_PC5_FUNC_EVENTOUT 0x2510\n-#define STM32H7_PC5_FUNC_ANALOG 0x2511\n-\n-#define STM32H7_PC6_FUNC_GPIO 0x2600\n-#define STM32H7_PC6_FUNC_HRTIM_CHA1 0x2602\n-#define STM32H7_PC6_FUNC_TIM3_CH1 0x2603\n-#define STM32H7_PC6_FUNC_TIM8_CH1 0x2604\n-#define STM32H7_PC6_FUNC_DFSDM_CKIN3 0x2605\n-#define STM32H7_PC6_FUNC_I2S2_MCK 0x2606\n-#define STM32H7_PC6_FUNC_USART6_TX 0x2608\n-#define STM32H7_PC6_FUNC_SDMMC1_D0DIR 0x2609\n-#define STM32H7_PC6_FUNC_FMC_NWAIT 0x260a\n-#define STM32H7_PC6_FUNC_SDMMC2_D6 0x260b\n-#define STM32H7_PC6_FUNC_SDMMC1_D6 0x260d\n-#define STM32H7_PC6_FUNC_DCMI_D0 0x260e\n-#define STM32H7_PC6_FUNC_LCD_HSYNC 0x260f\n-#define STM32H7_PC6_FUNC_EVENTOUT 0x2610\n-#define STM32H7_PC6_FUNC_ANALOG 0x2611\n-\n-#define STM32H7_PC7_FUNC_GPIO 0x2700\n-#define STM32H7_PC7_FUNC_TRGIO 0x2701\n-#define STM32H7_PC7_FUNC_HRTIM_CHA2 0x2702\n-#define STM32H7_PC7_FUNC_TIM3_CH2 0x2703\n-#define STM32H7_PC7_FUNC_TIM8_CH2 0x2704\n-#define STM32H7_PC7_FUNC_DFSDM_DATIN3 0x2705\n-#define STM32H7_PC7_FUNC_I2S3_MCK 0x2707\n-#define STM32H7_PC7_FUNC_USART6_RX 0x2708\n-#define STM32H7_PC7_FUNC_SDMMC1_D123DIR 0x2709\n-#define STM32H7_PC7_FUNC_FMC_NE1 0x270a\n-#define STM32H7_PC7_FUNC_SDMMC2_D7 0x270b\n-#define STM32H7_PC7_FUNC_SWPMI_TX 0x270c\n-#define STM32H7_PC7_FUNC_SDMMC1_D7 0x270d\n-#define STM32H7_PC7_FUNC_DCMI_D1 0x270e\n-#define STM32H7_PC7_FUNC_LCD_G6 0x270f\n-#define STM32H7_PC7_FUNC_EVENTOUT 0x2710\n-#define STM32H7_PC7_FUNC_ANALOG 0x2711\n-\n-#define STM32H7_PC8_FUNC_GPIO 0x2800\n-#define STM32H7_PC8_FUNC_TRACED1 0x2801\n-#define STM32H7_PC8_FUNC_HRTIM_CHB1 0x2802\n-#define STM32H7_PC8_FUNC_TIM3_CH3 0x2803\n-#define STM32H7_PC8_FUNC_TIM8_CH3 0x2804\n-#define STM32H7_PC8_FUNC_USART6_CK 0x2808\n-#define STM32H7_PC8_FUNC_UART5_RTS 0x2809\n-#define STM32H7_PC8_FUNC_FMC_NE2_FMC_NCE 0x280a\n-#define STM32H7_PC8_FUNC_SWPMI_RX 0x280c\n-#define STM32H7_PC8_FUNC_SDMMC1_D0 0x280d\n-#define STM32H7_PC8_FUNC_DCMI_D2 0x280e\n-#define STM32H7_PC8_FUNC_EVENTOUT 0x2810\n-#define STM32H7_PC8_FUNC_ANALOG 0x2811\n-\n-#define STM32H7_PC9_FUNC_GPIO 0x2900\n-#define STM32H7_PC9_FUNC_MCO2 0x2901\n-#define STM32H7_PC9_FUNC_TIM3_CH4 0x2903\n-#define STM32H7_PC9_FUNC_TIM8_CH4 0x2904\n-#define STM32H7_PC9_FUNC_I2C3_SDA 0x2905\n-#define STM32H7_PC9_FUNC_I2S_CKIN 0x2906\n-#define STM32H7_PC9_FUNC_UART5_CTS 0x2909\n-#define STM32H7_PC9_FUNC_QUADSPI_BK1_IO0 0x290a\n-#define STM32H7_PC9_FUNC_LCD_G3 0x290b\n-#define STM32H7_PC9_FUNC_SWPMI_SUSPEND 0x290c\n-#define STM32H7_PC9_FUNC_SDMMC1_D1 0x290d\n-#define STM32H7_PC9_FUNC_DCMI_D3 0x290e\n-#define STM32H7_PC9_FUNC_LCD_B2 0x290f\n-#define STM32H7_PC9_FUNC_EVENTOUT 0x2910\n-#define STM32H7_PC9_FUNC_ANALOG 0x2911\n-\n-#define STM32H7_PC10_FUNC_GPIO 0x2a00\n-#define STM32H7_PC10_FUNC_HRTIM_EEV1 0x2a03\n-#define STM32H7_PC10_FUNC_DFSDM_CKIN5 0x2a04\n-#define STM32H7_PC10_FUNC_SPI3_SCK_I2S3_CK 0x2a07\n-#define STM32H7_PC10_FUNC_USART3_TX 0x2a08\n-#define STM32H7_PC10_FUNC_UART4_TX 0x2a09\n-#define STM32H7_PC10_FUNC_QUADSPI_BK1_IO1 0x2a0a\n-#define STM32H7_PC10_FUNC_SDMMC1_D2 0x2a0d\n-#define STM32H7_PC10_FUNC_DCMI_D8 0x2a0e\n-#define STM32H7_PC10_FUNC_LCD_R2 0x2a0f\n-#define STM32H7_PC10_FUNC_EVENTOUT 0x2a10\n-#define STM32H7_PC10_FUNC_ANALOG 0x2a11\n-\n-#define STM32H7_PC11_FUNC_GPIO 0x2b00\n-#define STM32H7_PC11_FUNC_HRTIM_FLT2 0x2b03\n-#define STM32H7_PC11_FUNC_DFSDM_DATIN5 0x2b04\n-#define STM32H7_PC11_FUNC_SPI3_MISO_I2S3_SDI 0x2b07\n-#define STM32H7_PC11_FUNC_USART3_RX 0x2b08\n-#define STM32H7_PC11_FUNC_UART4_RX 0x2b09\n-#define STM32H7_PC11_FUNC_QUADSPI_BK2_NCS 0x2b0a\n-#define STM32H7_PC11_FUNC_SDMMC1_D3 0x2b0d\n-#define STM32H7_PC11_FUNC_DCMI_D4 0x2b0e\n-#define STM32H7_PC11_FUNC_EVENTOUT 0x2b10\n-#define STM32H7_PC11_FUNC_ANALOG 0x2b11\n-\n-#define STM32H7_PC12_FUNC_GPIO 0x2c00\n-#define STM32H7_PC12_FUNC_TRACED3 0x2c01\n-#define STM32H7_PC12_FUNC_HRTIM_EEV2 0x2c03\n-#define STM32H7_PC12_FUNC_SPI3_MOSI_I2S3_SDO 0x2c07\n-#define STM32H7_PC12_FUNC_USART3_CK 0x2c08\n-#define STM32H7_PC12_FUNC_UART5_TX 0x2c09\n-#define STM32H7_PC12_FUNC_SDMMC1_CK 0x2c0d\n-#define STM32H7_PC12_FUNC_DCMI_D9 0x2c0e\n-#define STM32H7_PC12_FUNC_EVENTOUT 0x2c10\n-#define STM32H7_PC12_FUNC_ANALOG 0x2c11\n-\n-#define STM32H7_PC13_FUNC_GPIO 0x2d00\n-#define STM32H7_PC13_FUNC_EVENTOUT 0x2d10\n-#define STM32H7_PC13_FUNC_ANALOG 0x2d11\n-\n-#define STM32H7_PC14_FUNC_GPIO 0x2e00\n-#define STM32H7_PC14_FUNC_EVENTOUT 0x2e10\n-#define STM32H7_PC14_FUNC_ANALOG 0x2e11\n-\n-#define STM32H7_PC15_FUNC_GPIO 0x2f00\n-#define STM32H7_PC15_FUNC_EVENTOUT 0x2f10\n-#define STM32H7_PC15_FUNC_ANALOG 0x2f11\n-\n-#define STM32H7_PD0_FUNC_GPIO 0x3000\n-#define STM32H7_PD0_FUNC_DFSDM_CKIN6 0x3004\n-#define STM32H7_PD0_FUNC_SAI3_SCK_A 0x3007\n-#define STM32H7_PD0_FUNC_UART4_RX 0x3009\n-#define STM32H7_PD0_FUNC_CAN1_RX 0x300a\n-#define STM32H7_PD0_FUNC_FMC_D2_FMC_DA2 0x300d\n-#define STM32H7_PD0_FUNC_EVENTOUT 0x3010\n-#define STM32H7_PD0_FUNC_ANALOG 0x3011\n-\n-#define STM32H7_PD1_FUNC_GPIO 0x3100\n-#define STM32H7_PD1_FUNC_DFSDM_DATIN6 0x3104\n-#define STM32H7_PD1_FUNC_SAI3_SD_A 0x3107\n-#define STM32H7_PD1_FUNC_UART4_TX 0x3109\n-#define STM32H7_PD1_FUNC_CAN1_TX 0x310a\n-#define STM32H7_PD1_FUNC_FMC_D3_FMC_DA3 0x310d\n-#define STM32H7_PD1_FUNC_EVENTOUT 0x3110\n-#define STM32H7_PD1_FUNC_ANALOG 0x3111\n-\n-#define STM32H7_PD2_FUNC_GPIO 0x3200\n-#define STM32H7_PD2_FUNC_TRACED2 0x3201\n-#define STM32H7_PD2_FUNC_TIM3_ETR 0x3203\n-#define STM32H7_PD2_FUNC_UART5_RX 0x3209\n-#define STM32H7_PD2_FUNC_SDMMC1_CMD 0x320d\n-#define STM32H7_PD2_FUNC_DCMI_D11 0x320e\n-#define STM32H7_PD2_FUNC_EVENTOUT 0x3210\n-#define STM32H7_PD2_FUNC_ANALOG 0x3211\n-\n-#define STM32H7_PD3_FUNC_GPIO 0x3300\n-#define STM32H7_PD3_FUNC_DFSDM_CKOUT 0x3304\n-#define STM32H7_PD3_FUNC_SPI2_SCK_I2S2_CK 0x3306\n-#define STM32H7_PD3_FUNC_USART2_CTS_NSS 0x3308\n-#define STM32H7_PD3_FUNC_FMC_CLK 0x330d\n-#define STM32H7_PD3_FUNC_DCMI_D5 0x330e\n-#define STM32H7_PD3_FUNC_LCD_G7 0x330f\n-#define STM32H7_PD3_FUNC_EVENTOUT 0x3310\n-#define STM32H7_PD3_FUNC_ANALOG 0x3311\n-\n-#define STM32H7_PD4_FUNC_GPIO 0x3400\n-#define STM32H7_PD4_FUNC_HRTIM_FLT3 0x3403\n-#define STM32H7_PD4_FUNC_SAI3_FS_A 0x3407\n-#define STM32H7_PD4_FUNC_USART2_RTS 0x3408\n-#define STM32H7_PD4_FUNC_CAN1_RXFD 0x340a\n-#define STM32H7_PD4_FUNC_FMC_NOE 0x340d\n-#define STM32H7_PD4_FUNC_EVENTOUT 0x3410\n-#define STM32H7_PD4_FUNC_ANALOG 0x3411\n-\n-#define STM32H7_PD5_FUNC_GPIO 0x3500\n-#define STM32H7_PD5_FUNC_HRTIM_EEV3 0x3503\n-#define STM32H7_PD5_FUNC_USART2_TX 0x3508\n-#define STM32H7_PD5_FUNC_CAN1_TXFD 0x350a\n-#define STM32H7_PD5_FUNC_FMC_NWE 0x350d\n-#define STM32H7_PD5_FUNC_EVENTOUT 0x3510\n-#define STM32H7_PD5_FUNC_ANALOG 0x3511\n-\n-#define STM32H7_PD6_FUNC_GPIO 0x3600\n-#define STM32H7_PD6_FUNC_SAI1_D1 0x3603\n-#define STM32H7_PD6_FUNC_DFSDM_CKIN4 0x3604\n-#define STM32H7_PD6_FUNC_DFSDM_DATIN1 0x3605\n-#define STM32H7_PD6_FUNC_SPI3_MOSI_I2S3_SDO 0x3606\n-#define STM32H7_PD6_FUNC_SAI1_SD_A 0x3607\n-#define STM32H7_PD6_FUNC_USART2_RX 0x3608\n-#define STM32H7_PD6_FUNC_SAI4_SD_A 0x3609\n-#define STM32H7_PD6_FUNC_CAN2_RXFD 0x360a\n-#define STM32H7_PD6_FUNC_SAI4_D1 0x360b\n-#define STM32H7_PD6_FUNC_SDMMC2_CK 0x360c\n-#define STM32H7_PD6_FUNC_FMC_NWAIT 0x360d\n-#define STM32H7_PD6_FUNC_DCMI_D10 0x360e\n-#define STM32H7_PD6_FUNC_LCD_B2 0x360f\n-#define STM32H7_PD6_FUNC_EVENTOUT 0x3610\n-#define STM32H7_PD6_FUNC_ANALOG 0x3611\n-\n-#define STM32H7_PD7_FUNC_GPIO 0x3700\n-#define STM32H7_PD7_FUNC_DFSDM_DATIN4 0x3704\n-#define STM32H7_PD7_FUNC_SPI1_MOSI_I2S1_SDO 0x3706\n-#define STM32H7_PD7_FUNC_DFSDM_CKIN1 0x3707\n-#define STM32H7_PD7_FUNC_USART2_CK 0x3708\n-#define STM32H7_PD7_FUNC_SPDIFRX_IN0 0x370a\n-#define STM32H7_PD7_FUNC_SDMMC2_CMD 0x370c\n-#define STM32H7_PD7_FUNC_FMC_NE1 0x370d\n-#define STM32H7_PD7_FUNC_EVENTOUT 0x3710\n-#define STM32H7_PD7_FUNC_ANALOG 0x3711\n-\n-#define STM32H7_PD8_FUNC_GPIO 0x3800\n-#define STM32H7_PD8_FUNC_DFSDM_CKIN3 0x3804\n-#define STM32H7_PD8_FUNC_SAI3_SCK_B 0x3807\n-#define STM32H7_PD8_FUNC_USART3_TX 0x3808\n-#define STM32H7_PD8_FUNC_SPDIFRX_IN1 0x380a\n-#define STM32H7_PD8_FUNC_FMC_D13_FMC_DA13 0x380d\n-#define STM32H7_PD8_FUNC_EVENTOUT 0x3810\n-#define STM32H7_PD8_FUNC_ANALOG 0x3811\n-\n-#define STM32H7_PD9_FUNC_GPIO 0x3900\n-#define STM32H7_PD9_FUNC_DFSDM_DATIN3 0x3904\n-#define STM32H7_PD9_FUNC_SAI3_SD_B 0x3907\n-#define STM32H7_PD9_FUNC_USART3_RX 0x3908\n-#define STM32H7_PD9_FUNC_CAN2_RXFD 0x390a\n-#define STM32H7_PD9_FUNC_FMC_D14_FMC_DA14 0x390d\n-#define STM32H7_PD9_FUNC_EVENTOUT 0x3910\n-#define STM32H7_PD9_FUNC_ANALOG 0x3911\n-\n-#define STM32H7_PD10_FUNC_GPIO 0x3a00\n-#define STM32H7_PD10_FUNC_DFSDM_CKOUT 0x3a04\n-#define STM32H7_PD10_FUNC_SAI3_FS_B 0x3a07\n-#define STM32H7_PD10_FUNC_USART3_CK 0x3a08\n-#define STM32H7_PD10_FUNC_CAN2_TXFD 0x3a0a\n-#define STM32H7_PD10_FUNC_FMC_D15_FMC_DA15 0x3a0d\n-#define STM32H7_PD10_FUNC_LCD_B3 0x3a0f\n-#define STM32H7_PD10_FUNC_EVENTOUT 0x3a10\n-#define STM32H7_PD10_FUNC_ANALOG 0x3a11\n-\n-#define STM32H7_PD11_FUNC_GPIO 0x3b00\n-#define STM32H7_PD11_FUNC_LPTIM2_IN2 0x3b04\n-#define STM32H7_PD11_FUNC_I2C4_SMBA 0x3b05\n-#define STM32H7_PD11_FUNC_USART3_CTS_NSS 0x3b08\n-#define STM32H7_PD11_FUNC_QUADSPI_BK1_IO0 0x3b0a\n-#define STM32H7_PD11_FUNC_SAI2_SD_A 0x3b0b\n-#define STM32H7_PD11_FUNC_FMC_A16 0x3b0d\n-#define STM32H7_PD11_FUNC_EVENTOUT 0x3b10\n-#define STM32H7_PD11_FUNC_ANALOG 0x3b11\n-\n-#define STM32H7_PD12_FUNC_GPIO 0x3c00\n-#define STM32H7_PD12_FUNC_LPTIM1_IN1 0x3c02\n-#define STM32H7_PD12_FUNC_TIM4_CH1 0x3c03\n-#define STM32H7_PD12_FUNC_LPTIM2_IN1 0x3c04\n-#define STM32H7_PD12_FUNC_I2C4_SCL 0x3c05\n-#define STM32H7_PD12_FUNC_USART3_RTS 0x3c08\n-#define STM32H7_PD12_FUNC_QUADSPI_BK1_IO1 0x3c0a\n-#define STM32H7_PD12_FUNC_SAI2_FS_A 0x3c0b\n-#define STM32H7_PD12_FUNC_FMC_A17 0x3c0d\n-#define STM32H7_PD12_FUNC_EVENTOUT 0x3c10\n-#define STM32H7_PD12_FUNC_ANALOG 0x3c11\n-\n-#define STM32H7_PD13_FUNC_GPIO 0x3d00\n-#define STM32H7_PD13_FUNC_LPTIM1_OUT 0x3d02\n-#define STM32H7_PD13_FUNC_TIM4_CH2 0x3d03\n-#define STM32H7_PD13_FUNC_I2C4_SDA 0x3d05\n-#define STM32H7_PD13_FUNC_QUADSPI_BK1_IO3 0x3d0a\n-#define STM32H7_PD13_FUNC_SAI2_SCK_A 0x3d0b\n-#define STM32H7_PD13_FUNC_FMC_A18 0x3d0d\n-#define STM32H7_PD13_FUNC_EVENTOUT 0x3d10\n-#define STM32H7_PD13_FUNC_ANALOG 0x3d11\n-\n-#define STM32H7_PD14_FUNC_GPIO 0x3e00\n-#define STM32H7_PD14_FUNC_TIM4_CH3 0x3e03\n-#define STM32H7_PD14_FUNC_SAI3_MCLK_B 0x3e07\n-#define STM32H7_PD14_FUNC_UART8_CTS 0x3e09\n-#define STM32H7_PD14_FUNC_FMC_D0_FMC_DA0 0x3e0d\n-#define STM32H7_PD14_FUNC_EVENTOUT 0x3e10\n-#define STM32H7_PD14_FUNC_ANALOG 0x3e11\n-\n-#define STM32H7_PD15_FUNC_GPIO 0x3f00\n-#define STM32H7_PD15_FUNC_TIM4_CH4 0x3f03\n-#define STM32H7_PD15_FUNC_SAI3_MCLK_A 0x3f07\n-#define STM32H7_PD15_FUNC_UART8_RTS 0x3f09\n-#define STM32H7_PD15_FUNC_FMC_D1_FMC_DA1 0x3f0d\n-#define STM32H7_PD15_FUNC_EVENTOUT 0x3f10\n-#define STM32H7_PD15_FUNC_ANALOG 0x3f11\n-\n-#define STM32H7_PE0_FUNC_GPIO 0x4000\n-#define STM32H7_PE0_FUNC_LPTIM1_ETR 0x4002\n-#define STM32H7_PE0_FUNC_TIM4_ETR 0x4003\n-#define STM32H7_PE0_FUNC_HRTIM_SCIN 0x4004\n-#define STM32H7_PE0_FUNC_LPTIM2_ETR 0x4005\n-#define STM32H7_PE0_FUNC_UART8_RX 0x4009\n-#define STM32H7_PE0_FUNC_CAN1_RXFD 0x400a\n-#define STM32H7_PE0_FUNC_SAI2_MCK_A 0x400b\n-#define STM32H7_PE0_FUNC_FMC_NBL0 0x400d\n-#define STM32H7_PE0_FUNC_DCMI_D2 0x400e\n-#define STM32H7_PE0_FUNC_EVENTOUT 0x4010\n-#define STM32H7_PE0_FUNC_ANALOG 0x4011\n-\n-#define STM32H7_PE1_FUNC_GPIO 0x4100\n-#define STM32H7_PE1_FUNC_LPTIM1_IN2 0x4102\n-#define STM32H7_PE1_FUNC_HRTIM_SCOUT 0x4104\n-#define STM32H7_PE1_FUNC_UART8_TX 0x4109\n-#define STM32H7_PE1_FUNC_CAN1_TXFD 0x410a\n-#define STM32H7_PE1_FUNC_FMC_NBL1 0x410d\n-#define STM32H7_PE1_FUNC_DCMI_D3 0x410e\n-#define STM32H7_PE1_FUNC_EVENTOUT 0x4110\n-#define STM32H7_PE1_FUNC_ANALOG 0x4111\n-\n-#define STM32H7_PE2_FUNC_GPIO 0x4200\n-#define STM32H7_PE2_FUNC_TRACECLK 0x4201\n-#define STM32H7_PE2_FUNC_SAI1_CK1 0x4203\n-#define STM32H7_PE2_FUNC_SPI4_SCK 0x4206\n-#define STM32H7_PE2_FUNC_SAI1_MCLK_A 0x4207\n-#define STM32H7_PE2_FUNC_SAI4_MCLK_A 0x4209\n-#define STM32H7_PE2_FUNC_QUADSPI_BK1_IO2 0x420a\n-#define STM32H7_PE2_FUNC_SAI4_CK1 0x420b\n-#define STM32H7_PE2_FUNC_ETH_MII_TXD3 0x420c\n-#define STM32H7_PE2_FUNC_FMC_A23 0x420d\n-#define STM32H7_PE2_FUNC_EVENTOUT 0x4210\n-#define STM32H7_PE2_FUNC_ANALOG 0x4211\n-\n-#define STM32H7_PE3_FUNC_GPIO 0x4300\n-#define STM32H7_PE3_FUNC_TRACED0 0x4301\n-#define STM32H7_PE3_FUNC_TIM15_BKIN 0x4305\n-#define STM32H7_PE3_FUNC_SAI1_SD_B 0x4307\n-#define STM32H7_PE3_FUNC_SAI4_SD_B 0x4309\n-#define STM32H7_PE3_FUNC_FMC_A19 0x430d\n-#define STM32H7_PE3_FUNC_EVENTOUT 0x4310\n-#define STM32H7_PE3_FUNC_ANALOG 0x4311\n-\n-#define STM32H7_PE4_FUNC_GPIO 0x4400\n-#define STM32H7_PE4_FUNC_TRACED1 0x4401\n-#define STM32H7_PE4_FUNC_SAI1_D2 0x4403\n-#define STM32H7_PE4_FUNC_DFSDM_DATIN3 0x4404\n-#define STM32H7_PE4_FUNC_TIM15_CH1N 0x4405\n-#define STM32H7_PE4_FUNC_SPI4_NSS 0x4406\n-#define STM32H7_PE4_FUNC_SAI1_FS_A 0x4407\n-#define STM32H7_PE4_FUNC_SAI4_FS_A 0x4409\n-#define STM32H7_PE4_FUNC_SAI4_D2 0x440b\n-#define STM32H7_PE4_FUNC_FMC_A20 0x440d\n-#define STM32H7_PE4_FUNC_DCMI_D4 0x440e\n-#define STM32H7_PE4_FUNC_LCD_B0 0x440f\n-#define STM32H7_PE4_FUNC_EVENTOUT 0x4410\n-#define STM32H7_PE4_FUNC_ANALOG 0x4411\n-\n-#define STM32H7_PE5_FUNC_GPIO 0x4500\n-#define STM32H7_PE5_FUNC_TRACED2 0x4501\n-#define STM32H7_PE5_FUNC_SAI1_CK2 0x4503\n-#define STM32H7_PE5_FUNC_DFSDM_CKIN3 0x4504\n-#define STM32H7_PE5_FUNC_TIM15_CH1 0x4505\n-#define STM32H7_PE5_FUNC_SPI4_MISO 0x4506\n-#define STM32H7_PE5_FUNC_SAI1_SCK_A 0x4507\n-#define STM32H7_PE5_FUNC_SAI4_SCK_A 0x4509\n-#define STM32H7_PE5_FUNC_SAI4_CK2 0x450b\n-#define STM32H7_PE5_FUNC_FMC_A21 0x450d\n-#define STM32H7_PE5_FUNC_DCMI_D6 0x450e\n-#define STM32H7_PE5_FUNC_LCD_G0 0x450f\n-#define STM32H7_PE5_FUNC_EVENTOUT 0x4510\n-#define STM32H7_PE5_FUNC_ANALOG 0x4511\n-\n-#define STM32H7_PE6_FUNC_GPIO 0x4600\n-#define STM32H7_PE6_FUNC_TRACED3 0x4601\n-#define STM32H7_PE6_FUNC_TIM1_BKIN2 0x4602\n-#define STM32H7_PE6_FUNC_SAI1_D1 0x4603\n-#define STM32H7_PE6_FUNC_TIM15_CH2 0x4605\n-#define STM32H7_PE6_FUNC_SPI4_MOSI 0x4606\n-#define STM32H7_PE6_FUNC_SAI1_SD_A 0x4607\n-#define STM32H7_PE6_FUNC_SAI4_SD_A 0x4609\n-#define STM32H7_PE6_FUNC_SAI4_D1 0x460a\n-#define STM32H7_PE6_FUNC_SAI2_MCK_B 0x460b\n-#define STM32H7_PE6_FUNC_TIM1_BKIN2_COMP12 0x460c\n-#define STM32H7_PE6_FUNC_FMC_A22 0x460d\n-#define STM32H7_PE6_FUNC_DCMI_D7 0x460e\n-#define STM32H7_PE6_FUNC_LCD_G1 0x460f\n-#define STM32H7_PE6_FUNC_EVENTOUT 0x4610\n-#define STM32H7_PE6_FUNC_ANALOG 0x4611\n-\n-#define STM32H7_PE7_FUNC_GPIO 0x4700\n-#define STM32H7_PE7_FUNC_TIM1_ETR 0x4702\n-#define STM32H7_PE7_FUNC_DFSDM_DATIN2 0x4704\n-#define STM32H7_PE7_FUNC_UART7_RX 0x4708\n-#define STM32H7_PE7_FUNC_QUADSPI_BK2_IO0 0x470b\n-#define STM32H7_PE7_FUNC_FMC_D4_FMC_DA4 0x470d\n-#define STM32H7_PE7_FUNC_EVENTOUT 0x4710\n-#define STM32H7_PE7_FUNC_ANALOG 0x4711\n-\n-#define STM32H7_PE8_FUNC_GPIO 0x4800\n-#define STM32H7_PE8_FUNC_TIM1_CH1N 0x4802\n-#define STM32H7_PE8_FUNC_DFSDM_CKIN2 0x4804\n-#define STM32H7_PE8_FUNC_UART7_TX 0x4808\n-#define STM32H7_PE8_FUNC_QUADSPI_BK2_IO1 0x480b\n-#define STM32H7_PE8_FUNC_FMC_D5_FMC_DA5 0x480d\n-#define STM32H7_PE8_FUNC_COMP_2_OUT 0x480e\n-#define STM32H7_PE8_FUNC_EVENTOUT 0x4810\n-#define STM32H7_PE8_FUNC_ANALOG 0x4811\n-\n-#define STM32H7_PE9_FUNC_GPIO 0x4900\n-#define STM32H7_PE9_FUNC_TIM1_CH1 0x4902\n-#define STM32H7_PE9_FUNC_DFSDM_CKOUT 0x4904\n-#define STM32H7_PE9_FUNC_UART7_RTS 0x4908\n-#define STM32H7_PE9_FUNC_QUADSPI_BK2_IO2 0x490b\n-#define STM32H7_PE9_FUNC_FMC_D6_FMC_DA6 0x490d\n-#define STM32H7_PE9_FUNC_EVENTOUT 0x4910\n-#define STM32H7_PE9_FUNC_ANALOG 0x4911\n-\n-#define STM32H7_PE10_FUNC_GPIO 0x4a00\n-#define STM32H7_PE10_FUNC_TIM1_CH2N 0x4a02\n-#define STM32H7_PE10_FUNC_DFSDM_DATIN4 0x4a04\n-#define STM32H7_PE10_FUNC_UART7_CTS 0x4a08\n-#define STM32H7_PE10_FUNC_QUADSPI_BK2_IO3 0x4a0b\n-#define STM32H7_PE10_FUNC_FMC_D7_FMC_DA7 0x4a0d\n-#define STM32H7_PE10_FUNC_EVENTOUT 0x4a10\n-#define STM32H7_PE10_FUNC_ANALOG 0x4a11\n-\n-#define STM32H7_PE11_FUNC_GPIO 0x4b00\n-#define STM32H7_PE11_FUNC_TIM1_CH2 0x4b02\n-#define STM32H7_PE11_FUNC_DFSDM_CKIN4 0x4b04\n-#define STM32H7_PE11_FUNC_SPI4_NSS 0x4b06\n-#define STM32H7_PE11_FUNC_SAI2_SD_B 0x4b0b\n-#define STM32H7_PE11_FUNC_FMC_D8_FMC_DA8 0x4b0d\n-#define STM32H7_PE11_FUNC_LCD_G3 0x4b0f\n-#define STM32H7_PE11_FUNC_EVENTOUT 0x4b10\n-#define STM32H7_PE11_FUNC_ANALOG 0x4b11\n-\n-#define STM32H7_PE12_FUNC_GPIO 0x4c00\n-#define STM32H7_PE12_FUNC_TIM1_CH3N 0x4c02\n-#define STM32H7_PE12_FUNC_DFSDM_DATIN5 0x4c04\n-#define STM32H7_PE12_FUNC_SPI4_SCK 0x4c06\n-#define STM32H7_PE12_FUNC_SAI2_SCK_B 0x4c0b\n-#define STM32H7_PE12_FUNC_FMC_D9_FMC_DA9 0x4c0d\n-#define STM32H7_PE12_FUNC_COMP_1_OUT 0x4c0e\n-#define STM32H7_PE12_FUNC_LCD_B4 0x4c0f\n-#define STM32H7_PE12_FUNC_EVENTOUT 0x4c10\n-#define STM32H7_PE12_FUNC_ANALOG 0x4c11\n-\n-#define STM32H7_PE13_FUNC_GPIO 0x4d00\n-#define STM32H7_PE13_FUNC_TIM1_CH3 0x4d02\n-#define STM32H7_PE13_FUNC_DFSDM_CKIN5 0x4d04\n-#define STM32H7_PE13_FUNC_SPI4_MISO 0x4d06\n-#define STM32H7_PE13_FUNC_SAI2_FS_B 0x4d0b\n-#define STM32H7_PE13_FUNC_FMC_D10_FMC_DA10 0x4d0d\n-#define STM32H7_PE13_FUNC_COMP_2_OUT 0x4d0e\n-#define STM32H7_PE13_FUNC_LCD_DE 0x4d0f\n-#define STM32H7_PE13_FUNC_EVENTOUT 0x4d10\n-#define STM32H7_PE13_FUNC_ANALOG 0x4d11\n-\n-#define STM32H7_PE14_FUNC_GPIO 0x4e00\n-#define STM32H7_PE14_FUNC_TIM1_CH4 0x4e02\n-#define STM32H7_PE14_FUNC_SPI4_MOSI 0x4e06\n-#define STM32H7_PE14_FUNC_SAI2_MCK_B 0x4e0b\n-#define STM32H7_PE14_FUNC_FMC_D11_FMC_DA11 0x4e0d\n-#define STM32H7_PE14_FUNC_LCD_CLK 0x4e0f\n-#define STM32H7_PE14_FUNC_EVENTOUT 0x4e10\n-#define STM32H7_PE14_FUNC_ANALOG 0x4e11\n-\n-#define STM32H7_PE15_FUNC_GPIO 0x4f00\n-#define STM32H7_PE15_FUNC_TIM1_BKIN 0x4f02\n-#define STM32H7_PE15_FUNC_HDMI__TIM1_BKIN 0x4f06\n-#define STM32H7_PE15_FUNC_FMC_D12_FMC_DA12 0x4f0d\n-#define STM32H7_PE15_FUNC_TIM1_BKIN_COMP12 0x4f0e\n-#define STM32H7_PE15_FUNC_LCD_R7 0x4f0f\n-#define STM32H7_PE15_FUNC_EVENTOUT 0x4f10\n-#define STM32H7_PE15_FUNC_ANALOG 0x4f11\n-\n-#define STM32H7_PF0_FUNC_GPIO 0x5000\n-#define STM32H7_PF0_FUNC_I2C2_SDA 0x5005\n-#define STM32H7_PF0_FUNC_FMC_A0 0x500d\n-#define STM32H7_PF0_FUNC_EVENTOUT 0x5010\n-#define STM32H7_PF0_FUNC_ANALOG 0x5011\n-\n-#define STM32H7_PF1_FUNC_GPIO 0x5100\n-#define STM32H7_PF1_FUNC_I2C2_SCL 0x5105\n-#define STM32H7_PF1_FUNC_FMC_A1 0x510d\n-#define STM32H7_PF1_FUNC_EVENTOUT 0x5110\n-#define STM32H7_PF1_FUNC_ANALOG 0x5111\n-\n-#define STM32H7_PF2_FUNC_GPIO 0x5200\n-#define STM32H7_PF2_FUNC_I2C2_SMBA 0x5205\n-#define STM32H7_PF2_FUNC_FMC_A2 0x520d\n-#define STM32H7_PF2_FUNC_EVENTOUT 0x5210\n-#define STM32H7_PF2_FUNC_ANALOG 0x5211\n-\n-#define STM32H7_PF3_FUNC_GPIO 0x5300\n-#define STM32H7_PF3_FUNC_FMC_A3 0x530d\n-#define STM32H7_PF3_FUNC_EVENTOUT 0x5310\n-#define STM32H7_PF3_FUNC_ANALOG 0x5311\n-\n-#define STM32H7_PF4_FUNC_GPIO 0x5400\n-#define STM32H7_PF4_FUNC_FMC_A4 0x540d\n-#define STM32H7_PF4_FUNC_EVENTOUT 0x5410\n-#define STM32H7_PF4_FUNC_ANALOG 0x5411\n-\n-#define STM32H7_PF5_FUNC_GPIO 0x5500\n-#define STM32H7_PF5_FUNC_FMC_A5 0x550d\n-#define STM32H7_PF5_FUNC_EVENTOUT 0x5510\n-#define STM32H7_PF5_FUNC_ANALOG 0x5511\n-\n-#define STM32H7_PF6_FUNC_GPIO 0x5600\n-#define STM32H7_PF6_FUNC_TIM16_CH1 0x5602\n-#define STM32H7_PF6_FUNC_SPI5_NSS 0x5606\n-#define STM32H7_PF6_FUNC_SAI1_SD_B 0x5607\n-#define STM32H7_PF6_FUNC_UART7_RX 0x5608\n-#define STM32H7_PF6_FUNC_SAI4_SD_B 0x5609\n-#define STM32H7_PF6_FUNC_QUADSPI_BK1_IO3 0x560a\n-#define STM32H7_PF6_FUNC_EVENTOUT 0x5610\n-#define STM32H7_PF6_FUNC_ANALOG 0x5611\n-\n-#define STM32H7_PF7_FUNC_GPIO 0x5700\n-#define STM32H7_PF7_FUNC_TIM17_CH1 0x5702\n-#define STM32H7_PF7_FUNC_SPI5_SCK 0x5706\n-#define STM32H7_PF7_FUNC_SAI1_MCLK_B 0x5707\n-#define STM32H7_PF7_FUNC_UART7_TX 0x5708\n-#define STM32H7_PF7_FUNC_SAI4_MCLK_B 0x5709\n-#define STM32H7_PF7_FUNC_QUADSPI_BK1_IO2 0x570a\n-#define STM32H7_PF7_FUNC_EVENTOUT 0x5710\n-#define STM32H7_PF7_FUNC_ANALOG 0x5711\n-\n-#define STM32H7_PF8_FUNC_GPIO 0x5800\n-#define STM32H7_PF8_FUNC_TIM16_CH1N 0x5802\n-#define STM32H7_PF8_FUNC_SPI5_MISO 0x5806\n-#define STM32H7_PF8_FUNC_SAI1_SCK_B 0x5807\n-#define STM32H7_PF8_FUNC_UART7_RTS 0x5808\n-#define STM32H7_PF8_FUNC_SAI4_SCK_B 0x5809\n-#define STM32H7_PF8_FUNC_TIM13_CH1 0x580a\n-#define STM32H7_PF8_FUNC_QUADSPI_BK1_IO0 0x580b\n-#define STM32H7_PF8_FUNC_EVENTOUT 0x5810\n-#define STM32H7_PF8_FUNC_ANALOG 0x5811\n-\n-#define STM32H7_PF9_FUNC_GPIO 0x5900\n-#define STM32H7_PF9_FUNC_TIM17_CH1N 0x5902\n-#define STM32H7_PF9_FUNC_SPI5_MOSI 0x5906\n-#define STM32H7_PF9_FUNC_SAI1_FS_B 0x5907\n-#define STM32H7_PF9_FUNC_UART7_CTS 0x5908\n-#define STM32H7_PF9_FUNC_SAI4_FS_B 0x5909\n-#define STM32H7_PF9_FUNC_TIM14_CH1 0x590a\n-#define STM32H7_PF9_FUNC_QUADSPI_BK1_IO1 0x590b\n-#define STM32H7_PF9_FUNC_EVENTOUT 0x5910\n-#define STM32H7_PF9_FUNC_ANALOG 0x5911\n-\n-#define STM32H7_PF10_FUNC_GPIO 0x5a00\n-#define STM32H7_PF10_FUNC_TIM16_BKIN 0x5a02\n-#define STM32H7_PF10_FUNC_SAI1_D3 0x5a03\n-#define STM32H7_PF10_FUNC_QUADSPI_CLK 0x5a0a\n-#define STM32H7_PF10_FUNC_SAI4_D3 0x5a0b\n-#define STM32H7_PF10_FUNC_DCMI_D11 0x5a0e\n-#define STM32H7_PF10_FUNC_LCD_DE 0x5a0f\n-#define STM32H7_PF10_FUNC_EVENTOUT 0x5a10\n-#define STM32H7_PF10_FUNC_ANALOG 0x5a11\n-\n-#define STM32H7_PF11_FUNC_GPIO 0x5b00\n-#define STM32H7_PF11_FUNC_SPI5_MOSI 0x5b06\n-#define STM32H7_PF11_FUNC_SAI2_SD_B 0x5b0b\n-#define STM32H7_PF11_FUNC_FMC_SDNRAS 0x5b0d\n-#define STM32H7_PF11_FUNC_DCMI_D12 0x5b0e\n-#define STM32H7_PF11_FUNC_EVENTOUT 0x5b10\n-#define STM32H7_PF11_FUNC_ANALOG 0x5b11\n-\n-#define STM32H7_PF12_FUNC_GPIO 0x5c00\n-#define STM32H7_PF12_FUNC_FMC_A6 0x5c0d\n-#define STM32H7_PF12_FUNC_EVENTOUT 0x5c10\n-#define STM32H7_PF12_FUNC_ANALOG 0x5c11\n-\n-#define STM32H7_PF13_FUNC_GPIO 0x5d00\n-#define STM32H7_PF13_FUNC_DFSDM_DATIN6 0x5d04\n-#define STM32H7_PF13_FUNC_I2C4_SMBA 0x5d05\n-#define STM32H7_PF13_FUNC_FMC_A7 0x5d0d\n-#define STM32H7_PF13_FUNC_EVENTOUT 0x5d10\n-#define STM32H7_PF13_FUNC_ANALOG 0x5d11\n-\n-#define STM32H7_PF14_FUNC_GPIO 0x5e00\n-#define STM32H7_PF14_FUNC_DFSDM_CKIN6 0x5e04\n-#define STM32H7_PF14_FUNC_I2C4_SCL 0x5e05\n-#define STM32H7_PF14_FUNC_FMC_A8 0x5e0d\n-#define STM32H7_PF14_FUNC_EVENTOUT 0x5e10\n-#define STM32H7_PF14_FUNC_ANALOG 0x5e11\n-\n-#define STM32H7_PF15_FUNC_GPIO 0x5f00\n-#define STM32H7_PF15_FUNC_I2C4_SDA 0x5f05\n-#define STM32H7_PF15_FUNC_FMC_A9 0x5f0d\n-#define STM32H7_PF15_FUNC_EVENTOUT 0x5f10\n-#define STM32H7_PF15_FUNC_ANALOG 0x5f11\n-\n-#define STM32H7_PG0_FUNC_GPIO 0x6000\n-#define STM32H7_PG0_FUNC_FMC_A10 0x600d\n-#define STM32H7_PG0_FUNC_EVENTOUT 0x6010\n-#define STM32H7_PG0_FUNC_ANALOG 0x6011\n-\n-#define STM32H7_PG1_FUNC_GPIO 0x6100\n-#define STM32H7_PG1_FUNC_FMC_A11 0x610d\n-#define STM32H7_PG1_FUNC_EVENTOUT 0x6110\n-#define STM32H7_PG1_FUNC_ANALOG 0x6111\n-\n-#define STM32H7_PG2_FUNC_GPIO 0x6200\n-#define STM32H7_PG2_FUNC_TIM8_BKIN 0x6204\n-#define STM32H7_PG2_FUNC_TIM8_BKIN_COMP12 0x620c\n-#define STM32H7_PG2_FUNC_FMC_A12 0x620d\n-#define STM32H7_PG2_FUNC_EVENTOUT 0x6210\n-#define STM32H7_PG2_FUNC_ANALOG 0x6211\n-\n-#define STM32H7_PG3_FUNC_GPIO 0x6300\n-#define STM32H7_PG3_FUNC_TIM8_BKIN2 0x6304\n-#define STM32H7_PG3_FUNC_TIM8_BKIN2_COMP12 0x630c\n-#define STM32H7_PG3_FUNC_FMC_A13 0x630d\n-#define STM32H7_PG3_FUNC_EVENTOUT 0x6310\n-#define STM32H7_PG3_FUNC_ANALOG 0x6311\n-\n-#define STM32H7_PG4_FUNC_GPIO 0x6400\n-#define STM32H7_PG4_FUNC_TIM1_BKIN2 0x6402\n-#define STM32H7_PG4_FUNC_TIM1_BKIN2_COMP12 0x640c\n-#define STM32H7_PG4_FUNC_FMC_A14_FMC_BA0 0x640d\n-#define STM32H7_PG4_FUNC_EVENTOUT 0x6410\n-#define STM32H7_PG4_FUNC_ANALOG 0x6411\n-\n-#define STM32H7_PG5_FUNC_GPIO 0x6500\n-#define STM32H7_PG5_FUNC_TIM1_ETR 0x6502\n-#define STM32H7_PG5_FUNC_FMC_A15_FMC_BA1 0x650d\n-#define STM32H7_PG5_FUNC_EVENTOUT 0x6510\n-#define STM32H7_PG5_FUNC_ANALOG 0x6511\n-\n-#define STM32H7_PG6_FUNC_GPIO 0x6600\n-#define STM32H7_PG6_FUNC_TIM17_BKIN 0x6602\n-#define STM32H7_PG6_FUNC_HRTIM_CHE1 0x6603\n-#define STM32H7_PG6_FUNC_QUADSPI_BK1_NCS 0x660b\n-#define STM32H7_PG6_FUNC_FMC_NE3 0x660d\n-#define STM32H7_PG6_FUNC_DCMI_D12 0x660e\n-#define STM32H7_PG6_FUNC_LCD_R7 0x660f\n-#define STM32H7_PG6_FUNC_EVENTOUT 0x6610\n-#define STM32H7_PG6_FUNC_ANALOG 0x6611\n-\n-#define STM32H7_PG7_FUNC_GPIO 0x6700\n-#define STM32H7_PG7_FUNC_HRTIM_CHE2 0x6703\n-#define STM32H7_PG7_FUNC_SAI1_MCLK_A 0x6707\n-#define STM32H7_PG7_FUNC_USART6_CK 0x6708\n-#define STM32H7_PG7_FUNC_FMC_INT 0x670d\n-#define STM32H7_PG7_FUNC_DCMI_D13 0x670e\n-#define STM32H7_PG7_FUNC_LCD_CLK 0x670f\n-#define STM32H7_PG7_FUNC_EVENTOUT 0x6710\n-#define STM32H7_PG7_FUNC_ANALOG 0x6711\n-\n-#define STM32H7_PG8_FUNC_GPIO 0x6800\n-#define STM32H7_PG8_FUNC_TIM8_ETR 0x6804\n-#define STM32H7_PG8_FUNC_SPI6_NSS 0x6806\n-#define STM32H7_PG8_FUNC_USART6_RTS 0x6808\n-#define STM32H7_PG8_FUNC_SPDIFRX_IN2 0x6809\n-#define STM32H7_PG8_FUNC_ETH_PPS_OUT 0x680c\n-#define STM32H7_PG8_FUNC_FMC_SDCLK 0x680d\n-#define STM32H7_PG8_FUNC_LCD_G7 0x680f\n-#define STM32H7_PG8_FUNC_EVENTOUT 0x6810\n-#define STM32H7_PG8_FUNC_ANALOG 0x6811\n-\n-#define STM32H7_PG9_FUNC_GPIO 0x6900\n-#define STM32H7_PG9_FUNC_SPI1_MISO_I2S1_SDI 0x6906\n-#define STM32H7_PG9_FUNC_USART6_RX 0x6908\n-#define STM32H7_PG9_FUNC_SPDIFRX_IN3 0x6909\n-#define STM32H7_PG9_FUNC_QUADSPI_BK2_IO2 0x690a\n-#define STM32H7_PG9_FUNC_SAI2_FS_B 0x690b\n-#define STM32H7_PG9_FUNC_FMC_NE2_FMC_NCE 0x690d\n-#define STM32H7_PG9_FUNC_DCMI_VSYNC 0x690e\n-#define STM32H7_PG9_FUNC_EVENTOUT 0x6910\n-#define STM32H7_PG9_FUNC_ANALOG 0x6911\n-\n-#define STM32H7_PG10_FUNC_GPIO 0x6a00\n-#define STM32H7_PG10_FUNC_HRTIM_FLT5 0x6a03\n-#define STM32H7_PG10_FUNC_SPI1_NSS_I2S1_WS 0x6a06\n-#define STM32H7_PG10_FUNC_LCD_G3 0x6a0a\n-#define STM32H7_PG10_FUNC_SAI2_SD_B 0x6a0b\n-#define STM32H7_PG10_FUNC_FMC_NE3 0x6a0d\n-#define STM32H7_PG10_FUNC_DCMI_D2 0x6a0e\n-#define STM32H7_PG10_FUNC_LCD_B2 0x6a0f\n-#define STM32H7_PG10_FUNC_EVENTOUT 0x6a10\n-#define STM32H7_PG10_FUNC_ANALOG 0x6a11\n-\n-#define STM32H7_PG11_FUNC_GPIO 0x6b00\n-#define STM32H7_PG11_FUNC_HRTIM_EEV4 0x6b03\n-#define STM32H7_PG11_FUNC_SPI1_SCK_I2S1_CK 0x6b06\n-#define STM32H7_PG11_FUNC_SPDIFRX_IN0 0x6b09\n-#define STM32H7_PG11_FUNC_SDMMC2_D2 0x6b0b\n-#define STM32H7_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN 0x6b0c\n-#define STM32H7_PG11_FUNC_DCMI_D3 0x6b0e\n-#define STM32H7_PG11_FUNC_LCD_B3 0x6b0f\n-#define STM32H7_PG11_FUNC_EVENTOUT 0x6b10\n-#define STM32H7_PG11_FUNC_ANALOG 0x6b11\n-\n-#define STM32H7_PG12_FUNC_GPIO 0x6c00\n-#define STM32H7_PG12_FUNC_LPTIM1_IN1 0x6c02\n-#define STM32H7_PG12_FUNC_HRTIM_EEV5 0x6c03\n-#define STM32H7_PG12_FUNC_SPI6_MISO 0x6c06\n-#define STM32H7_PG12_FUNC_USART6_RTS 0x6c08\n-#define STM32H7_PG12_FUNC_SPDIFRX_IN1 0x6c09\n-#define STM32H7_PG12_FUNC_LCD_B4 0x6c0a\n-#define STM32H7_PG12_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6c0c\n-#define STM32H7_PG12_FUNC_FMC_NE4 0x6c0d\n-#define STM32H7_PG12_FUNC_LCD_B1 0x6c0f\n-#define STM32H7_PG12_FUNC_EVENTOUT 0x6c10\n-#define STM32H7_PG12_FUNC_ANALOG 0x6c11\n-\n-#define STM32H7_PG13_FUNC_GPIO 0x6d00\n-#define STM32H7_PG13_FUNC_TRACED0 0x6d01\n-#define STM32H7_PG13_FUNC_LPTIM1_OUT 0x6d02\n-#define STM32H7_PG13_FUNC_HRTIM_EEV10 0x6d03\n-#define STM32H7_PG13_FUNC_SPI6_SCK 0x6d06\n-#define STM32H7_PG13_FUNC_USART6_CTS_NSS 0x6d08\n-#define STM32H7_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0 0x6d0c\n-#define STM32H7_PG13_FUNC_FMC_A24 0x6d0d\n-#define STM32H7_PG13_FUNC_LCD_R0 0x6d0f\n-#define STM32H7_PG13_FUNC_EVENTOUT 0x6d10\n-#define STM32H7_PG13_FUNC_ANALOG 0x6d11\n-\n-#define STM32H7_PG14_FUNC_GPIO 0x6e00\n-#define STM32H7_PG14_FUNC_TRACED1 0x6e01\n-#define STM32H7_PG14_FUNC_LPTIM1_ETR 0x6e02\n-#define STM32H7_PG14_FUNC_SPI6_MOSI 0x6e06\n-#define STM32H7_PG14_FUNC_USART6_TX 0x6e08\n-#define STM32H7_PG14_FUNC_QUADSPI_BK2_IO3 0x6e0a\n-#define STM32H7_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1 0x6e0c\n-#define STM32H7_PG14_FUNC_FMC_A25 0x6e0d\n-#define STM32H7_PG14_FUNC_LCD_B0 0x6e0f\n-#define STM32H7_PG14_FUNC_EVENTOUT 0x6e10\n-#define STM32H7_PG14_FUNC_ANALOG 0x6e11\n-\n-#define STM32H7_PG15_FUNC_GPIO 0x6f00\n-#define STM32H7_PG15_FUNC_USART6_CTS_NSS 0x6f08\n-#define STM32H7_PG15_FUNC_FMC_SDNCAS 0x6f0d\n-#define STM32H7_PG15_FUNC_DCMI_D13 0x6f0e\n-#define STM32H7_PG15_FUNC_EVENTOUT 0x6f10\n-#define STM32H7_PG15_FUNC_ANALOG 0x6f11\n-\n-#define STM32H7_PH0_FUNC_GPIO 0x7000\n-#define STM32H7_PH0_FUNC_EVENTOUT 0x7010\n-#define STM32H7_PH0_FUNC_ANALOG 0x7011\n-\n-#define STM32H7_PH1_FUNC_GPIO 0x7100\n-#define STM32H7_PH1_FUNC_EVENTOUT 0x7110\n-#define STM32H7_PH1_FUNC_ANALOG 0x7111\n-\n-#define STM32H7_PH2_FUNC_GPIO 0x7200\n-#define STM32H7_PH2_FUNC_LPTIM1_IN2 0x7202\n-#define STM32H7_PH2_FUNC_QUADSPI_BK2_IO0 0x720a\n-#define STM32H7_PH2_FUNC_SAI2_SCK_B 0x720b\n-#define STM32H7_PH2_FUNC_ETH_MII_CRS 0x720c\n-#define STM32H7_PH2_FUNC_FMC_SDCKE0 0x720d\n-#define STM32H7_PH2_FUNC_LCD_R0 0x720f\n-#define STM32H7_PH2_FUNC_EVENTOUT 0x7210\n-#define STM32H7_PH2_FUNC_ANALOG 0x7211\n-\n-#define STM32H7_PH3_FUNC_GPIO 0x7300\n-#define STM32H7_PH3_FUNC_QUADSPI_BK2_IO1 0x730a\n-#define STM32H7_PH3_FUNC_SAI2_MCK_B 0x730b\n-#define STM32H7_PH3_FUNC_ETH_MII_COL 0x730c\n-#define STM32H7_PH3_FUNC_FMC_SDNE0 0x730d\n-#define STM32H7_PH3_FUNC_LCD_R1 0x730f\n-#define STM32H7_PH3_FUNC_EVENTOUT 0x7310\n-#define STM32H7_PH3_FUNC_ANALOG 0x7311\n-\n-#define STM32H7_PH4_FUNC_GPIO 0x7400\n-#define STM32H7_PH4_FUNC_I2C2_SCL 0x7405\n-#define STM32H7_PH4_FUNC_LCD_G5 0x740a\n-#define STM32H7_PH4_FUNC_OTG_HS_ULPI_NXT 0x740b\n-#define STM32H7_PH4_FUNC_LCD_G4 0x740f\n-#define STM32H7_PH4_FUNC_EVENTOUT 0x7410\n-#define STM32H7_PH4_FUNC_ANALOG 0x7411\n-\n-#define STM32H7_PH5_FUNC_GPIO 0x7500\n-#define STM32H7_PH5_FUNC_I2C2_SDA 0x7505\n-#define STM32H7_PH5_FUNC_SPI5_NSS 0x7506\n-#define STM32H7_PH5_FUNC_FMC_SDNWE 0x750d\n-#define STM32H7_PH5_FUNC_EVENTOUT 0x7510\n-#define STM32H7_PH5_FUNC_ANALOG 0x7511\n-\n-#define STM32H7_PH6_FUNC_GPIO 0x7600\n-#define STM32H7_PH6_FUNC_I2C2_SMBA 0x7605\n-#define STM32H7_PH6_FUNC_SPI5_SCK 0x7606\n-#define STM32H7_PH6_FUNC_ETH_MII_RXD2 0x760c\n-#define STM32H7_PH6_FUNC_FMC_SDNE1 0x760d\n-#define STM32H7_PH6_FUNC_DCMI_D8 0x760e\n-#define STM32H7_PH6_FUNC_EVENTOUT 0x7610\n-#define STM32H7_PH6_FUNC_ANALOG 0x7611\n-\n-#define STM32H7_PH7_FUNC_GPIO 0x7700\n-#define STM32H7_PH7_FUNC_I2C3_SCL 0x7705\n-#define STM32H7_PH7_FUNC_SPI5_MISO 0x7706\n-#define STM32H7_PH7_FUNC_ETH_MII_RXD3 0x770c\n-#define STM32H7_PH7_FUNC_FMC_SDCKE1 0x770d\n-#define STM32H7_PH7_FUNC_DCMI_D9 0x770e\n-#define STM32H7_PH7_FUNC_EVENTOUT 0x7710\n-#define STM32H7_PH7_FUNC_ANALOG 0x7711\n-\n-#define STM32H7_PH8_FUNC_GPIO 0x7800\n-#define STM32H7_PH8_FUNC_TIM5_ETR 0x7803\n-#define STM32H7_PH8_FUNC_I2C3_SDA 0x7805\n-#define STM32H7_PH8_FUNC_FMC_D16 0x780d\n-#define STM32H7_PH8_FUNC_DCMI_HSYNC 0x780e\n-#define STM32H7_PH8_FUNC_LCD_R2 0x780f\n-#define STM32H7_PH8_FUNC_EVENTOUT 0x7810\n-#define STM32H7_PH8_FUNC_ANALOG 0x7811\n-\n-#define STM32H7_PH9_FUNC_GPIO 0x7900\n-#define STM32H7_PH9_FUNC_I2C3_SMBA 0x7905\n-#define STM32H7_PH9_FUNC_FMC_D17 0x790d\n-#define STM32H7_PH9_FUNC_DCMI_D0 0x790e\n-#define STM32H7_PH9_FUNC_LCD_R3 0x790f\n-#define STM32H7_PH9_FUNC_EVENTOUT 0x7910\n-#define STM32H7_PH9_FUNC_ANALOG 0x7911\n-\n-#define STM32H7_PH10_FUNC_GPIO 0x7a00\n-#define STM32H7_PH10_FUNC_TIM5_CH1 0x7a03\n-#define STM32H7_PH10_FUNC_I2C4_SMBA 0x7a05\n-#define STM32H7_PH10_FUNC_FMC_D18 0x7a0d\n-#define STM32H7_PH10_FUNC_DCMI_D1 0x7a0e\n-#define STM32H7_PH10_FUNC_LCD_R4 0x7a0f\n-#define STM32H7_PH10_FUNC_EVENTOUT 0x7a10\n-#define STM32H7_PH10_FUNC_ANALOG 0x7a11\n-\n-#define STM32H7_PH11_FUNC_GPIO 0x7b00\n-#define STM32H7_PH11_FUNC_TIM5_CH2 0x7b03\n-#define STM32H7_PH11_FUNC_I2C4_SCL 0x7b05\n-#define STM32H7_PH11_FUNC_FMC_D19 0x7b0d\n-#define STM32H7_PH11_FUNC_DCMI_D2 0x7b0e\n-#define STM32H7_PH11_FUNC_LCD_R5 0x7b0f\n-#define STM32H7_PH11_FUNC_EVENTOUT 0x7b10\n-#define STM32H7_PH11_FUNC_ANALOG 0x7b11\n-\n-#define STM32H7_PH12_FUNC_GPIO 0x7c00\n-#define STM32H7_PH12_FUNC_TIM5_CH3 0x7c03\n-#define STM32H7_PH12_FUNC_I2C4_SDA 0x7c05\n-#define STM32H7_PH12_FUNC_FMC_D20 0x7c0d\n-#define STM32H7_PH12_FUNC_DCMI_D3 0x7c0e\n-#define STM32H7_PH12_FUNC_LCD_R6 0x7c0f\n-#define STM32H7_PH12_FUNC_EVENTOUT 0x7c10\n-#define STM32H7_PH12_FUNC_ANALOG 0x7c11\n-\n-#define STM32H7_PH13_FUNC_GPIO 0x7d00\n-#define STM32H7_PH13_FUNC_TIM8_CH1N 0x7d04\n-#define STM32H7_PH13_FUNC_UART4_TX 0x7d09\n-#define STM32H7_PH13_FUNC_CAN1_TX 0x7d0a\n-#define STM32H7_PH13_FUNC_FMC_D21 0x7d0d\n-#define STM32H7_PH13_FUNC_LCD_G2 0x7d0f\n-#define STM32H7_PH13_FUNC_EVENTOUT 0x7d10\n-#define STM32H7_PH13_FUNC_ANALOG 0x7d11\n-\n-#define STM32H7_PH14_FUNC_GPIO 0x7e00\n-#define STM32H7_PH14_FUNC_TIM8_CH2N 0x7e04\n-#define STM32H7_PH14_FUNC_UART4_RX 0x7e09\n-#define STM32H7_PH14_FUNC_CAN1_RX 0x7e0a\n-#define STM32H7_PH14_FUNC_FMC_D22 0x7e0d\n-#define STM32H7_PH14_FUNC_DCMI_D4 0x7e0e\n-#define STM32H7_PH14_FUNC_LCD_G3 0x7e0f\n-#define STM32H7_PH14_FUNC_EVENTOUT 0x7e10\n-#define STM32H7_PH14_FUNC_ANALOG 0x7e11\n-\n-#define STM32H7_PH15_FUNC_GPIO 0x7f00\n-#define STM32H7_PH15_FUNC_TIM8_CH3N 0x7f04\n-#define STM32H7_PH15_FUNC_CAN1_TXFD 0x7f0a\n-#define STM32H7_PH15_FUNC_FMC_D23 0x7f0d\n-#define STM32H7_PH15_FUNC_DCMI_D11 0x7f0e\n-#define STM32H7_PH15_FUNC_LCD_G4 0x7f0f\n-#define STM32H7_PH15_FUNC_EVENTOUT 0x7f10\n-#define STM32H7_PH15_FUNC_ANALOG 0x7f11\n-\n-#define STM32H7_PI0_FUNC_GPIO 0x8000\n-#define STM32H7_PI0_FUNC_TIM5_CH4 0x8003\n-#define STM32H7_PI0_FUNC_SPI2_NSS_I2S2_WS 0x8006\n-#define STM32H7_PI0_FUNC_CAN1_RXFD 0x800a\n-#define STM32H7_PI0_FUNC_FMC_D24 0x800d\n-#define STM32H7_PI0_FUNC_DCMI_D13 0x800e\n-#define STM32H7_PI0_FUNC_LCD_G5 0x800f\n-#define STM32H7_PI0_FUNC_EVENTOUT 0x8010\n-#define STM32H7_PI0_FUNC_ANALOG 0x8011\n-\n-#define STM32H7_PI1_FUNC_GPIO 0x8100\n-#define STM32H7_PI1_FUNC_TIM8_BKIN2 0x8104\n-#define STM32H7_PI1_FUNC_SPI2_SCK_I2S2_CK 0x8106\n-#define STM32H7_PI1_FUNC_TIM8_BKIN2_COMP12 0x810c\n-#define STM32H7_PI1_FUNC_FMC_D25 0x810d\n-#define STM32H7_PI1_FUNC_DCMI_D8 0x810e\n-#define STM32H7_PI1_FUNC_LCD_G6 0x810f\n-#define STM32H7_PI1_FUNC_EVENTOUT 0x8110\n-#define STM32H7_PI1_FUNC_ANALOG 0x8111\n-\n-#define STM32H7_PI2_FUNC_GPIO 0x8200\n-#define STM32H7_PI2_FUNC_TIM8_CH4 0x8204\n-#define STM32H7_PI2_FUNC_SPI2_MISO_I2S2_SDI 0x8206\n-#define STM32H7_PI2_FUNC_FMC_D26 0x820d\n-#define STM32H7_PI2_FUNC_DCMI_D9 0x820e\n-#define STM32H7_PI2_FUNC_LCD_G7 0x820f\n-#define STM32H7_PI2_FUNC_EVENTOUT 0x8210\n-#define STM32H7_PI2_FUNC_ANALOG 0x8211\n-\n-#define STM32H7_PI3_FUNC_GPIO 0x8300\n-#define STM32H7_PI3_FUNC_TIM8_ETR 0x8304\n-#define STM32H7_PI3_FUNC_SPI2_MOSI_I2S2_SDO 0x8306\n-#define STM32H7_PI3_FUNC_FMC_D27 0x830d\n-#define STM32H7_PI3_FUNC_DCMI_D10 0x830e\n-#define STM32H7_PI3_FUNC_EVENTOUT 0x8310\n-#define STM32H7_PI3_FUNC_ANALOG 0x8311\n-\n-#define STM32H7_PI4_FUNC_GPIO 0x8400\n-#define STM32H7_PI4_FUNC_TIM8_BKIN 0x8404\n-#define STM32H7_PI4_FUNC_SAI2_MCK_A 0x840b\n-#define STM32H7_PI4_FUNC_TIM8_BKIN_COMP12 0x840c\n-#define STM32H7_PI4_FUNC_FMC_NBL2 0x840d\n-#define STM32H7_PI4_FUNC_DCMI_D5 0x840e\n-#define STM32H7_PI4_FUNC_LCD_B4 0x840f\n-#define STM32H7_PI4_FUNC_EVENTOUT 0x8410\n-#define STM32H7_PI4_FUNC_ANALOG 0x8411\n-\n-#define STM32H7_PI5_FUNC_GPIO 0x8500\n-#define STM32H7_PI5_FUNC_TIM8_CH1 0x8504\n-#define STM32H7_PI5_FUNC_SAI2_SCK_A 0x850b\n-#define STM32H7_PI5_FUNC_FMC_NBL3 0x850d\n-#define STM32H7_PI5_FUNC_DCMI_VSYNC 0x850e\n-#define STM32H7_PI5_FUNC_LCD_B5 0x850f\n-#define STM32H7_PI5_FUNC_EVENTOUT 0x8510\n-#define STM32H7_PI5_FUNC_ANALOG 0x8511\n-\n-#define STM32H7_PI6_FUNC_GPIO 0x8600\n-#define STM32H7_PI6_FUNC_TIM8_CH2 0x8604\n-#define STM32H7_PI6_FUNC_SAI2_SD_A 0x860b\n-#define STM32H7_PI6_FUNC_FMC_D28 0x860d\n-#define STM32H7_PI6_FUNC_DCMI_D6 0x860e\n-#define STM32H7_PI6_FUNC_LCD_B6 0x860f\n-#define STM32H7_PI6_FUNC_EVENTOUT 0x8610\n-#define STM32H7_PI6_FUNC_ANALOG 0x8611\n-\n-#define STM32H7_PI7_FUNC_GPIO 0x8700\n-#define STM32H7_PI7_FUNC_TIM8_CH3 0x8704\n-#define STM32H7_PI7_FUNC_SAI2_FS_A 0x870b\n-#define STM32H7_PI7_FUNC_FMC_D29 0x870d\n-#define STM32H7_PI7_FUNC_DCMI_D7 0x870e\n-#define STM32H7_PI7_FUNC_LCD_B7 0x870f\n-#define STM32H7_PI7_FUNC_EVENTOUT 0x8710\n-#define STM32H7_PI7_FUNC_ANALOG 0x8711\n-\n-#define STM32H7_PI8_FUNC_GPIO 0x8800\n-#define STM32H7_PI8_FUNC_EVENTOUT 0x8810\n-#define STM32H7_PI8_FUNC_ANALOG 0x8811\n-\n-#define STM32H7_PI9_FUNC_GPIO 0x8900\n-#define STM32H7_PI9_FUNC_UART4_RX 0x8909\n-#define STM32H7_PI9_FUNC_CAN1_RX 0x890a\n-#define STM32H7_PI9_FUNC_FMC_D30 0x890d\n-#define STM32H7_PI9_FUNC_LCD_VSYNC 0x890f\n-#define STM32H7_PI9_FUNC_EVENTOUT 0x8910\n-#define STM32H7_PI9_FUNC_ANALOG 0x8911\n-\n-#define STM32H7_PI10_FUNC_GPIO 0x8a00\n-#define STM32H7_PI10_FUNC_CAN1_RXFD 0x8a0a\n-#define STM32H7_PI10_FUNC_ETH_MII_RX_ER 0x8a0c\n-#define STM32H7_PI10_FUNC_FMC_D31 0x8a0d\n-#define STM32H7_PI10_FUNC_LCD_HSYNC 0x8a0f\n-#define STM32H7_PI10_FUNC_EVENTOUT 0x8a10\n-#define STM32H7_PI10_FUNC_ANALOG 0x8a11\n-\n-#define STM32H7_PI11_FUNC_GPIO 0x8b00\n-#define STM32H7_PI11_FUNC_LCD_G6 0x8b0a\n-#define STM32H7_PI11_FUNC_OTG_HS_ULPI_DIR 0x8b0b\n-#define STM32H7_PI11_FUNC_EVENTOUT 0x8b10\n-#define STM32H7_PI11_FUNC_ANALOG 0x8b11\n-\n-#define STM32H7_PI12_FUNC_GPIO 0x8c00\n-#define STM32H7_PI12_FUNC_ETH_TX_ER 0x8c0c\n-#define STM32H7_PI12_FUNC_LCD_HSYNC 0x8c0f\n-#define STM32H7_PI12_FUNC_EVENTOUT 0x8c10\n-#define STM32H7_PI12_FUNC_ANALOG 0x8c11\n-\n-#define STM32H7_PI13_FUNC_GPIO 0x8d00\n-#define STM32H7_PI13_FUNC_LCD_VSYNC 0x8d0f\n-#define STM32H7_PI13_FUNC_EVENTOUT 0x8d10\n-#define STM32H7_PI13_FUNC_ANALOG 0x8d11\n-\n-#define STM32H7_PI14_FUNC_GPIO 0x8e00\n-#define STM32H7_PI14_FUNC_LCD_CLK 0x8e0f\n-#define STM32H7_PI14_FUNC_EVENTOUT 0x8e10\n-#define STM32H7_PI14_FUNC_ANALOG 0x8e11\n-\n-#define STM32H7_PI15_FUNC_GPIO 0x8f00\n-#define STM32H7_PI15_FUNC_LCD_G2 0x8f0a\n-#define STM32H7_PI15_FUNC_LCD_R0 0x8f0f\n-#define STM32H7_PI15_FUNC_EVENTOUT 0x8f10\n-#define STM32H7_PI15_FUNC_ANALOG 0x8f11\n-\n-#define STM32H7_PJ0_FUNC_GPIO 0x9000\n-#define STM32H7_PJ0_FUNC_LCD_R7 0x900a\n-#define STM32H7_PJ0_FUNC_LCD_R1 0x900f\n-#define STM32H7_PJ0_FUNC_EVENTOUT 0x9010\n-#define STM32H7_PJ0_FUNC_ANALOG 0x9011\n-\n-#define STM32H7_PJ1_FUNC_GPIO 0x9100\n-#define STM32H7_PJ1_FUNC_LCD_R2 0x910f\n-#define STM32H7_PJ1_FUNC_EVENTOUT 0x9110\n-#define STM32H7_PJ1_FUNC_ANALOG 0x9111\n-\n-#define STM32H7_PJ2_FUNC_GPIO 0x9200\n-#define STM32H7_PJ2_FUNC_DSI_TE 0x920e\n-#define STM32H7_PJ2_FUNC_LCD_R3 0x920f\n-#define STM32H7_PJ2_FUNC_EVENTOUT 0x9210\n-#define STM32H7_PJ2_FUNC_ANALOG 0x9211\n-\n-#define STM32H7_PJ3_FUNC_GPIO 0x9300\n-#define STM32H7_PJ3_FUNC_LCD_R4 0x930f\n-#define STM32H7_PJ3_FUNC_EVENTOUT 0x9310\n-#define STM32H7_PJ3_FUNC_ANALOG 0x9311\n-\n-#define STM32H7_PJ4_FUNC_GPIO 0x9400\n-#define STM32H7_PJ4_FUNC_LCD_R5 0x940f\n-#define STM32H7_PJ4_FUNC_EVENTOUT 0x9410\n-#define STM32H7_PJ4_FUNC_ANALOG 0x9411\n-\n-#define STM32H7_PJ5_FUNC_GPIO 0x9500\n-#define STM32H7_PJ5_FUNC_LCD_R6 0x950f\n-#define STM32H7_PJ5_FUNC_EVENTOUT 0x9510\n-#define STM32H7_PJ5_FUNC_ANALOG 0x9511\n-\n-#define STM32H7_PJ6_FUNC_GPIO 0x9600\n-#define STM32H7_PJ6_FUNC_TIM8_CH2 0x9604\n-#define STM32H7_PJ6_FUNC_LCD_R7 0x960f\n-#define STM32H7_PJ6_FUNC_EVENTOUT 0x9610\n-#define STM32H7_PJ6_FUNC_ANALOG 0x9611\n-\n-#define STM32H7_PJ7_FUNC_GPIO 0x9700\n-#define STM32H7_PJ7_FUNC_TRGIN 0x9701\n-#define STM32H7_PJ7_FUNC_TIM8_CH2N 0x9704\n-#define STM32H7_PJ7_FUNC_LCD_G0 0x970f\n-#define STM32H7_PJ7_FUNC_EVENTOUT 0x9710\n-#define STM32H7_PJ7_FUNC_ANALOG 0x9711\n-\n-#define STM32H7_PJ8_FUNC_GPIO 0x9800\n-#define STM32H7_PJ8_FUNC_TIM1_CH3N 0x9802\n-#define STM32H7_PJ8_FUNC_TIM8_CH1 0x9804\n-#define STM32H7_PJ8_FUNC_UART8_TX 0x9809\n-#define STM32H7_PJ8_FUNC_LCD_G1 0x980f\n-#define STM32H7_PJ8_FUNC_EVENTOUT 0x9810\n-#define STM32H7_PJ8_FUNC_ANALOG 0x9811\n-\n-#define STM32H7_PJ9_FUNC_GPIO 0x9900\n-#define STM32H7_PJ9_FUNC_TIM1_CH3 0x9902\n-#define STM32H7_PJ9_FUNC_TIM8_CH1N 0x9904\n-#define STM32H7_PJ9_FUNC_UART8_RX 0x9909\n-#define STM32H7_PJ9_FUNC_LCD_G2 0x990f\n-#define STM32H7_PJ9_FUNC_EVENTOUT 0x9910\n-#define STM32H7_PJ9_FUNC_ANALOG 0x9911\n-\n-#define STM32H7_PJ10_FUNC_GPIO 0x9a00\n-#define STM32H7_PJ10_FUNC_TIM1_CH2N 0x9a02\n-#define STM32H7_PJ10_FUNC_TIM8_CH2 0x9a04\n-#define STM32H7_PJ10_FUNC_SPI5_MOSI 0x9a06\n-#define STM32H7_PJ10_FUNC_LCD_G3 0x9a0f\n-#define STM32H7_PJ10_FUNC_EVENTOUT 0x9a10\n-#define STM32H7_PJ10_FUNC_ANALOG 0x9a11\n-\n-#define STM32H7_PJ11_FUNC_GPIO 0x9b00\n-#define STM32H7_PJ11_FUNC_TIM1_CH2 0x9b02\n-#define STM32H7_PJ11_FUNC_TIM8_CH2N 0x9b04\n-#define STM32H7_PJ11_FUNC_SPI5_MISO 0x9b06\n-#define STM32H7_PJ11_FUNC_LCD_G4 0x9b0f\n-#define STM32H7_PJ11_FUNC_EVENTOUT 0x9b10\n-#define STM32H7_PJ11_FUNC_ANALOG 0x9b11\n-\n-#define STM32H7_PJ12_FUNC_GPIO 0x9c00\n-#define STM32H7_PJ12_FUNC_TRGOUT 0x9c01\n-#define STM32H7_PJ12_FUNC_LCD_G3 0x9c0a\n-#define STM32H7_PJ12_FUNC_LCD_B0 0x9c0f\n-#define STM32H7_PJ12_FUNC_EVENTOUT 0x9c10\n-#define STM32H7_PJ12_FUNC_ANALOG 0x9c11\n-\n-#define STM32H7_PJ13_FUNC_GPIO 0x9d00\n-#define STM32H7_PJ13_FUNC_LCD_B4 0x9d0a\n-#define STM32H7_PJ13_FUNC_LCD_B1 0x9d0f\n-#define STM32H7_PJ13_FUNC_EVENTOUT 0x9d10\n-#define STM32H7_PJ13_FUNC_ANALOG 0x9d11\n-\n-#define STM32H7_PJ14_FUNC_GPIO 0x9e00\n-#define STM32H7_PJ14_FUNC_LCD_B2 0x9e0f\n-#define STM32H7_PJ14_FUNC_EVENTOUT 0x9e10\n-#define STM32H7_PJ14_FUNC_ANALOG 0x9e11\n-\n-#define STM32H7_PJ15_FUNC_GPIO 0x9f00\n-#define STM32H7_PJ15_FUNC_LCD_B3 0x9f0f\n-#define STM32H7_PJ15_FUNC_EVENTOUT 0x9f10\n-#define STM32H7_PJ15_FUNC_ANALOG 0x9f11\n-\n-#define STM32H7_PK0_FUNC_GPIO 0xa000\n-#define STM32H7_PK0_FUNC_TIM1_CH1N 0xa002\n-#define STM32H7_PK0_FUNC_TIM8_CH3 0xa004\n-#define STM32H7_PK0_FUNC_SPI5_SCK 0xa006\n-#define STM32H7_PK0_FUNC_LCD_G5 0xa00f\n-#define STM32H7_PK0_FUNC_EVENTOUT 0xa010\n-#define STM32H7_PK0_FUNC_ANALOG 0xa011\n-\n-#define STM32H7_PK1_FUNC_GPIO 0xa100\n-#define STM32H7_PK1_FUNC_TIM1_CH1 0xa102\n-#define STM32H7_PK1_FUNC_TIM8_CH3N 0xa104\n-#define STM32H7_PK1_FUNC_SPI5_NSS 0xa106\n-#define STM32H7_PK1_FUNC_LCD_G6 0xa10f\n-#define STM32H7_PK1_FUNC_EVENTOUT 0xa110\n-#define STM32H7_PK1_FUNC_ANALOG 0xa111\n-\n-#define STM32H7_PK2_FUNC_GPIO 0xa200\n-#define STM32H7_PK2_FUNC_TIM1_BKIN 0xa202\n-#define STM32H7_PK2_FUNC_TIM8_BKIN 0xa204\n-#define STM32H7_PK2_FUNC_TIM8_BKIN_COMP12 0xa20b\n-#define STM32H7_PK2_FUNC_TIM1_BKIN_COMP12 0xa20c\n-#define STM32H7_PK2_FUNC_LCD_G7 0xa20f\n-#define STM32H7_PK2_FUNC_EVENTOUT 0xa210\n-#define STM32H7_PK2_FUNC_ANALOG 0xa211\n-\n-#define STM32H7_PK3_FUNC_GPIO 0xa300\n-#define STM32H7_PK3_FUNC_LCD_B4 0xa30f\n-#define STM32H7_PK3_FUNC_EVENTOUT 0xa310\n-#define STM32H7_PK3_FUNC_ANALOG 0xa311\n-\n-#define STM32H7_PK4_FUNC_GPIO 0xa400\n-#define STM32H7_PK4_FUNC_LCD_B5 0xa40f\n-#define STM32H7_PK4_FUNC_EVENTOUT 0xa410\n-#define STM32H7_PK4_FUNC_ANALOG 0xa411\n-\n-#define STM32H7_PK5_FUNC_GPIO 0xa500\n-#define STM32H7_PK5_FUNC_LCD_B6 0xa50f\n-#define STM32H7_PK5_FUNC_EVENTOUT 0xa510\n-#define STM32H7_PK5_FUNC_ANALOG 0xa511\n-\n-#define STM32H7_PK6_FUNC_GPIO 0xa600\n-#define STM32H7_PK6_FUNC_LCD_B7 0xa60f\n-#define STM32H7_PK6_FUNC_EVENTOUT 0xa610\n-#define STM32H7_PK6_FUNC_ANALOG 0xa611\n-\n-#define STM32H7_PK7_FUNC_GPIO 0xa700\n-#define STM32H7_PK7_FUNC_LCD_DE 0xa70f\n-#define STM32H7_PK7_FUNC_EVENTOUT 0xa710\n-#define STM32H7_PK7_FUNC_ANALOG 0xa711\n-\n-#endif /* _DT_BINDINGS_STM32H7_PINFUNC_H */\n","prefixes":["v4"]}