{"id":807442,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807442/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1504073693-16900-10-git-send-email-peng.fan@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504073693-16900-10-git-send-email-peng.fan@nxp.com>","list_archive_url":null,"date":"2017-08-30T06:14:51","name":"[U-Boot,V4,10/12] board: freescale: common: add pfuze dm code","commit_ref":null,"pull_url":null,"state":"changes-requested","archived":false,"hash":"99bfe07e90ebc6e63d5724d17b94c73604c7ef78","submitter":{"id":67896,"url":"http://patchwork.ozlabs.org/api/1.2/people/67896/?format=json","name":"Peng Fan","email":"peng.fan@nxp.com"},"delegate":{"id":1693,"url":"http://patchwork.ozlabs.org/api/1.2/users/1693/?format=json","username":"sbabic","first_name":"Stefano","last_name":"Babic","email":"sbabic@denx.de"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1504073693-16900-10-git-send-email-peng.fan@nxp.com/mbox/","series":[{"id":530,"url":"http://patchwork.ozlabs.org/api/1.2/series/530/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=530","date":"2017-08-30T06:14:42","name":"[U-Boot,V4,01/12] scripts: spl: fix typo","version":4,"mbox":"http://patchwork.ozlabs.org/series/530/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807442/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807442/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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SFP:1101; SCL:1; SRVR:AM5PR04MB3217;\n\tH:linux-u7w5.ap.freescale.net; \n\tFPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"nxp.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"30 Aug 2017 06:16:52.1719\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"AM5PR04MB3217","Cc":"u-boot@lists.denx.de","Subject":"[U-Boot] [PATCH V4 10/12] board: freescale: common: add pfuze dm\n\tcode","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Add pfuze dm code, this code does the same thing as pfuze.c, but\nonly effects when CONFIG_$(SPL_)DM_PMIC_PFUZE100 enabled.\n\nSigned-off-by: Peng Fan \nCc: York Sun \nCc: Jaehoon Chung \nCc: Stefano Babic \n---\n\nV2->V4: none\n\n board/freescale/common/Makefile | 1 +\n board/freescale/common/pfuze.h | 5 +++\n board/freescale/common/pfuze_dm.c | 89 +++++++++++++++++++++++++++++++++++++++\n 3 files changed, 95 insertions(+)\n create mode 100644 board/freescale/common/pfuze_dm.c","diff":"diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile\nindex 1c53fb6..620dced 100644\n--- a/board/freescale/common/Makefile\n+++ b/board/freescale/common/Makefile\n@@ -61,6 +61,7 @@ obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o\n obj-$(CONFIG_IDT8T49N222A)\t+= idt8t49n222a_serdes_clk.o\n obj-$(CONFIG_ZM7300)\t\t+= zm7300.o\n obj-$(CONFIG_POWER_PFUZE100)\t+= pfuze.o\n+obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze_dm.o\n obj-$(CONFIG_POWER_MC34VR500)\t+= mc34vr500.o\n \n obj-$(CONFIG_LS102XA_STREAM_ID)\t+= ls102xa_stream_id.o\ndiff --git a/board/freescale/common/pfuze.h b/board/freescale/common/pfuze.h\nindex 53cfc99..9c4c92a 100644\n--- a/board/freescale/common/pfuze.h\n+++ b/board/freescale/common/pfuze.h\n@@ -7,7 +7,12 @@\n #ifndef __PFUZE_BOARD_HELPER__\n #define __PFUZE_BOARD_HELPER__\n \n+#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)\n+struct udevice *pfuze_common_init(void);\n+int pfuze_mode_init(struct udevice *dev, u32 mode);\n+#else\n struct pmic *pfuze_common_init(unsigned char i2cbus);\n int pfuze_mode_init(struct pmic *p, u32 mode);\n+#endif\n \n #endif\ndiff --git a/board/freescale/common/pfuze_dm.c b/board/freescale/common/pfuze_dm.c\nnew file mode 100644\nindex 0000000..c6af627\n--- /dev/null\n+++ b/board/freescale/common/pfuze_dm.c\n@@ -0,0 +1,89 @@\n+/*\n+ * Copyright 2017 NXP\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+\n+int pfuze_mode_init(struct udevice *dev, u32 mode)\n+{\n+\tunsigned char offset, i, switch_num;\n+\tu32 id;\n+\tint ret;\n+\n+\tid = pmic_reg_read(dev, PFUZE100_DEVICEID);\n+\tid = id & 0xf;\n+\n+\tif (id == 0) {\n+\t\tswitch_num = 6;\n+\t\toffset = PFUZE100_SW1CMODE;\n+\t} else if (id == 1) {\n+\t\tswitch_num = 4;\n+\t\toffset = PFUZE100_SW2MODE;\n+\t} else {\n+\t\tprintf(\"Not supported, id=%d\\n\", id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);\n+\tif (ret < 0) {\n+\t\tprintf(\"Set SW1AB mode error!\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tfor (i = 0; i < switch_num - 1; i++) {\n+\t\tret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);\n+\t\tif (ret < 0) {\n+\t\t\tprintf(\"Set switch 0x%x mode error!\\n\",\n+\t\t\t offset + i * SWITCH_SIZE);\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+struct udevice *pfuze_common_init(void)\n+{\n+\tstruct udevice *dev;\n+\tint ret;\n+\tunsigned int reg, dev_id, rev_id;\n+\n+\tret = pmic_get(\"pfuze100\", &dev);\n+\tif (ret == -ENODEV)\n+\t\treturn NULL;\n+\n+\tdev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);\n+\trev_id = pmic_reg_read(dev, PFUZE100_REVID);\n+\tprintf(\"PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\\n\", dev_id, rev_id);\n+\n+\t/* Set SW1AB stanby volage to 0.975V */\n+\treg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);\n+\treg &= ~SW1x_STBY_MASK;\n+\treg |= SW1x_0_975V;\n+\tpmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);\n+\n+\t/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */\n+\treg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);\n+\treg &= ~SW1xCONF_DVSSPEED_MASK;\n+\treg |= SW1xCONF_DVSSPEED_4US;\n+\tpmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);\n+\n+\t/* Set SW1C standby voltage to 0.975V */\n+\treg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);\n+\treg &= ~SW1x_STBY_MASK;\n+\treg |= SW1x_0_975V;\n+\tpmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);\n+\n+\t/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */\n+\treg = pmic_reg_read(dev, PFUZE100_SW1CCONF);\n+\treg &= ~SW1xCONF_DVSSPEED_MASK;\n+\treg |= SW1xCONF_DVSSPEED_4US;\n+\tpmic_reg_write(dev, PFUZE100_SW1CCONF, reg);\n+\n+\treturn dev;\n+}\n","prefixes":["U-Boot","V4","10/12"]}