{"id":807315,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807315/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/patch/1504041387.5204.20.camel@cavium.com/","project":{"id":41,"url":"http://patchwork.ozlabs.org/api/1.2/projects/41/?format=json","name":"GNU C Library","link_name":"glibc","list_id":"libc-alpha.sourceware.org","list_email":"libc-alpha@sourceware.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504041387.5204.20.camel@cavium.com>","list_archive_url":null,"date":"2017-08-29T21:16:27","name":"[AArch64] ILP32 math changes","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"8d39bde1a7d81a180acd3dd95cda65d2aec948e2","submitter":{"id":70332,"url":"http://patchwork.ozlabs.org/api/1.2/people/70332/?format=json","name":"Steve Ellcey","email":"sellcey@cavium.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/glibc/patch/1504041387.5204.20.camel@cavium.com/mbox/","series":[{"id":479,"url":"http://patchwork.ozlabs.org/api/1.2/series/479/?format=json","web_url":"http://patchwork.ozlabs.org/project/glibc/list/?series=479","date":"2017-08-29T21:16:27","name":"[AArch64] ILP32 math changes","version":1,"mbox":"http://patchwork.ozlabs.org/series/479/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807315/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807315/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list libc-alpha@sourceware.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=sourceware.org\n\t(client-ip=209.132.180.131; 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PCL:0;\n\tRULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(102415395)(6040450)(601004)(2401047)(5005006)(8121501046)(100000703101)(100105400095)(93006095)(93001095)(10201501046)(3002001)(6041248)(20161123558100)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123564025)(20161123562025)(20161123555025)(20161123560025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095);\n\tSRVR:MWHPR07MB3549; BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:MWHPR07MB3549; ","X-Forefront-PRVS":"0414DF926F","X-Forefront-Antispam-Report":"SFV:NSPM;\n\tSFS:(10009020)(4630300001)(7370300001)(6009001)(199003)(377424004)(189002)(54906002)(8676002)(3846002)(103116003)(81166006)(68736007)(6506006)(7350300001)(81156014)(4326008)(84326002)(69596002)(5660300001)(305945005)(6916009)(36756003)(512874002)(50226002)(6486002)(6116002)(7736002)(5890100001)(6512007)(25786009)(106356001)(105586002)(72206003)(110136004)(66066001)(53936002)(50986999)(2476003)(2906002)(4610100001)(478600001)(568964002)(42186005)(33646002)(101416001)(189998001)(97736004)(53416004)(43066003)(3450700001)(99106002);\n\tDIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR07MB3549;\n\tH:sellcey-dt.caveonetworks.com; FPR:; SPF:None;\n\tPTR:InfoNoRecords; A:1; MX:1; LANG:en; ","Received-SPF":"None (protection.outlook.com: cavium.com does not designate\n\tpermitted sender hosts)","SpamDiagnosticOutput":"1:99","SpamDiagnosticMetadata":"NSPM","X-OriginatorOrg":"cavium.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"29 Aug 2017 21:16:29.8308\n\t(UTC)","X-MS-Exchange-CrossTenant-FromEntityHeader":"Hosted","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"MWHPR07MB3549"},"content":"Since Szabolcs has expressed interest in getting some aarch64 ILP32\nchanges into glibc mainline (if they don't affect the kernel or glibc\nABI) I am resubmitting this patch for approval in advance of the main\nILP32 support patches.  I updated it with Richard Henderson's code (but\nonly doing it when the incoming argument is large).  I tested it on\naarch64 ILP32 and LP64 with no regressions.\n\nIs this something that can be checked in now withnout waiting for the\nkernel ILP32 support?\n\nSteve Ellcey\nsellcey@cavium.com\n\n\n2017-08-29  Steve Ellcey  \n\t    Richard Henderson \n\n\t* sysdeps/aarch64/fpu/s_llrint.c (OREG_SIZE): New macro.\n\t* sysdeps/aarch64/fpu/s_llround.c (OREG_SIZE): Likewise.\n\t* sysdeps/aarch64/fpu/s_llrintf.c (OREGS, IREGS): Remove.\n\t(IREG_SIZE, OREG_SIZE): New macros.\n\t* sysdeps/aarch64/fpu/s_llroundf.c: (OREGS, IREGS): Remove.\n\t(IREG_SIZE, OREG_SIZE): New macros.\n\t* sysdeps/aarch64/fpu/s_lrintf.c (IREGS): Remove.\n\t(IREG_SIZE): New macro.\n\t* sysdeps/aarch64/fpu/s_lroundf.c (IREGS): Remove.\n\t(IREG_SIZE): New macro.\n\t* sysdeps/aarch64/fpu/s_lrint.c (get-rounding-mode.h, stdint.h):\n\tNew includes.\n\t(IREG_SIZE, OREG_SIZE): Initialize if not already set.\n\t(OREGS, IREGS): Set based on IREG_SIZE and OREG_SIZE.\n\t(__CONCATX): Handle exceptions correctly on large values that may\n\tset FE_INVALID.\n\t* sysdeps/aarch64/fpu/s_lround.c (IREG_SIZE, OREG_SIZE):\n\tInitialize if not already set.\n        (OREGS, IREGS): Set based on IREG_SIZE and OREG_SIZE.","diff":"diff --git a/sysdeps/aarch64/fpu/s_llrint.c b/sysdeps/aarch64/fpu/s_llrint.c\nindex c0d0d0e..57821c0 100644\n--- a/sysdeps/aarch64/fpu/s_llrint.c\n+++ b/sysdeps/aarch64/fpu/s_llrint.c\n@@ -18,4 +18,5 @@\n \n #define FUNC llrint\n #define OTYPE long long int\n+#define OREG_SIZE 64\n #include \ndiff --git a/sysdeps/aarch64/fpu/s_llrintf.c b/sysdeps/aarch64/fpu/s_llrintf.c\nindex 67724c6..98ed4f8 100644\n--- a/sysdeps/aarch64/fpu/s_llrintf.c\n+++ b/sysdeps/aarch64/fpu/s_llrintf.c\n@@ -18,6 +18,7 @@\n \n #define FUNC llrintf\n #define ITYPE float\n-#define IREGS \"s\"\n+#define IREG_SIZE 32\n #define OTYPE long long int\n+#define OREG_SIZE 64\n #include \ndiff --git a/sysdeps/aarch64/fpu/s_llround.c b/sysdeps/aarch64/fpu/s_llround.c\nindex ed4b192..ef7aedf 100644\n--- a/sysdeps/aarch64/fpu/s_llround.c\n+++ b/sysdeps/aarch64/fpu/s_llround.c\n@@ -18,4 +18,5 @@\n \n #define FUNC llround\n #define OTYPE long long int\n+#define OREG_SIZE 64\n #include \ndiff --git a/sysdeps/aarch64/fpu/s_llroundf.c b/sysdeps/aarch64/fpu/s_llroundf.c\nindex 360ce8b..294f0f4 100644\n--- a/sysdeps/aarch64/fpu/s_llroundf.c\n+++ b/sysdeps/aarch64/fpu/s_llroundf.c\n@@ -18,6 +18,7 @@\n \n #define FUNC llroundf\n #define ITYPE float\n-#define IREGS \"s\"\n+#define IREG_SIZE 32\n #define OTYPE long long int\n+#define OREG_SIZE 64\n #include \ndiff --git a/sysdeps/aarch64/fpu/s_lrint.c b/sysdeps/aarch64/fpu/s_lrint.c\nindex 8c61a03..6ef64e2 100644\n--- a/sysdeps/aarch64/fpu/s_lrint.c\n+++ b/sysdeps/aarch64/fpu/s_lrint.c\n@@ -17,6 +17,8 @@\n . */\n \n #include \n+#include \n+#include \n \n #ifndef FUNC\n # define FUNC lrint\n@@ -24,18 +26,37 @@\n \n #ifndef ITYPE\n # define ITYPE double\n-# define IREGS \"d\"\n+# define IREG_SIZE 64\n #else\n-# ifndef IREGS\n-# error IREGS not defined\n+# ifndef IREG_SIZE\n+# error IREG_SIZE not defined\n # endif\n #endif\n \n #ifndef OTYPE\n # define OTYPE long int\n+# ifdef __ILP32__\n+# define OREG_SIZE 32\n+# else\n+# define OREG_SIZE 64\n+# endif\n+#else\n+# ifndef OREG_SIZE\n+# error OREG_SIZE not defined\n+# endif\n #endif\n \n-#define OREGS \"x\"\n+#if IREG_SIZE == 32\n+# define IREGS \"s\"\n+#else\n+# define IREGS \"d\"\n+#endif\n+\n+#if OREG_SIZE == 32\n+# define OREGS \"w\"\n+#else\n+# define OREGS \"x\"\n+#endif\n \n #define __CONCATX(a,b) __CONCAT(a,b)\n \n@@ -44,6 +65,37 @@ __CONCATX(__,FUNC) (ITYPE x)\n {\n OTYPE result;\n ITYPE temp;\n+\n+#if IREG_SIZE == 64 && OREG_SIZE == 32\n+ if (__builtin_fabs (x) > INT32_MAX)\n+ {\n+ /* Converting large values to a 32 bit int may cause the frintx/fcvtza\n+\t sequence to set both FE_INVALID and FE_INEXACT. To avoid this\n+\t check the rounding mode and do a single instruction with the\n+\t appropriate rounding mode. */\n+\n+ switch (get_rounding_mode ())\n+\t{\n+\tcase FE_TONEAREST:\n+\t asm volatile (\"fcvtns\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n+\t\t\t: \"=r\" (result) : \"w\" (x));\n+\t break;\n+\tcase FE_UPWARD:\n+\t asm volatile (\"fcvtps\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n+\t\t\t: \"=r\" (result) : \"w\" (x));\n+\t break;\n+\tcase FE_DOWNWARD:\n+\t asm volatile (\"fcvtms\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n+\t\t\t: \"=r\" (result) : \"w\" (x));\n+\t break;\n+\tcase FE_TOWARDZERO:\n+\tdefault:\n+\t asm volatile (\"fcvtzs\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n+\t\t\t: \"=r\" (result) : \"w\" (x));\n+\t}\n+ return result;\n+ }\n+#endif\n asm ( \"frintx\" \"\\t%\" IREGS \"1, %\" IREGS \"2\\n\\t\"\n \"fcvtzs\" \"\\t%\" OREGS \"0, %\" IREGS \"1\"\n : \"=r\" (result), \"=w\" (temp) : \"w\" (x) );\ndiff --git a/sysdeps/aarch64/fpu/s_lrintf.c b/sysdeps/aarch64/fpu/s_lrintf.c\nindex a995e4b..2e73271 100644\n--- a/sysdeps/aarch64/fpu/s_lrintf.c\n+++ b/sysdeps/aarch64/fpu/s_lrintf.c\n@@ -18,5 +18,5 @@\n \n #define FUNC lrintf\n #define ITYPE float\n-#define IREGS \"s\"\n+#define IREG_SIZE 32\n #include \ndiff --git a/sysdeps/aarch64/fpu/s_lround.c b/sysdeps/aarch64/fpu/s_lround.c\nindex 9be9e7f..1f77d82 100644\n--- a/sysdeps/aarch64/fpu/s_lround.c\n+++ b/sysdeps/aarch64/fpu/s_lround.c\n@@ -24,18 +24,37 @@\n \n #ifndef ITYPE\n # define ITYPE double\n-# define IREGS \"d\"\n+# define IREG_SIZE 64\n #else\n-# ifndef IREGS\n-# error IREGS not defined\n+# ifndef IREG_SIZE\n+# error IREG_SIZE not defined\n # endif\n #endif\n \n #ifndef OTYPE\n # define OTYPE long int\n+# ifdef __ILP32__\n+# define OREG_SIZE 32\n+# else\n+# define OREG_SIZE 64\n+# endif\n+#else\n+# ifndef OREG_SIZE\n+# error OREG_SIZE not defined\n+# endif\n+#endif\n+\n+#if IREG_SIZE == 32\n+# define IREGS \"s\"\n+#else\n+# define IREGS \"d\"\n #endif\n \n-#define OREGS \"x\"\n+#if OREG_SIZE == 32\n+# define OREGS \"w\"\n+#else\n+# define OREGS \"x\"\n+#endif\n \n #define __CONCATX(a,b) __CONCAT(a,b)\n \ndiff --git a/sysdeps/aarch64/fpu/s_lroundf.c b/sysdeps/aarch64/fpu/s_lroundf.c\nindex 4a066d4..b30ddb6 100644\n--- a/sysdeps/aarch64/fpu/s_lroundf.c\n+++ b/sysdeps/aarch64/fpu/s_lroundf.c\n@@ -18,5 +18,5 @@\n \n #define FUNC lroundf\n #define ITYPE float\n-#define IREGS \"s\"\n+#define IREG_SIZE 32\n #include \n","prefixes":["AArch64"]}