{"id":807294,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807294/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/patch/1504038918-49254-2-git-send-email-f.fainelli@gmail.com/","project":{"id":7,"url":"http://patchwork.ozlabs.org/api/1.2/projects/7/?format=json","name":"Linux network development","link_name":"netdev","list_id":"netdev.vger.kernel.org","list_email":"netdev@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1504038918-49254-2-git-send-email-f.fainelli@gmail.com>","list_archive_url":null,"date":"2017-08-29T20:35:15","name":"[net-next,v2,1/4] net: systemport: Use correct I/O accessors","commit_ref":null,"pull_url":null,"state":"accepted","archived":true,"hash":"85571debdb86d0c256fde64591065b7edd7ec89a","submitter":{"id":2800,"url":"http://patchwork.ozlabs.org/api/1.2/people/2800/?format=json","name":"Florian Fainelli","email":"f.fainelli@gmail.com"},"delegate":{"id":34,"url":"http://patchwork.ozlabs.org/api/1.2/users/34/?format=json","username":"davem","first_name":"David","last_name":"Miller","email":"davem@davemloft.net"},"mbox":"http://patchwork.ozlabs.org/project/netdev/patch/1504038918-49254-2-git-send-email-f.fainelli@gmail.com/mbox/","series":[{"id":470,"url":"http://patchwork.ozlabs.org/api/1.2/series/470/?format=json","web_url":"http://patchwork.ozlabs.org/project/netdev/list/?series=470","date":"2017-08-29T20:35:14","name":"Endian fixes for SYSTEMPORT/SF2/MDIO","version":2,"mbox":"http://patchwork.ozlabs.org/series/470/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807294/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807294/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tTue, 29 Aug 2017 13:41:15 -0700 (PDT)","From":"Florian Fainelli ","To":"netdev@vger.kernel.org","Cc":"davem@davemloft.net, opendmb@gmail.com, andrew@lunn.ch,\n\tvivien.didelot@savoirfairelinux.com,\n\tFlorian Fainelli ","Subject":"[PATCH net-next v2 1/4] net: systemport: Use correct I/O accessors","Date":"Tue, 29 Aug 2017 13:35:15 -0700","Message-Id":"<1504038918-49254-2-git-send-email-f.fainelli@gmail.com>","X-Mailer":"git-send-email 1.9.1","In-Reply-To":"<1504038918-49254-1-git-send-email-f.fainelli@gmail.com>","References":"<1504038918-49254-1-git-send-email-f.fainelli@gmail.com>","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"netdev@vger.kernel.org"},"content":"The SYSTEMPORT driver currently uses __raw_{read,write}l which means\nnative I/O endian. This works correctly for an ARM LE kernel (default)\nbut fails miserably on an ARM BE (BE8) kernel where registers are kept\nlittle endian, so replace uses with {read,write}l_relaxed here which is\nwhat we want because this is all performance sensitive code.\n\nSigned-off-by: Florian Fainelli \n---\n drivers/net/ethernet/broadcom/bcmsysport.c | 12 ++++++------\n 1 file changed, 6 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c b/drivers/net/ethernet/broadcom/bcmsysport.c\nindex b3a21418f511..a7e84292af50 100644\n--- a/drivers/net/ethernet/broadcom/bcmsysport.c\n+++ b/drivers/net/ethernet/broadcom/bcmsysport.c\n@@ -32,13 +32,13 @@\n #define BCM_SYSPORT_IO_MACRO(name, offset) \\\n static inline u32 name##_readl(struct bcm_sysport_priv *priv, u32 off)\t\\\n {\t\t\t\t\t\t\t\t\t\\\n-\tu32 reg = __raw_readl(priv->base + offset + off);\t\t\\\n+\tu32 reg = readl_relaxed(priv->base + offset + off);\t\t\\\n \treturn reg;\t\t\t\t\t\t\t\\\n }\t\t\t\t\t\t\t\t\t\\\n static inline void name##_writel(struct bcm_sysport_priv *priv,\t\t\\\n \t\t\t\t u32 val, u32 off)\t\t\t\\\n {\t\t\t\t\t\t\t\t\t\\\n-\t__raw_writel(val, priv->base + offset + off);\t\t\t\\\n+\twritel_relaxed(val, priv->base + offset + off);\t\t\t\\\n }\t\t\t\t\t\t\t\t\t\\\n \n BCM_SYSPORT_IO_MACRO(intrl2_0, SYS_PORT_INTRL2_0_OFFSET);\n@@ -59,14 +59,14 @@ static inline u32 rdma_readl(struct bcm_sysport_priv *priv, u32 off)\n {\n \tif (priv->is_lite && off >= RDMA_STATUS)\n \t\toff += 4;\n-\treturn __raw_readl(priv->base + SYS_PORT_RDMA_OFFSET + off);\n+\treturn readl_relaxed(priv->base + SYS_PORT_RDMA_OFFSET + off);\n }\n \n static inline void rdma_writel(struct bcm_sysport_priv *priv, u32 val, u32 off)\n {\n \tif (priv->is_lite && off >= RDMA_STATUS)\n \t\toff += 4;\n-\t__raw_writel(val, priv->base + SYS_PORT_RDMA_OFFSET + off);\n+\twritel_relaxed(val, priv->base + SYS_PORT_RDMA_OFFSET + off);\n }\n \n static inline u32 tdma_control_bit(struct bcm_sysport_priv *priv, u32 bit)\n@@ -110,10 +110,10 @@ static inline void dma_desc_set_addr(struct bcm_sysport_priv *priv,\n \t\t\t\t dma_addr_t addr)\n {\n #ifdef CONFIG_PHYS_ADDR_T_64BIT\n-\t__raw_writel(upper_32_bits(addr) & DESC_ADDR_HI_MASK,\n+\twritel_relaxed(upper_32_bits(addr) & DESC_ADDR_HI_MASK,\n \t\t d + DESC_ADDR_HI_STATUS_LEN);\n #endif\n-\t__raw_writel(lower_32_bits(addr), d + DESC_ADDR_LO);\n+\twritel_relaxed(lower_32_bits(addr), d + DESC_ADDR_LO);\n }\n \n static inline void tdma_port_write_desc_addr(struct bcm_sysport_priv *priv,\n","prefixes":["net-next","v2","1/4"]}