{"id":807245,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807245/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170829192148.19519.80519.stgit@localhost6.localdomain6/","project":{"id":46,"url":"http://patchwork.ozlabs.org/api/1.2/projects/46/?format=json","name":"Intel Wired Ethernet development","link_name":"intel-wired-lan","list_id":"intel-wired-lan.osuosl.org","list_email":"intel-wired-lan@osuosl.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170829192148.19519.80519.stgit@localhost6.localdomain6>","list_archive_url":null,"date":"2017-08-29T19:21:48","name":"ixgbe: split Tx/Rx ring clearing for ethtool loopback test","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"38dce2fd3307ff9d6fe41768d9a0aea1b249a7f4","submitter":{"id":1670,"url":"http://patchwork.ozlabs.org/api/1.2/people/1670/?format=json","name":"Tantilov, Emil S","email":"emil.s.tantilov@intel.com"},"delegate":{"id":68,"url":"http://patchwork.ozlabs.org/api/1.2/users/68/?format=json","username":"jtkirshe","first_name":"Jeff","last_name":"Kirsher","email":"jeffrey.t.kirsher@intel.com"},"mbox":"http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20170829192148.19519.80519.stgit@localhost6.localdomain6/mbox/","series":[{"id":447,"url":"http://patchwork.ozlabs.org/api/1.2/series/447/?format=json","web_url":"http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=447","date":"2017-08-29T19:21:48","name":"ixgbe: split Tx/Rx ring clearing for ethtool loopback test","version":1,"mbox":"http://patchwork.ozlabs.org/series/447/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807245/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807245/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","intel-wired-lan@lists.osuosl.org"],"Authentication-Results":"ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=)","Received":["from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhdmH64KGz9s76\n\tfor ;\n\tWed, 30 Aug 2017 05:21:35 +1000 (AEST)","from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 267D82FDD4;\n\tTue, 29 Aug 2017 19:21:33 +0000 (UTC)","from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 6-T+bQ+KIqL2; Tue, 29 Aug 2017 19:21:31 +0000 (UTC)","from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 4218E2FB26;\n\tTue, 29 Aug 2017 19:21:31 +0000 (UTC)","from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id F04A81C08E3\n\tfor ;\n\tTue, 29 Aug 2017 19:21:29 +0000 (UTC)","from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id E0C09872C2\n\tfor ;\n\tTue, 29 Aug 2017 19:21:29 +0000 (UTC)","from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ic6b4MP718HC for ;\n\tTue, 29 Aug 2017 19:21:29 +0000 (UTC)","from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 44DDD872BB\n\tfor ;\n\tTue, 29 Aug 2017 19:21:29 +0000 (UTC)","from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Aug 2017 12:21:28 -0700","from estantil-desk3.jf.intel.com (HELO localhost6.localdomain6)\n\t([134.134.177.78])\n\tby fmsmga004.fm.intel.com with ESMTP; 29 Aug 2017 12:21:28 -0700"],"X-Virus-Scanned":["amavisd-new at osuosl.org","amavisd-new at osuosl.org"],"X-Greylist":"domain auto-whitelisted by SQLgrey-1.7.6","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.41,445,1498546800\"; d=\"scan'208\";a=\"305822761\"","From":"Emil Tantilov ","To":"intel-wired-lan@lists.osuosl.org","Date":"Tue, 29 Aug 2017 12:21:48 -0700","Message-ID":"<20170829192148.19519.80519.stgit@localhost6.localdomain6>","User-Agent":"StGit/0.17.1-17-ge4e0","MIME-Version":"1.0","Subject":"[Intel-wired-lan] [PATCH] ixgbe: split Tx/Rx ring clearing for\n\tethtool loopback test","X-BeenThere":"intel-wired-lan@osuosl.org","X-Mailman-Version":"2.1.18-1","Precedence":"list","List-Id":"Intel Wired Ethernet Linux Kernel Driver Development\n\t","List-Unsubscribe":", \n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":", \n\t","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Errors-To":"intel-wired-lan-bounces@osuosl.org","Sender":"\"Intel-wired-lan\" "},"content":"Commit: fed21bcee7a5\n(\"ixgbe: Don't bother clearing buffer memory for descriptor rings)\n\nexposed some issues with the logic in the current implementation of\nixgbe_clean_test_rings() that are being addressed in this patch:\n\n- Split the clearing of the Tx and Rx rings in separate loops. Previously\nboth Tx and Rx rings were cleared in a rx_desc->wb.upper.length based\nloop which could lead to issues if for w/e reason packets were received\noutside of the frames transmitted for the loopback test.\n\n- Add check for IXGBE_TXD_STAT_DD to avoid clearing the rings if the\ntransmits have not comlpeted by the time we enter ixgbe_clean_test_rings()\n\n- Exit early on ixgbe_check_lbtest_frame() failure.\n\nThis change fixes a crash during ethtool diagnostic (ethtool -t).\n\nSigned-off-by: Emil Tantilov \n---\n drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 53 ++++++++++++++--------\n 1 file changed, 34 insertions(+), 19 deletions(-)","diff":"diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c\nindex 18f5576..108db29 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c\n@@ -1918,8 +1918,6 @@ static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,\n \t\t\t\t unsigned int size)\n {\n \tunion ixgbe_adv_rx_desc *rx_desc;\n-\tstruct ixgbe_rx_buffer *rx_buffer;\n-\tstruct ixgbe_tx_buffer *tx_buffer;\n \tu16 rx_ntc, tx_ntc, count = 0;\n \n \t/* initialize next to clean and descriptor values */\n@@ -1927,7 +1925,38 @@ static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,\n \ttx_ntc = tx_ring->next_to_clean;\n \trx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);\n \n+\twhile (tx_ntc != tx_ring->next_to_use) {\n+\t\tunion ixgbe_adv_tx_desc *tx_desc;\n+\t\tstruct ixgbe_tx_buffer *tx_buffer;\n+\n+\t\ttx_desc = IXGBE_TX_DESC(tx_ring, tx_ntc);\n+\n+\t\t/* if DD is not set transmit has not completed */\n+\t\tif (!(tx_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))\n+\t\t\treturn count;\n+\n+\t\t/* unmap buffer on Tx side */\n+\t\ttx_buffer = &tx_ring->tx_buffer_info[tx_ntc];\n+\n+\t\t/* Free all the Tx ring sk_buffs */\n+\t\tdev_kfree_skb_any(tx_buffer->skb);\n+\n+\t\t/* unmap skb header data */\n+\t\tdma_unmap_single(tx_ring->dev,\n+\t\t\t\t dma_unmap_addr(tx_buffer, dma),\n+\t\t\t\t dma_unmap_len(tx_buffer, len),\n+\t\t\t\t DMA_TO_DEVICE);\n+\t\tdma_unmap_len_set(tx_buffer, len, 0);\n+\n+\t\t/* increment Tx next to clean counter */\n+\t\ttx_ntc++;\n+\t\tif (tx_ntc == tx_ring->count)\n+\t\t\ttx_ntc = 0;\n+\t}\n+\n \twhile (rx_desc->wb.upper.length) {\n+\t\tstruct ixgbe_rx_buffer *rx_buffer;\n+\n \t\t/* check Rx buffer */\n \t\trx_buffer = &rx_ring->rx_buffer_info[rx_ntc];\n \n@@ -1940,6 +1969,8 @@ static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,\n \t\t/* verify contents of skb */\n \t\tif (ixgbe_check_lbtest_frame(rx_buffer, size))\n \t\t\tcount++;\n+\t\telse\n+\t\t\tbreak;\n \n \t\t/* sync Rx buffer for device write */\n \t\tdma_sync_single_for_device(rx_ring->dev,\n@@ -1947,26 +1978,10 @@ static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,\n \t\t\t\t\t ixgbe_rx_bufsz(rx_ring),\n \t\t\t\t\t DMA_FROM_DEVICE);\n \n-\t\t/* unmap buffer on Tx side */\n-\t\ttx_buffer = &tx_ring->tx_buffer_info[tx_ntc];\n-\n-\t\t/* Free all the Tx ring sk_buffs */\n-\t\tdev_kfree_skb_any(tx_buffer->skb);\n-\n-\t\t/* unmap skb header data */\n-\t\tdma_unmap_single(tx_ring->dev,\n-\t\t\t\t dma_unmap_addr(tx_buffer, dma),\n-\t\t\t\t dma_unmap_len(tx_buffer, len),\n-\t\t\t\t DMA_TO_DEVICE);\n-\t\tdma_unmap_len_set(tx_buffer, len, 0);\n-\n-\t\t/* increment Rx/Tx next to clean counters */\n+\t\t/* increment Rx next to clean counter */\n \t\trx_ntc++;\n \t\tif (rx_ntc == rx_ring->count)\n \t\t\trx_ntc = 0;\n-\t\ttx_ntc++;\n-\t\tif (tx_ntc == tx_ring->count)\n-\t\t\ttx_ntc = 0;\n \n \t\t/* fetch next descriptor */\n \t\trx_desc = IXGBE_RX_DESC(rx_ring, rx_ntc);\n","prefixes":[]}