{"id":807195,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807195/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829172326.1131-1-bobby.prani@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170829172326.1131-1-bobby.prani@gmail.com>","list_archive_url":null,"date":"2017-08-29T17:23:26","name":"tcg/softmmu: Increase size of TLB caches","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"35b6d01f4d6ab24968f85193d138feda91732d28","submitter":{"id":64653,"url":"http://patchwork.ozlabs.org/api/1.2/people/64653/?format=json","name":"Pranith Kumar","email":"bobby.prani@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20170829172326.1131-1-bobby.prani@gmail.com/mbox/","series":[{"id":420,"url":"http://patchwork.ozlabs.org/api/1.2/series/420/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=420","date":"2017-08-29T17:23:26","name":"tcg/softmmu: Increase size of TLB caches","version":1,"mbox":"http://patchwork.ozlabs.org/series/420/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807195/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807195/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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I went\nover a few architectures to see if increasing it is problematic. Only\narmv6 seems to have a limitation that only 8 bits can be used for\nindexing these entries. For other architectures, the number of TLB\nentries is increased to a 4K-sized cache. The patch also doubles the\nnumber of victim TLB entries.\n\nSome statistics collected from a build benchmark for various cache\nsizes is listed below:\n\n| TLB bits\\vTLB entires | 8 | 16 | 32 |\n| 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) |\n| 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |\n| 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |\n\nThe best combination for this workload came out to be 12 bits for the\nTLB and a 16 entry vTLB cache.\n\nSigned-off-by: Pranith Kumar \n---\n include/exec/cpu-defs.h | 6 +++---\n tcg/aarch64/tcg-target.h | 1 +\n tcg/arm/tcg-target.h | 1 +\n tcg/i386/tcg-target.h | 2 ++\n tcg/ia64/tcg-target.h | 1 +\n tcg/mips/tcg-target.h | 2 ++\n tcg/ppc/tcg-target.h | 1 +\n tcg/s390/tcg-target.h | 1 +\n tcg/sparc/tcg-target.h | 1 +\n tcg/tci/tcg-target.h | 1 +\n 10 files changed, 14 insertions(+), 3 deletions(-)","diff":"diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h\nindex bc8e7f848d..1957e3f32c 100644\n--- a/include/exec/cpu-defs.h\n+++ b/include/exec/cpu-defs.h\n@@ -57,8 +57,8 @@ typedef uint64_t target_ulong;\n #endif\n \n #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)\n-/* use a fully associative victim tlb of 8 entries */\n-#define CPU_VTLB_SIZE 8\n+/* use a fully associative victim tlb of 16 entries */\n+#define CPU_VTLB_SIZE 16\n \n #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32\n #define CPU_TLB_ENTRY_BITS 4\n@@ -89,7 +89,7 @@ typedef uint64_t target_ulong;\n * of tlb_table inside env (which is non-trivial but not huge).\n */\n #define CPU_TLB_BITS \\\n- MIN(8, \\\n+ MIN(MIN(12, TCG_TARGET_TLB_MAX_INDEX_BITS), \\\n TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \\\n (NB_MMU_MODES <= 1 ? 0 : \\\n NB_MMU_MODES <= 2 ? 1 : \\\ndiff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h\nindex b41a248bee..9f4558cd83 100644\n--- a/tcg/aarch64/tcg-target.h\n+++ b/tcg/aarch64/tcg-target.h\n@@ -15,6 +15,7 @@\n \n #define TCG_TARGET_INSN_UNIT_SIZE 4\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n #undef TCG_TARGET_STACK_GROWSUP\n \n typedef enum {\ndiff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h\nindex a38be15a39..ebe27991f3 100644\n--- a/tcg/arm/tcg-target.h\n+++ b/tcg/arm/tcg-target.h\n@@ -60,6 +60,7 @@ extern int arm_arch;\n #undef TCG_TARGET_STACK_GROWSUP\n #define TCG_TARGET_INSN_UNIT_SIZE 4\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 8\n \n typedef enum {\n TCG_REG_R0 = 0,\ndiff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h\nindex 73a15f7e80..5279af6eb1 100644\n--- a/tcg/i386/tcg-target.h\n+++ b/tcg/i386/tcg-target.h\n@@ -162,6 +162,8 @@ extern bool have_popcnt;\n # define TCG_AREG0 TCG_REG_EBP\n #endif\n \n+#define TCG_TARGET_TLB_MAX_INDEX_BITS (32 - CPU_TLB_ENTRY_BITS)\n+\n static inline void flush_icache_range(uintptr_t start, uintptr_t stop)\n {\n }\ndiff --git a/tcg/ia64/tcg-target.h b/tcg/ia64/tcg-target.h\nindex 8f475fe742..35878e20c7 100644\n--- a/tcg/ia64/tcg-target.h\n+++ b/tcg/ia64/tcg-target.h\n@@ -28,6 +28,7 @@\n \n #define TCG_TARGET_INSN_UNIT_SIZE 16\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 21\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n \n typedef struct {\n uint64_t lo __attribute__((aligned(16)));\ndiff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h\nindex e9558d15bc..1b60e53169 100644\n--- a/tcg/mips/tcg-target.h\n+++ b/tcg/mips/tcg-target.h\n@@ -39,6 +39,8 @@\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16\n #define TCG_TARGET_NB_REGS 32\n \n+#define TCG_TARGET_TLB_MAX_INDEX_BITS (16 - CPU_TLB_ENTRY_BITS)\n+\n typedef enum {\n TCG_REG_ZERO = 0,\n TCG_REG_AT,\ndiff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h\nindex 5a092b038a..82e10c9471 100644\n--- a/tcg/ppc/tcg-target.h\n+++ b/tcg/ppc/tcg-target.h\n@@ -34,6 +34,7 @@\n #define TCG_TARGET_NB_REGS 32\n #define TCG_TARGET_INSN_UNIT_SIZE 4\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n \n typedef enum {\n TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,\ndiff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h\nindex dc0e59193c..57f0e22532 100644\n--- a/tcg/s390/tcg-target.h\n+++ b/tcg/s390/tcg-target.h\n@@ -27,6 +27,7 @@\n \n #define TCG_TARGET_INSN_UNIT_SIZE 2\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 19\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n \n typedef enum TCGReg {\n TCG_REG_R0 = 0,\ndiff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h\nindex 4515c9ab48..378d218923 100644\n--- a/tcg/sparc/tcg-target.h\n+++ b/tcg/sparc/tcg-target.h\n@@ -29,6 +29,7 @@\n \n #define TCG_TARGET_INSN_UNIT_SIZE 4\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 12\n #define TCG_TARGET_NB_REGS 32\n \n typedef enum {\ndiff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h\nindex 06963288dc..bb36e8197d 100644\n--- a/tcg/tci/tcg-target.h\n+++ b/tcg/tci/tcg-target.h\n@@ -43,6 +43,7 @@\n #define TCG_TARGET_INTERPRETER 1\n #define TCG_TARGET_INSN_UNIT_SIZE 1\n #define TCG_TARGET_TLB_DISPLACEMENT_BITS 32\n+#define TCG_TARGET_TLB_MAX_INDEX_BITS 32\n \n #if UINTPTR_MAX == UINT32_MAX\n # define TCG_TARGET_REG_BITS 32\n","prefixes":[]}