{"id":807012,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807012/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1503999271-15712-6-git-send-email-daniel.lezcano@linaro.org/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.2/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503999271-15712-6-git-send-email-daniel.lezcano@linaro.org>","list_archive_url":null,"date":"2017-08-29T09:34:24","name":"[6/9] devicetree: bindings: Deprecate property, update example","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"c8ab186c8e465f3f83923cfd24957177e9e219c6","submitter":{"id":13265,"url":"http://patchwork.ozlabs.org/api/1.2/people/13265/?format=json","name":"Daniel Lezcano","email":"daniel.lezcano@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1503999271-15712-6-git-send-email-daniel.lezcano@linaro.org/mbox/","series":[{"id":334,"url":"http://patchwork.ozlabs.org/api/1.2/series/334/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=334","date":"2017-08-29T09:34:19","name":"[1/9] dt-bindings: timer: Add nxp tpm timer binding doc","version":1,"mbox":"http://patchwork.ozlabs.org/series/334/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807012/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807012/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"L+CzjkQK\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhNmm707sz9t38\n\tfor ;\n\tTue, 29 Aug 2017 19:36:08 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752136AbdH2JgG (ORCPT\n\t);\n\tTue, 29 Aug 2017 05:36:06 -0400","from mail-wm0-f41.google.com ([74.125.82.41]:34179 \"EHLO\n\tmail-wm0-f41.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751250AbdH2JgD (ORCPT\n\t); Tue, 29 Aug 2017 05:36:03 -0400","by mail-wm0-f41.google.com with SMTP id f13so18676655wme.1\n\tfor ;\n\tTue, 29 Aug 2017 02:36:03 -0700 (PDT)","from localhost.localdomain\n\t([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf])\n\tby smtp.gmail.com with ESMTPSA id\n\tr18sm3621775wrc.44.2017.08.29.02.36.01\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 29 Aug 2017 02:36:02 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=Hw8SPcc7bdppz8KvYUFfFEcjTWQWrd10aHA8KkB1/hM=;\n\tb=L+CzjkQK4etCafApqAtlI6CDwT9/xDlQV+zbqRZyqLXrvBf5l/Dcs3IiroTEo+L8Ro\n\tUHUza4gRfYATL9OCRywdEO25oQSbXgNa+iwKsXhKpfnqOpo/Xe01NGM/hFGdiElMbLOV\n\tLl/zmJ2cv8VK6jssS69XOjRDzMK3jSLVcgwjs=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=Hw8SPcc7bdppz8KvYUFfFEcjTWQWrd10aHA8KkB1/hM=;\n\tb=erB6ZNjZ1xWVenVvcmXxHDV8FrjshlSFB9BWT1nLvdA8UN9/D8FecFdrjkrXa5pba3\n\tLGGZakO85kaxMKzbSKaa63F+IKT9UbYLk0i+BJtpYx9rVq3yCIPFOgijr+JIyoDu7kmq\n\t2wKqy++B5kMDI+V/xh20CDE3s1mFz/uhhqHrG1PBwviygOMT2CdNAm+2Yl1Myg/x9z3M\n\tazm0w5CiEWVrLMJg9lb5kRAyAMdArwYv8Zzs/J+t6DP3fAnCPurgX+tRyATBlRKmSfTc\n\tJRgyJK7gpaM9rKRDL1xFNZ8RS254kO81E11C5RiNexdQ/5y7sbZ8OKPRXAWnb40jcG17\n\tRmeg==","X-Gm-Message-State":"AHYfb5jwjWQYpj/PaG1gj5YezFOx5q9u1IyEsUA6bjYrHwhpG2v8qlUC\n\taxFD6nW7YYZ4u9wz","X-Received":"by 10.28.105.24 with SMTP id e24mr1099111wmc.47.1503999362509;\n\tTue, 29 Aug 2017 02:36:02 -0700 (PDT)","From":"Daniel Lezcano ","To":"tglx@linutronix.de","Cc":"linux-kernel@vger.kernel.org, Magnus Damm , \n\tGeert Uytterhoeven ,\n\tLaurent Pinchart ,\n\tRob Herring , Rob Herring ,\n\tMark Rutland ,\n\tdevicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED\n\tDEVICE TREE BINDINGS)","Subject":"[PATCH 6/9] devicetree: bindings: Deprecate property, update example","Date":"Tue, 29 Aug 2017 11:34:24 +0200","Message-Id":"<1503999271-15712-6-git-send-email-daniel.lezcano@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org>","References":"<20170829093354.GA2572@mai>\n\t<1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"From: Magnus Damm \n\nDeprecate \"renesas,channels-mask\" and update the r8a7790 CMT example.\n\nSigned-off-by: Magnus Damm \nAcked-by: Geert Uytterhoeven \nAcked-by: Laurent Pinchart \nAcked-by: Rob Herring \nSigned-off-by: Daniel Lezcano \n---\n .../devicetree/bindings/timer/renesas,cmt.txt | 24 +++++++++++++++-------\n 1 file changed, 17 insertions(+), 7 deletions(-)","diff":"diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt\nindex e81e0d2..8fb7c93 100644\n--- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt\n+++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt\n@@ -60,21 +60,31 @@ Required Properties:\n in clock-names.\n - clock-names: must contain \"fck\" for the functional clock.\n \n- - renesas,channels-mask: bitmask of the available channels.\n+ - renesas,channels-mask: , information kept in device driver.\n \n \n-Example: R8A7790 (R-Car H2) CMT0 node\n-\n-\tCMT0 on R8A7790 implements hardware channels 5 and 6 only and names\n-\tthem channels 0 and 1 in the documentation.\n+Example: R8A7790 (R-Car H2) CMT0 and CMT1 nodes\n \n \tcmt0: timer@ffca0000 {\n-\t\tcompatible = \"renesas,cmt-48-r8a7790\", \"renesas,cmt-48-gen2\";\n+\t\tcompatible = \"renesas,cmt0-r8a7790\", \"renesas,rcar-gen2-cmt0\";\n \t\treg = <0 0xffca0000 0 0x1004>;\n \t\tinterrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,\n \t\t\t <0 142 IRQ_TYPE_LEVEL_HIGH>;\n \t\tclocks = <&mstp1_clks R8A7790_CLK_CMT0>;\n \t\tclock-names = \"fck\";\n+\t};\n \n-\t\trenesas,channels-mask = <0x60>;\n+\tcmt1: timer@e6130000 {\n+\t\tcompatible = \"renesas,cmt1-r8a7790\", \"renesas,rcar-gen2-cmt1\";\n+\t\treg = <0 0xe6130000 0 0x1004>;\n+\t\tinterrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t <0 121 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t <0 122 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t <0 123 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t <0 124 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t <0 125 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t <0 126 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t <0 127 IRQ_TYPE_LEVEL_HIGH>;\n+\t\tclocks = <&mstp3_clks R8A7790_CLK_CMT1>;\n+\t\tclock-names = \"fck\";\n \t};\n","prefixes":["6/9"]}