{"id":807011,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807011/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.2/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org>","list_archive_url":null,"date":"2017-08-29T09:34:19","name":"[1/9] dt-bindings: timer: Add nxp tpm timer binding doc","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"fcb263e29dd821765eb0f72cce770674ea819810","submitter":{"id":13265,"url":"http://patchwork.ozlabs.org/api/1.2/people/13265/?format=json","name":"Daniel Lezcano","email":"daniel.lezcano@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org/mbox/","series":[{"id":334,"url":"http://patchwork.ozlabs.org/api/1.2/series/334/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=334","date":"2017-08-29T09:34:19","name":"[1/9] dt-bindings: timer: Add nxp tpm timer binding doc","version":1,"mbox":"http://patchwork.ozlabs.org/series/334/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807011/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807011/checks/","tags":{},"related":[],"headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"YfqzHefI\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhNmQ0rXDz9t33\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 19:35:50 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751355AbdH2Jfs (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 29 Aug 2017 05:35:48 -0400","from mail-wm0-f48.google.com ([74.125.82.48]:33392 \"EHLO\n\tmail-wm0-f48.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751227AbdH2Jfr (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 29 Aug 2017 05:35:47 -0400","by mail-wm0-f48.google.com with SMTP id b14so18796792wme.0\n\tfor <devicetree@vger.kernel.org>;\n\tTue, 29 Aug 2017 02:35:47 -0700 (PDT)","from localhost.localdomain\n\t([2a01:e35:879a:6cd0:cc22:a7ba:e8a7:7caf])\n\tby smtp.gmail.com with ESMTPSA id\n\tr18sm3621775wrc.44.2017.08.29.02.35.45\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 29 Aug 2017 02:35:45 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=OhzhjGoVjNsRobb84pBEAw6JcQXRvH0PdGogBMKgdPc=;\n\tb=YfqzHefIteA/tsBkVY2vL91PnjqLdaz4B5181dSdPjhxwffgdlyvTKTCunNh25kJFC\n\tLKwzWogzZMg6pHM2OJ0q2t7pYsiHoiT7IYq7aAWsp2krpCKC23zem/HHd+kjmHp6QEQy\n\ts6pGXCuk5zX7wSHYuXBOvpL6YY93c4PYV5nwo=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=OhzhjGoVjNsRobb84pBEAw6JcQXRvH0PdGogBMKgdPc=;\n\tb=l+zRv4fpQfzoAuaBvNQ8Y9fBje6+cgFdKKGEOZuiwVkIupz6fLbLayPKRf44Mlju2d\n\tFHMltbW2JuSPBmFcDILAoNDlA+kO2RGWGKT0xhTWjTt617FXARywX/0bfvXBIeqRTLWQ\n\tre2JsULBHvTdWjKx0yMytKl+6biB6CzseI9ZdWu2sd2cOCo8UZB+7eQ+i6u/Vb0qxUU4\n\tHOHo695xzv0FD6dOsZRLtEMRScknDydbASlzfErcEOu+BKFHkbps1UonBn9q5mFRYNE8\n\tgAY2VewtXKQ3ljWUWIkYY5ab6Ort4kNBFctxcinU0qWdS2eqb2dniBhWCU+UiAC74mBv\n\tszww==","X-Gm-Message-State":"AHYfb5ju9xjT8CctswU1lQlE5GeS6oxTAiJLodTuZC+65DEoge5Z3L6z\n\tQkY2sERJbw/g6lr6Z660lw==","X-Received":"by 10.28.187.4 with SMTP id l4mr1915456wmf.168.1503999346620;\n\tTue, 29 Aug 2017 02:35:46 -0700 (PDT)","From":"Daniel Lezcano <daniel.lezcano@linaro.org>","To":"tglx@linutronix.de","Cc":"linux-kernel@vger.kernel.org, Dong Aisheng <aisheng.dong@nxp.com>,\n\tMark Rutland <mark.rutland@arm.com>,\n\tdevicetree@vger.kernel.org, Shawn Guo <shawnguo@kernel.org>,\n\tBai Ping <ping.bai@nxp.com>, Rob Herring <robh@kernel.org>,\n\tRob Herring <robh+dt@kernel.org>","Subject":"[PATCH 1/9] dt-bindings: timer: Add nxp tpm timer binding doc","Date":"Tue, 29 Aug 2017 11:34:19 +0200","Message-Id":"<1503999271-15712-1-git-send-email-daniel.lezcano@linaro.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<20170829093354.GA2572@mai>","References":"<20170829093354.GA2572@mai>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"From: Dong Aisheng <aisheng.dong@nxp.com>\n\nAdding NXP Low Power Timer/Pulse Width Modulation Module (TPM)\nbinding doc.\n\nCc: Mark Rutland <mark.rutland@arm.com>\nCc: devicetree@vger.kernel.org\nCc: Daniel Lezcano <daniel.lezcano@linaro.org>\nCc: Thomas Gleixner <tglx@linutronix.de>\nCc: Shawn Guo <shawnguo@kernel.org>\nCc: Bai Ping <ping.bai@nxp.com>\nAcked-by: Rob Herring <robh@kernel.org>\nSigned-off-by: Dong Aisheng <aisheng.dong@nxp.com>\nSigned-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>\n---\n .../devicetree/bindings/timer/nxp,tpm-timer.txt    | 28 ++++++++++++++++++++++\n 1 file changed, 28 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt","diff":"diff --git a/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt\nnew file mode 100644\nindex 0000000..b4aa7dd\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/timer/nxp,tpm-timer.txt\n@@ -0,0 +1,28 @@\n+NXP Low Power Timer/Pulse Width Modulation Module (TPM)\n+\n+The Timer/PWM Module (TPM) supports input capture, output compare,\n+and the generation of PWM signals to control electric motor and power\n+management applications. The counter, compare and capture registers\n+are clocked by an asynchronous clock that can remain enabled in low\n+power modes. TPM can support global counter bus where one TPM drives\n+the counter bus for the others, provided bit width is the same.\n+\n+Required properties:\n+\n+- compatible :\tshould be \"fsl,imx7ulp-tpm\"\n+- reg :\t\tSpecifies base physical address and size of the register sets\n+\t\tfor the clock event device and clock source device.\n+- interrupts :\tShould be the clock event device interrupt.\n+- clocks :\tThe clocks provided by the SoC to drive the timer, must contain\n+\t\tan entry for each entry in clock-names.\n+- clock-names : Must include the following entries: \"igp\" and \"per\".\n+\n+Example:\n+tpm5: tpm@40260000 {\n+\tcompatible = \"fsl,imx7ulp-tpm\";\n+\treg = <0x40260000 0x1000>;\n+\tinterrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;\n+\tclocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,\n+\t\t <&clks IMX7ULP_CLK_LPTPM5>;\n+\tclock-names = \"ipg\", \"per\";\n+};\n","prefixes":["1/9"]}