{"id":807003,"url":"http://patchwork.ozlabs.org/api/1.2/patches/807003/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/b7bea49d254da89c43baf2ae02858bf67c59fd1d.1503995645.git.baolin.wang@spreadtrum.com/","project":{"id":37,"url":"http://patchwork.ozlabs.org/api/1.2/projects/37/?format=json","name":"Devicetree Bindings","link_name":"devicetree-bindings","list_id":"devicetree.vger.kernel.org","list_email":"devicetree@vger.kernel.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<b7bea49d254da89c43baf2ae02858bf67c59fd1d.1503995645.git.baolin.wang@spreadtrum.com>","list_archive_url":null,"date":"2017-08-29T08:47:16","name":"[v2,1/2] dt-bindings: dma: Add Spreadtrum SC9860 DMA controller","commit_ref":null,"pull_url":null,"state":"not-applicable","archived":true,"hash":"d98601cbc7d0ab9d5233469cc938f59f3b456387","submitter":{"id":71631,"url":"http://patchwork.ozlabs.org/api/1.2/people/71631/?format=json","name":"Baolin Wang","email":"baolin.wang@spreadtrum.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/devicetree-bindings/patch/b7bea49d254da89c43baf2ae02858bf67c59fd1d.1503995645.git.baolin.wang@spreadtrum.com/mbox/","series":[{"id":327,"url":"http://patchwork.ozlabs.org/api/1.2/series/327/?format=json","web_url":"http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=327","date":"2017-08-29T08:47:16","name":"[v2,1/2] dt-bindings: dma: Add Spreadtrum SC9860 DMA controller","version":2,"mbox":"http://patchwork.ozlabs.org/series/327/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/807003/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/807003/checks/","tags":{},"related":[],"headers":{"Return-Path":"<devicetree-owner@vger.kernel.org>","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xhMpf0qgxz9s4q\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 18:52:41 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751434AbdH2Iwk (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 29 Aug 2017 04:52:40 -0400","from sci-ig2.spreadtrum.com ([222.66.158.135]:24876 \"EHLO\n\tSHSQR01.spreadtrum.com\" rhost-flags-OK-FAIL-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750815AbdH2Iwj (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 29 Aug 2017 04:52:39 -0400","from ig2.spreadtrum.com (shmbx04.spreadtrum.com [10.0.1.214])\n\tby SHSQR01.spreadtrum.com with ESMTP id v7T8qHTM022591\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO);\n\tTue, 29 Aug 2017 16:52:17 +0800 (CST)\n\t(envelope-from Orson.Zhai@spreadtrum.com)","from SHCAS02.spreadtrum.com (10.0.1.202) by SHMBX04.spreadtrum.com\n\t(10.0.1.214) with Microsoft SMTP Server (TLS) id 15.0.847.32;\n\tTue, 29 Aug 2017 16:52:17 +0800","from localhost (10.0.73.143) by SHCAS02.spreadtrum.com (10.0.1.250)\n\twith Microsoft SMTP Server (TLS) id 15.0.847.32 via Frontend\n\tTransport; Tue, 29 Aug 2017 16:52:16 +0800"],"From":"Baolin Wang <baolin.wang@spreadtrum.com>","To":"<vinod.koul@intel.com>, <robh+dt@kernel.org>,\n\t<mark.rutland@arm.com>, <dan.j.williams@intel.com>","CC":"<dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>, <broonie@kernel.org>,\n\t<baolin.wang@linaro.org>, <baolin.wang@spreadtrum.com>","Subject":"[PATCH v2 1/2] dt-bindings: dma: Add Spreadtrum SC9860 DMA\n\tcontroller","Date":"Tue, 29 Aug 2017 16:47:16 +0800","Message-ID":"<b7bea49d254da89c43baf2ae02858bf67c59fd1d.1503995645.git.baolin.wang@spreadtrum.com>","X-Mailer":"git-send-email 2.12.2","MIME-Version":"1.0","Content-Type":"text/plain","X-MAIL":"SHSQR01.spreadtrum.com v7T8qHTM022591","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<devicetree.vger.kernel.org>","X-Mailing-List":"devicetree@vger.kernel.org"},"content":"This patch adds the binding documentation for Spreadtrum SC9860 DMA\ncontroller device.\n\nSigned-off-by: Baolin Wang <baolin.wang@spreadtrum.com>\nAcked-by: Rob Herring <robh@kernel.org>\n---\nChanges since v1:\n - Fix typos.\n---\n Documentation/devicetree/bindings/dma/sprd-dma.txt |   41 ++++++++++++++++++++\n 1 file changed, 41 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/dma/sprd-dma.txt","diff":"diff --git a/Documentation/devicetree/bindings/dma/sprd-dma.txt b/Documentation/devicetree/bindings/dma/sprd-dma.txt\nnew file mode 100644\nindex 0000000..7a10fea\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/dma/sprd-dma.txt\n@@ -0,0 +1,41 @@\n+* Spreadtrum DMA controller\n+\n+This binding follows the generic DMA bindings defined in dma.txt.\n+\n+Required properties:\n+- compatible: Should be \"sprd,sc9860-dma\".\n+- reg: Should contain DMA registers location and length.\n+- interrupts: Should contain one interrupt shared by all channel.\n+- #dma-cells: must be <1>. Used to represent the number of integer\n+\tcells in the dmas property of client device.\n+- #dma-channels : Number of DMA channels supported. Should be 32.\n+- clock-names: Should contain the clock of the DMA controller.\n+- clocks: Should contain a clock specifier for each entry in clock-names.\n+\n+Example:\n+\n+Controller:\n+apdma: dma-controller@20100000 {\n+\tcompatible = \"sprd,sc9860-dma\";\n+\treg = <0x20100000 0x4000>;\n+\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n+\t#dma-cells = <1>;\n+\t#dma-channels = <32>;\n+\tclock-names = \"enable\";\n+\tclocks = <&clk_ap_ahb_gates 5>;\n+};\n+\n+\n+Client:\n+DMA clients connected to the Spreadtrum DMA controller must use the format\n+described in the dma.txt file, using a two-cell specifier for each channel.\n+The two cells in order are:\n+1. A phandle pointing to the DMA controller.\n+2. The channel id.\n+\n+spi0: spi@70a00000{\n+\t...\n+\tdma-names = \"rx_chn\", \"tx_chn\";\n+\tdmas = <&apdma 11>, <&apdma 12>;\n+\t...\n+};\n","prefixes":["v2","1/2"]}