{"id":806927,"url":"http://patchwork.ozlabs.org/api/1.2/patches/806927/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/patch/20170829034147.GA15563@ibm-tiger.the-meissners.org/","project":{"id":17,"url":"http://patchwork.ozlabs.org/api/1.2/projects/17/?format=json","name":"GNU Compiler Collection","link_name":"gcc","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20170829034147.GA15563@ibm-tiger.the-meissners.org>","list_archive_url":null,"date":"2017-08-29T03:41:47","name":", PR target/82015, add PowerPC warning for unpack_vector_int128 with illegal 2nd argument","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"f915071f09075847673c4b7a39531bfee9440c99","submitter":{"id":4611,"url":"http://patchwork.ozlabs.org/api/1.2/people/4611/?format=json","name":"Michael Meissner","email":"meissner@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/gcc/patch/20170829034147.GA15563@ibm-tiger.the-meissners.org/mbox/","series":[{"id":293,"url":"http://patchwork.ozlabs.org/api/1.2/series/293/?format=json","web_url":"http://patchwork.ozlabs.org/project/gcc/list/?series=293","date":"2017-08-29T03:41:47","name":", PR target/82015, add PowerPC warning for unpack_vector_int128 with illegal 2nd argument","version":1,"mbox":"http://patchwork.ozlabs.org/series/293/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/806927/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/806927/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","mailing list gcc-patches@gcc.gnu.org"],"Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org\n\t(client-ip=209.132.180.131; helo=sourceware.org;\n\tenvelope-from=gcc-patches-return-461058-incoming=patchwork.ozlabs.org@gcc.gnu.org;\n\treceiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org\n\theader.b=\"Xq5Qs2rL\"; dkim-atps=neutral","sourceware.org; auth=none"],"Received":["from sourceware.org (server1.sourceware.org [209.132.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xhDwS66dBz9s7h\n\tfor ;\n\tTue, 29 Aug 2017 13:42:14 +1000 (AEST)","(qmail 90795 invoked by alias); 29 Aug 2017 03:42:05 -0000","(qmail 90769 invoked by uid 89); 29 Aug 2017 03:42:04 -0000","from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com)\n\t(148.163.156.1) by sourceware.org\n\t(qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP;\n\tTue, 29 Aug 2017 03:41:54 +0000","from pps.filterd (m0098396.ppops.net [127.0.0.1])\tby\n\tmx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7T3fiip141805\tfor ;\n\tMon, 28 Aug 2017 23:41:52 -0400","from e34.co.us.ibm.com (e34.co.us.ibm.com [32.97.110.152])\tby\n\tmx0a-001b2d01.pphosted.com with ESMTP id\n\t2cmvjevsdy-1\t(version=TLSv1.2 cipher=AES256-SHA bits=256\n\tverify=NOT)\tfor ;\n\tMon, 28 Aug 2017 23:41:51 -0400","from localhost\tby e34.co.us.ibm.com with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! 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The compiler\nput the 2nd argument into a register, but there wasn't a valid insn for this,\nand raised an insn not found message. GCC should warn about this illegal\nusage.\n\nThis patch adds such a warning. While I was mucking about with this built-in\nfunction, I fixed the constraints to allow the 64-bit integer for unpack result\nand pack inputs to be in the traditional Altivec registers as well as the\ntraditional floating point registers.\n\nI did a bootstrap of the compiler, and there were no regressions on a little\nendian power8 system. I verified that the new test is run. Can I apply this\npatch to the trunk?\n\nCan I apply the part of the patch from rs6000.c to the existing GCC 6/7\nbranches as well after a shake down period? The patch to rs6000.md is not\nappropriate for GCC 6 (since DImode can't go into Altivec registers). For GCC\n7, it would need to be modified to use the 'wi' constraint instead of 'wa',\nsince GCC 7 still had support for the -mno-upper-regs-di option to control\naccess to the traditional Altivec register.\n\n[gcc]\n2017-08-28 Michael Meissner \n\n\tPR target/82015\n\t* config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Insure\n\tthat the second argument of the built-in functions to unpack\n\t128-bit scalar types to 64-bit values is 0 or 1. Change to use a\n\tswitch statement instead a lot of if statements.\n\t* config/rs6000/rs6000.md (unpack, FMOVE128_VSX iterator):\n\tAllow 64-bit values to be in Altivec registers as well as\n\ttraditional floating point registers.\n\t(pack, FMOVE128_VSX iterator): Likewise.\n\n[gcc/testsuite]\n2017-08-28 Michael Meissner \n\n\tPR target/82015\n\t* gcc.target/powerpc/pr82015.c: New test.","diff":"Index: gcc/config/rs6000/rs6000.c\n===================================================================\n--- gcc/config/rs6000/rs6000.c\t(revision 251390)\n+++ gcc/config/rs6000/rs6000.c\t(working copy)\n@@ -14001,14 +14001,17 @@ rs6000_expand_binop_builtin (enum insn_c\n if (arg0 == error_mark_node || arg1 == error_mark_node)\n return const0_rtx;\n \n- if (icode == CODE_FOR_altivec_vcfux\n- || icode == CODE_FOR_altivec_vcfsx\n- || icode == CODE_FOR_altivec_vctsxs\n- || icode == CODE_FOR_altivec_vctuxs\n- || icode == CODE_FOR_altivec_vspltb\n- || icode == CODE_FOR_altivec_vsplth\n- || icode == CODE_FOR_altivec_vspltw)\n+ switch (icode)\n {\n+ default:\n+ break;\n+ case CODE_FOR_altivec_vcfux:\n+ case CODE_FOR_altivec_vcfsx:\n+ case CODE_FOR_altivec_vctsxs:\n+ case CODE_FOR_altivec_vctuxs:\n+ case CODE_FOR_altivec_vspltb:\n+ case CODE_FOR_altivec_vsplth:\n+ case CODE_FOR_altivec_vspltw:\n /* Only allow 5-bit unsigned literals. */\n STRIP_NOPS (arg1);\n if (TREE_CODE (arg1) != INTEGER_CST\n@@ -14017,16 +14020,15 @@ rs6000_expand_binop_builtin (enum insn_c\n \t error (\"argument 2 must be a 5-bit unsigned literal\");\n \t return CONST0_RTX (tmode);\n \t}\n- }\n- else if (icode == CODE_FOR_dfptstsfi_eq_dd\n- || icode == CODE_FOR_dfptstsfi_lt_dd\n- || icode == CODE_FOR_dfptstsfi_gt_dd\n- || icode == CODE_FOR_dfptstsfi_unordered_dd\n- || icode == CODE_FOR_dfptstsfi_eq_td\n- || icode == CODE_FOR_dfptstsfi_lt_td\n- || icode == CODE_FOR_dfptstsfi_gt_td\n- || icode == CODE_FOR_dfptstsfi_unordered_td)\n- {\n+ break;\n+ case CODE_FOR_dfptstsfi_eq_dd:\n+ case CODE_FOR_dfptstsfi_lt_dd:\n+ case CODE_FOR_dfptstsfi_gt_dd:\n+ case CODE_FOR_dfptstsfi_unordered_dd:\n+ case CODE_FOR_dfptstsfi_eq_td:\n+ case CODE_FOR_dfptstsfi_lt_td:\n+ case CODE_FOR_dfptstsfi_gt_td:\n+ case CODE_FOR_dfptstsfi_unordered_td:\n /* Only allow 6-bit unsigned literals. */\n STRIP_NOPS (arg0);\n if (TREE_CODE (arg0) != INTEGER_CST\n@@ -14035,13 +14037,12 @@ rs6000_expand_binop_builtin (enum insn_c\n \t error (\"argument 1 must be a 6-bit unsigned literal\");\n \t return CONST0_RTX (tmode);\n \t}\n- }\n- else if (icode == CODE_FOR_xststdcqp\n-\t || icode == CODE_FOR_xststdcdp\n-\t || icode == CODE_FOR_xststdcsp\n-\t || icode == CODE_FOR_xvtstdcdp\n-\t || icode == CODE_FOR_xvtstdcsp)\n- {\n+ break;\n+ case CODE_FOR_xststdcqp:\n+ case CODE_FOR_xststdcdp:\n+ case CODE_FOR_xststdcsp:\n+ case CODE_FOR_xvtstdcdp:\n+ case CODE_FOR_xvtstdcsp:\n /* Only allow 7-bit unsigned literals. */\n STRIP_NOPS (arg1);\n if (TREE_CODE (arg1) != INTEGER_CST\n@@ -14050,6 +14051,21 @@ rs6000_expand_binop_builtin (enum insn_c\n \t error (\"argument 2 must be a 7-bit unsigned literal\");\n \t return CONST0_RTX (tmode);\n \t}\n+ break;\n+ case CODE_FOR_unpackv1ti:\n+ case CODE_FOR_unpackkf:\n+ case CODE_FOR_unpacktf:\n+ case CODE_FOR_unpackif:\n+ case CODE_FOR_unpacktd:\n+ /* Only allow 1-bit unsigned literals. */\n+ STRIP_NOPS (arg1);\n+ if (TREE_CODE (arg1) != INTEGER_CST\n+\t || !IN_RANGE (TREE_INT_CST_LOW (arg1), 0, 1))\n+\t{\n+\t error (\"argument 2 must be 0 or 1\");\n+\t return CONST0_RTX (tmode);\n+\t}\n+ break;\n }\n \n if (target == 0\nIndex: gcc/config/rs6000/rs6000.md\n===================================================================\n--- gcc/config/rs6000/rs6000.md\t(revision 251390)\n+++ gcc/config/rs6000/rs6000.md\t(working copy)\n@@ -14165,7 +14165,7 @@ (define_insn_and_split \"pack\"\n (set_attr \"length\" \"4,8\")])\n \n (define_insn \"unpack\"\n- [(set (match_operand:DI 0 \"register_operand\" \"=d,d\")\n+ [(set (match_operand:DI 0 \"register_operand\" \"=wa,wa\")\n \t(unspec:DI [(match_operand:FMOVE128_VSX 1 \"register_operand\" \"0,wa\")\n \t\t (match_operand:QI 2 \"const_0_to_1_operand\" \"O,i\")]\n \t UNSPEC_UNPACK_128BIT))]\n@@ -14182,8 +14182,8 @@ (define_insn \"unpack\"\n (define_insn \"pack\"\n [(set (match_operand:FMOVE128_VSX 0 \"register_operand\" \"=wa\")\n \t(unspec:FMOVE128_VSX\n-\t [(match_operand:DI 1 \"register_operand\" \"d\")\n-\t (match_operand:DI 2 \"register_operand\" \"d\")]\n+\t [(match_operand:DI 1 \"register_operand\" \"wa\")\n+\t (match_operand:DI 2 \"register_operand\" \"wa\")]\n \t UNSPEC_PACK_128BIT))]\n \"TARGET_VSX\"\n \"xxpermdi %x0,%x1,%x2,0\"\nIndex: gcc/testsuite/gcc.target/powerpc/pr82015.c\n===================================================================\n--- gcc/testsuite/gcc.target/powerpc/pr82015.c\t(revision 0)\n+++ gcc/testsuite/gcc.target/powerpc/pr82015.c\t(revision 0)\n@@ -0,0 +1,14 @@\n+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */\n+/* { dg-skip-if \"\" { powerpc*-*-darwin* } } */\n+/* { dg-require-effective-target powerpc_vsx_ok } */\n+/* { dg-options \"-O2 -mvsx\" } */\n+\n+unsigned long foo_11(vector __int128_t *p)\n+{\n+ return __builtin_unpack_vector_int128(*p, 11); /* { dg-error \"argument 2 must be 0 or 1\" } */\n+}\n+\n+unsigned long foo_n(vector __int128_t *p, unsigned long n)\n+{\n+ return __builtin_unpack_vector_int128(*p, n);\t/* { dg-error \"argument 2 must be 0 or 1\" } */\n+}\n","prefixes":[]}