{"id":805768,"url":"http://patchwork.ozlabs.org/api/1.2/patches/805768/?format=json","web_url":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503639722-19121-8-git-send-email-paulus@ozlabs.org/","project":{"id":2,"url":"http://patchwork.ozlabs.org/api/1.2/projects/2/?format=json","name":"Linux PPC development","link_name":"linuxppc-dev","list_id":"linuxppc-dev.lists.ozlabs.org","list_email":"linuxppc-dev@lists.ozlabs.org","web_url":"https://github.com/linuxppc/wiki/wiki","scm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git","webscm_url":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/","list_archive_url":"https://lore.kernel.org/linuxppc-dev/","list_archive_url_format":"https://lore.kernel.org/linuxppc-dev/{}/","commit_url_format":"https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}"},"msgid":"<1503639722-19121-8-git-send-email-paulus@ozlabs.org>","list_archive_url":"https://lore.kernel.org/linuxppc-dev/1503639722-19121-8-git-send-email-paulus@ozlabs.org/","date":"2017-08-25T05:41:59","name":"[v2,07/10] powerpc: Handle vector element load/stores in emulation code","commit_ref":null,"pull_url":null,"state":"superseded","archived":true,"hash":"29b0306d3058ebbe0ac4f12f2266c3316e17d374","submitter":{"id":67079,"url":"http://patchwork.ozlabs.org/api/1.2/people/67079/?format=json","name":"Paul Mackerras","email":"paulus@ozlabs.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503639722-19121-8-git-send-email-paulus@ozlabs.org/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/805768/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/805768/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org","linuxppc-dev@ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xdrYK39jxz9s4s\n\tfor ;\n\tFri, 25 Aug 2017 16:17:25 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xdrYK1yRFzDrW7\n\tfor ;\n\tFri, 25 Aug 2017 16:17:25 +1000 (AEST)","from ozlabs.org (bilbo.ozlabs.org [103.22.144.67])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xdrDW3MvczDrS9\n\tfor ;\n\tFri, 25 Aug 2017 16:02:51 +1000 (AEST)","by ozlabs.org (Postfix)\n\tid 3xdrDW2kNcz9sR9; Fri, 25 Aug 2017 16:02:51 +1000 (AEST)","from authenticated.ozlabs.org (localhost [127.0.0.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPSA id 3xdrDW1w42z9sRY\n\tfor ; Fri, 25 Aug 2017 16:02:51 +1000 (AEST)"],"Authentication-Results":["ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"hJJO5qub\";\n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"hJJO5qub\";\n\tdkim-atps=neutral","lists.ozlabs.org; dkim=pass (2048-bit key;\n\tsecure) header.d=ozlabs.org header.i=@ozlabs.org header.b=\"hJJO5qub\"; \n\tdkim-atps=neutral"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; \n\tt=1503640971; bh=qMFAyuyIcc2ArQ277I8KBQkOnrIad8H7KjolmnCY5bw=;\n\th=From:To:Subject:Date:In-Reply-To:References:From;\n\tb=hJJO5qubBl2MetIu1FrAnuM6WPH6JvWJhIXfGVpe/sPSKvh53XIb2FkTS7hS7f9Kx\n\txldAHVVePUXCGK3jj3JHnA96/ohI0jWGRGCVRIV1rxFhDrlJ+iTpDqS+zmOsLPucNb\n\toK/kAYuKRXNke1dIPNMC2yIPaVvJyms3u2TtyM3xCk/ae3kAMDbJCdLzjlILndjDoH\n\tjz1y1edCZfYWu0r01fVhHWEQfaNzAlu6/UE4GpKmc9wlm+mGh4UCUASP88oiwaEcgk\n\tc3+H/wNR+/V1MDMKD7mb/TmZloFsz7SfyNvMtnquskqsMSsSiKjA3loCsnFaNg2uAo\n\tJlciV4qTNOAxQ==","From":"Paul Mackerras ","To":"linuxppc-dev@ozlabs.org","Subject":"[PATCH v2 07/10] powerpc: Handle vector element load/stores in\n\temulation code","Date":"Fri, 25 Aug 2017 15:41:59 +1000","Message-Id":"<1503639722-19121-8-git-send-email-paulus@ozlabs.org>","X-Mailer":"git-send-email 2.7.4","In-Reply-To":"<1503639722-19121-1-git-send-email-paulus@ozlabs.org>","References":"<1503639722-19121-1-git-send-email-paulus@ozlabs.org>","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"},"content":"This adds code to analyse_instr() and emulate_step() to handle the\nvector element loads and stores:\n\nlvebx, lvehx, lvewx, stvebx, stvehx, stvewx.\n\nSigned-off-by: Paul Mackerras \n---\n arch/powerpc/lib/sstep.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 48 insertions(+), 2 deletions(-)","diff":"diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c\nindex 0b295fb..82b1e69 100644\n--- a/arch/powerpc/lib/sstep.c\n+++ b/arch/powerpc/lib/sstep.c\n@@ -475,7 +475,7 @@ static nokprobe_inline int do_vec_load(int rn, unsigned long ea,\n \t\treturn -EFAULT;\n \t/* align to multiple of size */\n \tea &= ~(size - 1);\n-\terr = copy_mem_in(u.b, ea, size);\n+\terr = copy_mem_in(&u.b[ea & 0xf], ea, size);\n \tif (err)\n \t\treturn err;\n \n@@ -507,7 +507,7 @@ static nokprobe_inline int do_vec_store(int rn, unsigned long ea,\n \telse\n \t\tu.v = current->thread.vr_state.vr[rn];\n \tpreempt_enable();\n-\treturn copy_mem_out(u.b, ea, size);\n+\treturn copy_mem_out(&u.b[ea & 0xf], ea, size);\n }\n #endif /* CONFIG_ALTIVEC */\n \n@@ -1808,6 +1808,31 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\t\tbreak;\n \n #ifdef CONFIG_ALTIVEC\n+\t\t/*\n+\t\t * Note: for the load/store vector element instructions,\n+\t\t * bits of the EA say which field of the VMX register to use.\n+\t\t */\n+\t\tcase 7:\t\t/* lvebx */\n+\t\t\tif (!(regs->msr & MSR_VEC))\n+\t\t\t\tgoto vecunavail;\n+\t\t\top->type = MKOP(LOAD_VMX, 0, 1);\n+\t\t\top->element_size = 1;\n+\t\t\tbreak;\n+\n+\t\tcase 39:\t/* lvehx */\n+\t\t\tif (!(regs->msr & MSR_VEC))\n+\t\t\t\tgoto vecunavail;\n+\t\t\top->type = MKOP(LOAD_VMX, 0, 2);\n+\t\t\top->element_size = 2;\n+\t\t\tbreak;\n+\n+\t\tcase 71:\t/* lvewx */\n+\t\t\tif (!(regs->msr & MSR_VEC))\n+\t\t\t\tgoto vecunavail;\n+\t\t\top->type = MKOP(LOAD_VMX, 0, 4);\n+\t\t\top->element_size = 4;\n+\t\t\tbreak;\n+\n \t\tcase 103:\t/* lvx */\n \t\tcase 359:\t/* lvxl */\n \t\t\tif (!(regs->msr & MSR_VEC))\n@@ -1816,6 +1841,27 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,\n \t\t\top->element_size = 16;\n \t\t\tbreak;\n \n+\t\tcase 135:\t/* stvebx */\n+\t\t\tif (!(regs->msr & MSR_VEC))\n+\t\t\t\tgoto vecunavail;\n+\t\t\top->type = MKOP(STORE_VMX, 0, 1);\n+\t\t\top->element_size = 1;\n+\t\t\tbreak;\n+\n+\t\tcase 167:\t/* stvehx */\n+\t\t\tif (!(regs->msr & MSR_VEC))\n+\t\t\t\tgoto vecunavail;\n+\t\t\top->type = MKOP(STORE_VMX, 0, 2);\n+\t\t\top->element_size = 2;\n+\t\t\tbreak;\n+\n+\t\tcase 199:\t/* stvewx */\n+\t\t\tif (!(regs->msr & MSR_VEC))\n+\t\t\t\tgoto vecunavail;\n+\t\t\top->type = MKOP(STORE_VMX, 0, 4);\n+\t\t\top->element_size = 4;\n+\t\t\tbreak;\n+\n \t\tcase 231:\t/* stvx */\n \t\tcase 487:\t/* stvxl */\n \t\t\tif (!(regs->msr & MSR_VEC))\n","prefixes":["v2","07/10"]}