{"id":804533,"url":"http://patchwork.ozlabs.org/api/1.2/patches/804533/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1503414919-30820-10-git-send-email-bmeng.cn@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503414919-30820-10-git-send-email-bmeng.cn@gmail.com>","list_archive_url":null,"date":"2017-08-22T15:15:14","name":"[U-Boot,09/14] nvme: Apply cache operations on the DMA buffers","commit_ref":"704e040a51d2456a6c56e79363279b230d37cef7","pull_url":null,"state":"accepted","archived":false,"hash":"6c69f9e228076870dd9d59092c8a985db114573c","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/1.2/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.2/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1503414919-30820-10-git-send-email-bmeng.cn@gmail.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/804533/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/804533/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"So far cache operations are only applied on the submission queue and\ncompletion queue, but they are missing in other places like identify\nand block read/write routines.\n\nIn order to correctly operate on the caches, the DMA buffer passed\nto identify routine must be allocated properly on the stack with the\nexisting macro ALLOC_CACHE_ALIGN_BUFFER().\n\nSigned-off-by: Bin Meng \n---\n\n drivers/nvme/nvme.c | 32 +++++++++++++++++++++++++++++---\n drivers/nvme/nvme_show.c | 7 +++++--\n 2 files changed, 34 insertions(+), 5 deletions(-)","diff":"diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c\nindex c545ce7..67f7d75 100644\n--- a/drivers/nvme/nvme.c\n+++ b/drivers/nvme/nvme.c\n@@ -435,6 +435,7 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,\n \tu32 page_size = dev->page_size;\n \tint offset = dma_addr & (page_size - 1);\n \tint length = sizeof(struct nvme_id_ctrl);\n+\tint ret;\n \n \tmemset(&c, 0, sizeof(c));\n \tc.identify.opcode = nvme_admin_identify;\n@@ -451,7 +452,12 @@ int nvme_identify(struct nvme_dev *dev, unsigned nsid,\n \n \tc.identify.cns = cpu_to_le32(cns);\n \n-\treturn nvme_submit_admin_cmd(dev, &c, NULL);\n+\tret = nvme_submit_admin_cmd(dev, &c, NULL);\n+\tif (!ret)\n+\t\tinvalidate_dcache_range(dma_addr,\n+\t\t\t\t\tdma_addr + sizeof(struct nvme_id_ctrl));\n+\n+\treturn ret;\n }\n \n int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,\n@@ -465,6 +471,11 @@ int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,\n \tc.features.prp1 = cpu_to_le64(dma_addr);\n \tc.features.fid = cpu_to_le32(fid);\n \n+\t/*\n+\t * TODO: add cache invalidate operation when the size of\n+\t * the DMA buffer is known\n+\t */\n+\n \treturn nvme_submit_admin_cmd(dev, &c, result);\n }\n \n@@ -479,6 +490,11 @@ int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,\n \tc.features.fid = cpu_to_le32(fid);\n \tc.features.dword11 = cpu_to_le32(dword11);\n \n+\t/*\n+\t * TODO: add cache flush operation when the size of\n+\t * the DMA buffer is known\n+\t */\n+\n \treturn nvme_submit_admin_cmd(dev, &c, result);\n }\n \n@@ -562,7 +578,8 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)\n \n static int nvme_get_info_from_identify(struct nvme_dev *dev)\n {\n-\tstruct nvme_id_ctrl buf, *ctrl = &buf;\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ctrl));\n+\tstruct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf;\n \tint ret;\n \tint shift = NVME_CAP_MPSMIN(dev->cap) + 12;\n \n@@ -627,7 +644,8 @@ static int nvme_blk_probe(struct udevice *udev)\n \tstruct blk_desc *desc = dev_get_uclass_platdata(udev);\n \tstruct nvme_ns *ns = dev_get_priv(udev);\n \tu8 flbas;\n-\tstruct nvme_id_ns buf, *id = &buf;\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf, sizeof(struct nvme_id_ns));\n+\tstruct nvme_id_ns *id = (struct nvme_id_ns *)buf;\n \tstruct pci_child_platdata *pplat;\n \n \tmemset(ns, 0, sizeof(*ns));\n@@ -672,6 +690,10 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,\n \tu16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);\n \tu64 total_lbas = blkcnt;\n \n+\tif (!read)\n+\t\tflush_dcache_range((unsigned long)buffer,\n+\t\t\t\t (unsigned long)buffer + total_len);\n+\n \tc.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;\n \tc.rw.flags = 0;\n \tc.rw.nsid = cpu_to_le32(ns->ns_id);\n@@ -706,6 +728,10 @@ static ulong nvme_blk_rw(struct udevice *udev, lbaint_t blknr,\n \t\tbuffer += lbas << ns->lba_shift;\n \t}\n \n+\tif (read)\n+\t\tinvalidate_dcache_range((unsigned long)buffer,\n+\t\t\t\t\t(unsigned long)buffer + total_len);\n+\n \treturn (total_len - temp_len) >> desc->log2blksz;\n }\n \ndiff --git a/drivers/nvme/nvme_show.c b/drivers/nvme/nvme_show.c\nindex 5577e5d..5235138 100644\n--- a/drivers/nvme/nvme_show.c\n+++ b/drivers/nvme/nvme_show.c\n@@ -8,6 +8,7 @@\n #include \n #include \n #include \n+#include \n #include \n #include \"nvme.h\"\n \n@@ -106,8 +107,10 @@ int nvme_print_info(struct udevice *udev)\n {\n \tstruct nvme_ns *ns = dev_get_priv(udev);\n \tstruct nvme_dev *dev = ns->dev;\n-\tstruct nvme_id_ns buf_ns, *id = &buf_ns;\n-\tstruct nvme_id_ctrl buf_ctrl, *ctrl = &buf_ctrl;\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf_ns, sizeof(struct nvme_id_ns));\n+\tstruct nvme_id_ns *id = (struct nvme_id_ns *)buf_ns;\n+\tALLOC_CACHE_ALIGN_BUFFER(char, buf_ctrl, sizeof(struct nvme_id_ctrl));\n+\tstruct nvme_id_ctrl *ctrl = (struct nvme_id_ctrl *)buf_ctrl;\n \n \tif (nvme_identify(dev, 0, 1, (dma_addr_t)ctrl))\n \t\treturn -EIO;\n","prefixes":["U-Boot","09/14"]}