{"id":804530,"url":"http://patchwork.ozlabs.org/api/1.2/patches/804530/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1503414919-30820-6-git-send-email-bmeng.cn@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1503414919-30820-6-git-send-email-bmeng.cn@gmail.com>","list_archive_url":null,"date":"2017-08-22T15:15:10","name":"[U-Boot,05/14] nvme: Cache controller's capabilities","commit_ref":"b65c6921433c8fcf306b4671f9f9f7c68c36cefc","pull_url":null,"state":"accepted","archived":false,"hash":"9ea7cb1bd394a032eb01db2b925b3208845f71e9","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/1.2/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"delegate":{"id":3651,"url":"http://patchwork.ozlabs.org/api/1.2/users/3651/?format=json","username":"trini","first_name":"Tom","last_name":"Rini","email":"trini@ti.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1503414919-30820-6-git-send-email-bmeng.cn@gmail.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/804530/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/804530/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Capabilities register is RO and accessed at various places in the\ndriver. Let's cache it in the controller driver's priv struct.\n\nSigned-off-by: Bin Meng \n---\n\n drivers/nvme/nvme.c | 11 +++++------\n drivers/nvme/nvme.h | 1 +\n 2 files changed, 6 insertions(+), 6 deletions(-)","diff":"diff --git a/drivers/nvme/nvme.c b/drivers/nvme/nvme.c\nindex 2ae947c..d92273e 100644\n--- a/drivers/nvme/nvme.c\n+++ b/drivers/nvme/nvme.c\n@@ -318,7 +318,7 @@ static int nvme_configure_admin_queue(struct nvme_dev *dev)\n {\n \tint result;\n \tu32 aqa;\n-\tu64 cap = nvme_readq(&dev->bar->cap);\n+\tu64 cap = dev->cap;\n \tstruct nvme_queue *nvmeq;\n \t/* most architectures use 4KB as the page size */\n \tunsigned page_shift = 12;\n@@ -549,7 +549,7 @@ static int nvme_get_info_from_identify(struct nvme_dev *dev)\n {\n \tstruct nvme_id_ctrl buf, *ctrl = &buf;\n \tint ret;\n-\tint shift = NVME_CAP_MPSMIN(nvme_readq(&dev->bar->cap)) + 12;\n+\tint shift = NVME_CAP_MPSMIN(dev->cap) + 12;\n \n \tret = nvme_identify(dev, 0, 1, (dma_addr_t)ctrl);\n \tif (ret)\n@@ -772,7 +772,6 @@ static int nvme_probe(struct udevice *udev)\n {\n \tint ret;\n \tstruct nvme_dev *ndev = dev_get_priv(udev);\n-\tu64 cap;\n \n \tndev->instance = trailing_strtol(udev->name);\n \n@@ -801,9 +800,9 @@ static int nvme_probe(struct udevice *udev)\n \t}\n \tndev->prp_entry_num = MAX_PRP_POOL >> 3;\n \n-\tcap = nvme_readq(&ndev->bar->cap);\n-\tndev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);\n-\tndev->db_stride = 1 << NVME_CAP_STRIDE(cap);\n+\tndev->cap = nvme_readq(&ndev->bar->cap);\n+\tndev->q_depth = min_t(int, NVME_CAP_MQES(ndev->cap) + 1, NVME_Q_DEPTH);\n+\tndev->db_stride = 1 << NVME_CAP_STRIDE(ndev->cap);\n \tndev->dbs = ((void __iomem *)ndev->bar) + 4096;\n \n \tret = nvme_configure_admin_queue(ndev);\ndiff --git a/drivers/nvme/nvme.h b/drivers/nvme/nvme.h\nindex cd411be..f0fa639 100644\n--- a/drivers/nvme/nvme.h\n+++ b/drivers/nvme/nvme.h\n@@ -621,6 +621,7 @@ struct nvme_dev {\n \tchar model[40];\n \tchar firmware_rev[8];\n \tu32 max_transfer_shift;\n+\tu64 cap;\n \tu32 stripe_size;\n \tu32 page_size;\n \tu8 vwc;\n","prefixes":["U-Boot","05/14"]}