{"id":802395,"url":"http://patchwork.ozlabs.org/api/1.2/patches/802395/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1502955089-2049-1-git-send-email-ran.wang_1@nxp.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1502955089-2049-1-git-send-email-ran.wang_1@nxp.com>","list_archive_url":null,"date":"2017-08-17T07:31:22","name":"[U-Boot,v3,1/8] armv8: Add workaround for USB erratum A-009008","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"f09631c3381c5b02a85b63441752217ef316d624","submitter":{"id":71939,"url":"http://patchwork.ozlabs.org/api/1.2/people/71939/?format=json","name":"Ran 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07:48:28.3573\n\t(UTC)","X-MS-Exchange-CrossTenant-Id":"5afe0b00-7697-4969-b663-5eab37d5f47e","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"TenantId=5afe0b00-7697-4969-b663-5eab37d5f47e;\n\tIp=[192.88.168.50]; \n\tHelo=[tx30smr01.am.freescale.net]","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"BN6PR03MB3316","Cc":"Priyanka Jain , ran.wang_1@nxp.com","Subject":"[U-Boot] [PATCH v3 1/8] armv8: Add workaround for USB erratum\n\tA-009008","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"USB High Speed (HS) EYE Height Adjustment\nUSB HS speed eye diagram fails with the default value at\nmany corners, particularly at a high temperature\n\nOptimal eye at TXREFTUNE value to 1001 is observed, change\nset the same value.\n\nSigned-off-by: Ran Wang \n---\nChange in v3:\n\tUse inline function to make code cleaner.\n\nChange in v2:\n\tIn function erratum_a009008():\n\t1.Put a blank line after variable declaration.\n\t2.Move common code together.\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 ++++++\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 25 ++++++++++++++++++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 6 ++++++\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 +\n 4 files changed, 39 insertions(+)","diff":"diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex 5825f9b..300f5ce 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -22,6 +22,7 @@ config ARCH_LS1043A\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010315\n \tselect SYS_FSL_ERRATUM_A010539\n+\tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_HAS_DDR3\n \tselect SYS_FSL_HAS_DDR4\n \tselect ARCH_EARLY_INIT_R\n@@ -43,6 +44,7 @@ config ARCH_LS1046A\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010165\n \tselect SYS_FSL_ERRATUM_A010539\n+\tselect SYS_FSL_ERRATUM_A009008\n \tselect SYS_FSL_HAS_DDR4\n \tselect SYS_FSL_SRDS_2\n \tselect ARCH_EARLY_INIT_R\n@@ -79,6 +81,7 @@ config ARCH_LS2080A\n \tselect SYS_FSL_ERRATUM_A009942\n \tselect SYS_FSL_ERRATUM_A010165\n \tselect SYS_FSL_ERRATUM_A009203\n+\tselect SYS_FSL_ERRATUM_A009008\n \tselect ARCH_EARLY_INIT_R\n \tselect BOARD_EARLY_INIT_F\n \n@@ -222,6 +225,10 @@ config SYS_FSL_ERRATUM_A010315\n config SYS_FSL_ERRATUM_A010539\n \tbool \"Workaround for PIN MUX erratum A010539\"\n \n+config SYS_FSL_ERRATUM_A009008\n+\tbool \"Workaround for USB PHY erratum A009008\"\n+\n+\n config MAX_CPUS\n \tint \"Maximum number of CPUs permitted for Layerscape\"\n \tdefault 4 if ARCH_LS1043A\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex aee1ffa..7e5288b 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -52,6 +52,29 @@ bool soc_has_aiop(void)\n \treturn false;\n }\n \n+static inline void set_usb_txvreftune(u32 __iomem *scfg, u32 offset)\n+{\n+\tu32 val;\n+\n+\tval = scfg_in32(scfg + offset / 4) & ~(0xF << 6);\n+\tval |= USB_TXVREFTUNE << 6;\n+\tscfg_out32(scfg + offset / 4, val);\n+}\n+\n+static void erratum_a009008(void)\n+{\n+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008\n+\tu32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;\n+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)\n+\tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1);\n+\tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2);\n+\tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3);\n+#elif defined(CONFIG_ARCH_LS2080A)\n+\tset_usb_txvreftune(scfg, SCFG_USB3PRM1CR);\n+#endif\n+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */\n+}\n+\n #if defined(CONFIG_FSL_LSCH3)\n /*\n * This erratum requires setting a value to eddrtqcr1 to\n@@ -198,6 +221,7 @@ void fsl_lsch3_early_init_f(void)\n #endif\n \terratum_a008514();\n \terratum_a008336();\n+\terratum_a009008();\n #ifdef CONFIG_CHAIN_OF_TRUST\n \t/* In case of Secure Boot, the IBR configures the SMMU\n \t* to allow only Secure transactions.\n@@ -473,6 +497,7 @@ void fsl_lsch2_early_init_f(void)\n \terratum_a009929();\n \terratum_a009660();\n \terratum_a010539();\n+\terratum_a009008();\n }\n #endif\n \ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\nindex 8ad199f..62d7046 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h\n@@ -337,6 +337,12 @@ struct ccsr_gur {\n #define SCFG_USBPWRFAULT_USB2_SHIFT\t2\n #define SCFG_USBPWRFAULT_USB1_SHIFT\t0\n \n+#define SCFG_BASE\t\t\t0x01570000\n+#define SCFG_USB3PRM1CR_USB1\t\t0x070\n+#define SCFG_USB3PRM1CR_USB2\t\t0x07C\n+#define SCFG_USB3PRM1CR_USB3\t\t0x088\n+#define USB_TXVREFTUNE\t\t\t0x9\n+\n #define SCFG_SNPCNFGCR_SECRDSNP\t\t0x80000000\n #define SCFG_SNPCNFGCR_SECWRSNP\t\t0x40000000\n #define SCFG_SNPCNFGCR_SATARDSNP\t0x00800000\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 59410aa..c622ee5 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -133,6 +133,7 @@\n #define SCFG_BASE\t\t0x01fc0000\n #define SCFG_USB3PRM1CR\t\t\t0x000\n #define SCFG_USB3PRM1CR_INIT\t\t0x27672b2a\n+#define USB_TXVREFTUNE\t\t\t0x9\n #define SCFG_QSPICLKCTLR\t0x10\n \n #define TP_ITYP_AV\t\t0x00000001\t/* Initiator available */\n","prefixes":["U-Boot","v3","1/8"]}