{"id":801902,"url":"http://patchwork.ozlabs.org/api/1.2/patches/801902/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1502862122-14771-12-git-send-email-bmeng.cn@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1502862122-14771-12-git-send-email-bmeng.cn@gmail.com>","list_archive_url":null,"date":"2017-08-16T05:42:00","name":"[U-Boot,11/13] x86: braswell: Add FSP configuration","commit_ref":null,"pull_url":null,"state":"accepted","archived":false,"hash":"c42ca2956ba58dfe535f3632f54c1ab5354b7739","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/1.2/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"delegate":{"id":56520,"url":"http://patchwork.ozlabs.org/api/1.2/users/56520/?format=json","username":"bmeng","first_name":"Bin","last_name":"Meng","email":"bmeng.cn@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1502862122-14771-12-git-send-email-bmeng.cn@gmail.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/801902/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/801902/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com 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1.7.9.5","In-Reply-To":"<1502862122-14771-1-git-send-email-bmeng.cn@gmail.com>","References":"<1502862122-14771-1-git-send-email-bmeng.cn@gmail.com>","Subject":"[U-Boot] [PATCH 11/13] x86: braswell: Add FSP configuration","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Add FSP related configuration for Braswell.\n\nSigned-off-by: Bin Meng \n---\n\n arch/x86/cpu/braswell/Makefile | 2 +-\n arch/x86/cpu/braswell/fsp_configs.c | 158 ++++++++++++++\n .../include/asm/arch-braswell/fsp/fsp_configs.h | 89 ++++++++\n arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h | 172 +++++++++++++++\n arch/x86/include/asm/arch-braswell/gpio.h | 234 +++++++++++++++++++++\n 5 files changed, 654 insertions(+), 1 deletion(-)\n create mode 100644 arch/x86/cpu/braswell/fsp_configs.c\n create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h\n create mode 100644 arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h\n create mode 100644 arch/x86/include/asm/arch-braswell/gpio.h","diff":"diff --git a/arch/x86/cpu/braswell/Makefile b/arch/x86/cpu/braswell/Makefile\nindex 19bcee6..ddf6d28 100644\n--- a/arch/x86/cpu/braswell/Makefile\n+++ b/arch/x86/cpu/braswell/Makefile\n@@ -4,4 +4,4 @@\n # SPDX-License-Identifier:\tGPL-2.0+\n #\n \n-obj-y += braswell.o cpu.o early_uart.o\n+obj-y += braswell.o cpu.o early_uart.o fsp_configs.o\ndiff --git a/arch/x86/cpu/braswell/fsp_configs.c b/arch/x86/cpu/braswell/fsp_configs.c\nnew file mode 100644\nindex 0000000..d984519\n--- /dev/null\n+++ b/arch/x86/cpu/braswell/fsp_configs.c\n@@ -0,0 +1,158 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include \n+#include \n+#include \n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+/**\n+ * Override the FSP's Azalia configuration data\n+ *\n+ * @azalia:\tpointer to be updated to point to a ROM address where Azalia\n+ *\t\tconfiguration data is stored\n+ */\n+__weak void update_fsp_azalia_configs(struct azalia_config **azalia)\n+{\n+\t*azalia = NULL;\n+}\n+\n+/**\n+ * Override the FSP's GPIO configuration data\n+ *\n+ * @family:\tpointer to be updated to point to a ROM address where GPIO\n+ *\t\tfamily configuration data is stored\n+ * @pad:\tpointer to be updated to point to a ROM address where GPIO\n+ *\t\tpad configuration data is stored\n+ */\n+__weak void update_fsp_gpio_configs(struct gpio_family **family,\n+\t\t\t\t struct gpio_pad **pad)\n+{\n+\t*family = NULL;\n+\t*pad = NULL;\n+}\n+\n+/**\n+ * Override the FSP's configuration data.\n+ * If the device tree does not specify an integer setting, use the default\n+ * provided in Intel's Braswell release FSP/BraswellFsp.bsf file.\n+ */\n+void update_fsp_configs(struct fsp_config_data *config,\n+\t\t\tstruct fspinit_rtbuf *rt_buf)\n+{\n+\tstruct upd_region *fsp_upd = &config->fsp_upd;\n+\tstruct memory_upd *memory_upd = &fsp_upd->memory_upd;\n+\tstruct silicon_upd *silicon_upd = &fsp_upd->silicon_upd;\n+\tconst void *blob = gd->fdt_blob;\n+\tint node;\n+\n+\t/* Initialize runtime buffer for fsp_init() */\n+\trt_buf->common.stack_top = config->common.stack_top - 32;\n+\trt_buf->common.boot_mode = config->common.boot_mode;\n+\trt_buf->common.upd_data = &config->fsp_upd;\n+\n+\tnode = fdt_node_offset_by_compatible(blob, 0, \"intel,braswell-fsp\");\n+\tif (node < 0) {\n+\t\tdebug(\"%s: Cannot find FSP node\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\tnode = fdt_node_offset_by_compatible(blob, node,\n+\t\t\t\t\t \"intel,braswell-fsp-memory\");\n+\tif (node < 0) {\n+\t\tdebug(\"%s: Cannot find FSP memory node\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\t/* Override memory UPD contents */\n+\tmemory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,\n+\t\t\"fsp,mrc-init-tseg-size\", MRC_INIT_TSEG_SIZE_4MB);\n+\tmemory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,\n+\t\t\"fsp,mrc-init-mmio-size\", MRC_INIT_MMIO_SIZE_2048MB);\n+\tmemory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,\n+\t\t\"fsp,mrc-init-spd-addr1\", 0xa0);\n+\tmemory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,\n+\t\t\"fsp,mrc-init-spd-addr2\", 0xa2);\n+\tmemory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,\n+\t\t\"fsp,igd-dvmt50-pre-alloc\", IGD_DVMT50_PRE_ALLOC_32MB);\n+\tmemory_upd->aperture_size = fdtdec_get_int(blob, node,\n+\t\t\"fsp,aperture-size\", APERTURE_SIZE_256MB);\n+\tmemory_upd->gtt_size = fdtdec_get_int(blob, node,\n+\t\t\"fsp,gtt-size\", GTT_SIZE_1MB);\n+\tmemory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,legacy-seg-decode\");\n+\tmemory_upd->enable_dvfs = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-dvfs\");\n+\tmemory_upd->memory_type = fdtdec_get_int(blob, node,\n+\t\t\"fsp,memory-type\", DRAM_TYPE_DDR3);\n+\tmemory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-ca-mirror\");\n+\n+\tnode = fdt_node_offset_by_compatible(blob, node,\n+\t\t\t\t\t \"intel,braswell-fsp-silicon\");\n+\tif (node < 0) {\n+\t\tdebug(\"%s: Cannot find FSP silicon node\\n\", __func__);\n+\t\treturn;\n+\t}\n+\n+\t/* Override silicon UPD contents */\n+\tsilicon_upd->sdcard_mode = fdtdec_get_int(blob, node,\n+\t\t\"fsp,sdcard-mode\", SDCARD_MODE_PCI);\n+\tsilicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-hsuart0\");\n+\tsilicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-hsuart1\");\n+\tsilicon_upd->enable_azalia = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-azalia\");\n+\tif (silicon_upd->enable_azalia)\n+\t\tupdate_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr);\n+\tsilicon_upd->enable_sata = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-sata\");\n+\tsilicon_upd->enable_xhci = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-xhci\");\n+\tsilicon_upd->lpe_mode = fdtdec_get_int(blob, node,\n+\t\t\"fsp,lpe-mode\", LPE_MODE_PCI);\n+\tsilicon_upd->enable_dma0 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-dma0\");\n+\tsilicon_upd->enable_dma1 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-dma1\");\n+\tsilicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-i2c0\");\n+\tsilicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-i2c1\");\n+\tsilicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-i2c2\");\n+\tsilicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-i2c3\");\n+\tsilicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-i2c4\");\n+\tsilicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-i2c5\");\n+\tsilicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-i2c6\");\n+#ifdef CONFIG_HAVE_VBT\n+\tsilicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR;\n+#endif\n+\tupdate_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,\n+\t\t\t\t&silicon_upd->gpio_pad_ptr);\n+\tsilicon_upd->emmc_mode = fdtdec_get_int(blob, node,\n+\t\t\"fsp,emmc-mode\", EMMC_MODE_PCI);\n+\tsilicon_upd->sata_speed = fdtdec_get_int(blob, node,\n+\t\t\"fsp,sata-speed\", SATA_SPEED_GEN3);\n+\tsilicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node,\n+\t\t\"fsp,pmic-i2c-bus\", 0);\n+\tsilicon_upd->enable_isp = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,enable-isp\");\n+\tsilicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node,\n+\t\t\"fsp,isp-pci-dev-config\", ISP_PCI_DEV_CONFIG_2);\n+\tsilicon_upd->turbo_mode = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,turbo-mode\");\n+\tsilicon_upd->pnp_settings = fdtdec_get_int(blob, node,\n+\t\t\"fsp,pnp-settings\", PNP_SETTING_POWER_AND_PERF);\n+\tsilicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node,\n+\t\t\"fsp,sd-detect-chk\");\n+}\ndiff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h\nnew file mode 100644\nindex 0000000..4b8521d\n--- /dev/null\n+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_configs.h\n@@ -0,0 +1,89 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __FSP_CONFIGS_H__\n+#define __FSP_CONFIGS_H__\n+\n+#ifndef __ASSEMBLY__\n+struct fsp_config_data {\n+\tstruct fsp_cfg_common\tcommon;\n+\tstruct upd_region\tfsp_upd;\n+};\n+\n+struct fspinit_rtbuf {\n+\tstruct common_buf\tcommon;\t/* FSP common runtime data structure */\n+};\n+#endif\n+\n+/* FSP user configuration settings */\n+\n+#define MRC_INIT_TSEG_SIZE_1MB\t\t1\n+#define MRC_INIT_TSEG_SIZE_2MB\t\t2\n+#define MRC_INIT_TSEG_SIZE_4MB\t\t4\n+#define MRC_INIT_TSEG_SIZE_8MB\t\t8\n+\n+#define MRC_INIT_MMIO_SIZE_1024MB\t0x400\n+#define MRC_INIT_MMIO_SIZE_1536MB\t0x600\n+#define MRC_INIT_MMIO_SIZE_2048MB\t0x800\n+\n+#define IGD_DVMT50_PRE_ALLOC_32MB\t0x01\n+#define IGD_DVMT50_PRE_ALLOC_64MB\t0x02\n+#define IGD_DVMT50_PRE_ALLOC_96MB\t0x03\n+#define IGD_DVMT50_PRE_ALLOC_128MB\t0x04\n+#define IGD_DVMT50_PRE_ALLOC_160MB\t0x05\n+#define IGD_DVMT50_PRE_ALLOC_192MB\t0x06\n+#define IGD_DVMT50_PRE_ALLOC_224MB\t0x07\n+#define IGD_DVMT50_PRE_ALLOC_256MB\t0x08\n+#define IGD_DVMT50_PRE_ALLOC_288MB\t0x09\n+#define IGD_DVMT50_PRE_ALLOC_320MB\t0x0a\n+#define IGD_DVMT50_PRE_ALLOC_352MB\t0x0b\n+#define IGD_DVMT50_PRE_ALLOC_384MB\t0x0c\n+#define IGD_DVMT50_PRE_ALLOC_416MB\t0x0d\n+#define IGD_DVMT50_PRE_ALLOC_448MB\t0x0e\n+#define IGD_DVMT50_PRE_ALLOC_480MB\t0x0f\n+#define IGD_DVMT50_PRE_ALLOC_512MB\t0x10\n+\n+#define APERTURE_SIZE_128MB\t\t1\n+#define APERTURE_SIZE_256MB\t\t2\n+#define APERTURE_SIZE_512MB\t\t3\n+\n+#define GTT_SIZE_1MB\t\t\t1\n+#define GTT_SIZE_2MB\t\t\t2\n+\n+#define DRAM_TYPE_DDR3\t\t\t0\n+#define DRAM_TYPE_LPDDR3\t\t1\n+\n+#define SDCARD_MODE_DISABLED\t\t0\n+#define SDCARD_MODE_PCI\t\t\t1\n+#define SDCARD_MODE_ACPI\t\t2\n+\n+#define LPE_MODE_DISABLED\t\t0\n+#define LPE_MODE_PCI\t\t\t1\n+#define LPE_MODE_ACPI\t\t\t2\n+\n+#define CHV_SVID_CONFIG_0\t\t0\n+#define CHV_SVID_CONFIG_1\t\t1\n+#define CHV_SVID_CONFIG_2\t\t2\n+#define CHV_SVID_CONFIG_3\t\t3\n+\n+#define EMMC_MODE_DISABLED\t\t0\n+#define EMMC_MODE_PCI\t\t\t1\n+#define EMMC_MODE_ACPI\t\t\t2\n+\n+#define SATA_SPEED_GEN1\t\t\t1\n+#define SATA_SPEED_GEN2\t\t\t2\n+#define SATA_SPEED_GEN3\t\t\t3\n+\n+#define ISP_PCI_DEV_CONFIG_1\t\t1\n+#define ISP_PCI_DEV_CONFIG_2\t\t2\n+#define ISP_PCI_DEV_CONFIG_3\t\t3\n+\n+#define PNP_SETTING_DISABLED\t\t0\n+#define PNP_SETTING_POWER\t\t1\n+#define PNP_SETTING_PERF\t\t2\n+#define PNP_SETTING_POWER_AND_PERF\t3\n+\n+#endif /* __FSP_CONFIGS_H__ */\ndiff --git a/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h\nnew file mode 100644\nindex 0000000..ecb01fa\n--- /dev/null\n+++ b/arch/x86/include/asm/arch-braswell/fsp/fsp_vpd.h\n@@ -0,0 +1,172 @@\n+/*\n+ * Copyright (C) 2015, Intel Corporation\n+ * Copyright (C) 2017, Bin Meng \n+ *\n+ * SPDX-License-Identifier:\tIntel\n+ */\n+\n+#ifndef __FSP_VPD_H__\n+#define __FSP_VPD_H__\n+\n+struct __packed memory_upd {\n+\tu64 signature;\t\t\t\t/* Offset 0x0020 */\n+\tu8 revision;\t\t\t\t/* Offset 0x0028 */\n+\tu8 unused2[7];\t\t\t\t/* Offset 0x0029 */\n+\tu16 mrc_init_tseg_size;\t\t\t/* Offset 0x0030 */\n+\tu16 mrc_init_mmio_size;\t\t\t/* Offset 0x0032 */\n+\tu8 mrc_init_spd_addr1;\t\t\t/* Offset 0x0034 */\n+\tu8 mrc_init_spd_addr2;\t\t\t/* Offset 0x0035 */\n+\tu8 mem_ch0_config;\t\t\t/* Offset 0x0036 */\n+\tu8 mem_ch1_config;\t\t\t/* Offset 0x0037 */\n+\tu32 memory_spd_ptr;\t\t\t/* Offset 0x0038 */\n+\tu8 igd_dvmt50_pre_alloc;\t\t/* Offset 0x003c */\n+\tu8 aperture_size;\t\t\t/* Offset 0x003d */\n+\tu8 gtt_size;\t\t\t\t/* Offset 0x003e */\n+\tu8 legacy_seg_decode;\t\t\t/* Offset 0x003f */\n+\tu8 enable_dvfs;\t\t\t\t/* Offset 0x0040 */\n+\tu8 memory_type;\t\t\t\t/* Offset 0x0041 */\n+\tu8 enable_ca_mirror;\t\t\t/* Offset 0x0042 */\n+\tu8 reserved[189];\t\t\t/* Offset 0x0043 */\n+};\n+\n+struct __packed azalia_verb_table_header {\n+\tu32 vendor_device_id;\n+\tu16 sub_system_id;\n+\tu8 revision_id;\n+\tu8 front_panel_support;\n+\tu16 number_of_rear_jacks;\n+\tu16 number_of_front_jacks;\n+};\n+\n+struct __packed azalia_verb_table {\n+\tstruct azalia_verb_table_header header;\n+\tu32 *data;\n+};\n+\n+struct __packed azalia_config {\n+\tu8 pme_enable:1;\n+\tu8 docking_supported:1;\n+\tu8 docking_attached:1;\n+\tu8 hdmi_codec_enable:1;\n+\tu8 azalia_v_ci_enable:1;\n+\tu8 reserved:3;\n+\tu8 verb_table_num;\n+\tstruct azalia_verb_table *verb_table;\n+\tu16 reset_wait_timer_ms;\n+};\n+\n+struct gpio_family {\n+\tu32 confg;\n+\tu32 confg_changes;\n+\tu32 misc;\n+\tu32 mmio_addr;\n+\twchar_t *name;\n+};\n+\n+struct gpio_pad {\n+\tu32 confg0;\n+\tu32 confg0_changes;\n+\tu32 confg1;\n+\tu32 confg1_changes;\n+\tu32 community;\n+\tu32 mmio_addr;\n+\twchar_t *name;\n+\tu32 misc;\n+};\n+\n+struct __packed silicon_upd {\n+\tu64 signature;\t\t\t\t/* Offset 0x0100 */\n+\tu8 revision;\t\t\t\t/* Offset 0x0108 */\n+\tu8 unused3[7];\t\t\t\t/* Offset 0x0109 */\n+\tu8 sdcard_mode;\t\t\t\t/* Offset 0x0110 */\n+\tu8 enable_hsuart0;\t\t\t/* Offset 0x0111 */\n+\tu8 enable_hsuart1;\t\t\t/* Offset 0x0112 */\n+\tu8 enable_azalia;\t\t\t/* Offset 0x0113 */\n+\tstruct azalia_config *azalia_cfg_ptr;\t/* Offset 0x0114 */\n+\tu8 enable_sata;\t\t\t\t/* Offset 0x0118 */\n+\tu8 enable_xhci;\t\t\t\t/* Offset 0x0119 */\n+\tu8 lpe_mode;\t\t\t\t/* Offset 0x011a */\n+\tu8 enable_dma0;\t\t\t\t/* Offset 0x011b */\n+\tu8 enable_dma1;\t\t\t\t/* Offset 0x011c */\n+\tu8 enable_i2c0;\t\t\t\t/* Offset 0x011d */\n+\tu8 enable_i2c1;\t\t\t\t/* Offset 0x011e */\n+\tu8 enable_i2c2;\t\t\t\t/* Offset 0x011f */\n+\tu8 enable_i2c3;\t\t\t\t/* Offset 0x0120 */\n+\tu8 enable_i2c4;\t\t\t\t/* Offset 0x0121 */\n+\tu8 enable_i2c5;\t\t\t\t/* Offset 0x0122 */\n+\tu8 enable_i2c6;\t\t\t\t/* Offset 0x0123 */\n+\tu32 graphics_config_ptr;\t\t/* Offset 0x0124 */\n+\tstruct gpio_family *gpio_familiy_ptr;\t/* Offset 0x0128 */\n+\tstruct gpio_pad *gpio_pad_ptr;\t\t/* Offset 0x012c */\n+\tu8 disable_punit_pwr_config;\t\t/* Offset 0x0130 */\n+\tu8 chv_svid_config;\t\t\t/* Offset 0x0131 */\n+\tu8 disable_dptf;\t\t\t/* Offset 0x0132 */\n+\tu8 emmc_mode;\t\t\t\t/* Offset 0x0133 */\n+\tu8 usb3_clk_ssc;\t\t\t/* Offset 0x0134 */\n+\tu8 disp_clk_ssc;\t\t\t/* Offset 0x0135 */\n+\tu8 sata_clk_ssc;\t\t\t/* Offset 0x0136 */\n+\tu8 usb2_port0_pe_txi_set;\t\t/* Offset 0x0137 */\n+\tu8 usb2_port0_txi_set;\t\t\t/* Offset 0x0138 */\n+\tu8 usb2_port0_tx_emphasis_en;\t\t/* Offset 0x0139 */\n+\tu8 usb2_port0_tx_pe_half;\t\t/* Offset 0x013a */\n+\tu8 usb2_port1_pe_txi_set;\t\t/* Offset 0x013b */\n+\tu8 usb2_port1_txi_set;\t\t\t/* Offset 0x013c */\n+\tu8 usb2_port1_tx_emphasis_en;\t\t/* Offset 0x013d */\n+\tu8 usb2_port1_tx_pe_half;\t\t/* Offset 0x013e */\n+\tu8 usb2_port2_pe_txi_set;\t\t/* Offset 0x013f */\n+\tu8 usb2_port2_txi_set;\t\t\t/* Offset 0x0140 */\n+\tu8 usb2_port2_tx_emphasis_en;\t\t/* Offset 0x0141 */\n+\tu8 usb2_port2_tx_pe_half;\t\t/* Offset 0x0142 */\n+\tu8 usb2_port3_pe_txi_set;\t\t/* Offset 0x0143 */\n+\tu8 usb2_port3_txi_set;\t\t\t/* Offset 0x0144 */\n+\tu8 usb2_port3_tx_emphasis_en;\t\t/* Offset 0x0145 */\n+\tu8 usb2_port3_tx_pe_half;\t\t/* Offset 0x0146 */\n+\tu8 usb2_port4_pe_txi_set;\t\t/* Offset 0x0147 */\n+\tu8 usb2_port4_txi_set;\t\t\t/* Offset 0x0148 */\n+\tu8 usb2_port4_tx_emphasis_en;\t\t/* Offset 0x0149 */\n+\tu8 usb2_port4_tx_pe_half;\t\t/* Offset 0x014a */\n+\tu8 usb3_lane0_ow2tap_gen2_deemph3p5;\t/* Offset 0x014b */\n+\tu8 usb3_lane1_ow2tap_gen2_deemph3p5;\t/* Offset 0x014c */\n+\tu8 usb3_lane2_ow2tap_gen2_deemph3p5;\t/* Offset 0x014d */\n+\tu8 usb3_lane3_ow2tap_gen2_deemph3p5;\t/* Offset 0x014e */\n+\tu8 sata_speed;\t\t\t\t/* Offset 0x014f */\n+\tu8 usb_ssic_port;\t\t\t/* Offset 0x0150 */\n+\tu8 usb_hsic_port;\t\t\t/* Offset 0x0151 */\n+\tu8 pcie_rootport_speed;\t\t\t/* Offset 0x0152 */\n+\tu8 enable_ssic;\t\t\t\t/* Offset 0x0153 */\n+\tu32 logo_ptr;\t\t\t\t/* Offset 0x0154 */\n+\tu32 logo_size;\t\t\t\t/* Offset 0x0158 */\n+\tu8 rtc_lock;\t\t\t\t/* Offset 0x015c */\n+\tu8 pmic_i2c_bus;\t\t\t/* Offset 0x015d */\n+\tu8 enable_isp;\t\t\t\t/* Offset 0x015e */\n+\tu8 isp_pci_dev_config;\t\t\t/* Offset 0x015f */\n+\tu8 turbo_mode;\t\t\t\t/* Offset 0x0160 */\n+\tu8 pnp_settings;\t\t\t/* Offset 0x0161 */\n+\tu8 sd_detect_chk;\t\t\t/* Offset 0x0162 */\n+\tu8 reserved[411];\t\t\t/* Offset 0x0163 */\n+};\n+\n+#define MEMORY_UPD_ID\t0x244450554d454d24\t/* '$MEMUPD$' */\n+#define SILICON_UPD_ID\t0x244450555f495324\t/* '$SI_UPD$' */\n+\n+struct __packed upd_region {\n+\tu64 signature;\t\t\t\t/* Offset 0x0000 */\n+\tu8 revision;\t\t\t\t/* Offset 0x0008 */\n+\tu8 unused0[7];\t\t\t\t/* Offset 0x0009 */\n+\tu32 memory_upd_offset;\t\t\t/* Offset 0x0010 */\n+\tu32 silicon_upd_offset;\t\t\t/* Offset 0x0014 */\n+\tu64 unused1;\t\t\t\t/* Offset 0x0018 */\n+\tstruct memory_upd memory_upd;\t\t/* Offset 0x0020 */\n+\tstruct silicon_upd silicon_upd;\t\t/* Offset 0x0100 */\n+\tu16 terminator;\t\t\t\t/* Offset 0x02fe */\n+};\n+\n+#define VPD_IMAGE_ID\t0x2450534657534224\t/* '$BSWFSP$' */\n+\n+struct __packed vpd_region {\n+\tu64 sign;\t\t\t\t/* Offset 0x0000 */\n+\tu32 img_rev;\t\t\t\t/* Offset 0x0008 */\n+\tu32 upd_offset;\t\t\t\t/* Offset 0x000c */\n+};\n+\n+#endif /* __FSP_VPD_H__ */\ndiff --git a/arch/x86/include/asm/arch-braswell/gpio.h b/arch/x86/include/asm/arch-braswell/gpio.h\nnew file mode 100644\nindex 0000000..ff82a27\n--- /dev/null\n+++ b/arch/x86/include/asm/arch-braswell/gpio.h\n@@ -0,0 +1,234 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng \n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ *\n+ * From coreboot src/soc/intel/braswell/include/soc/gpio.h\n+ */\n+\n+#ifndef _BRASWELL_GPIO_H_\n+#define _BRASWELL_GPIO_H_\n+\n+#include \n+\n+#define NA\t\t0xff\n+#define LOW\t\t0\n+#define HIGH\t\t1\n+#define MASK_WAKE\t0\n+#define UNMASK_WAKE\t1\n+\n+enum mode_list {\n+\tM0,\n+\tM1,\n+\tM2,\n+\tM3,\n+\tM4,\n+\tM5,\n+\tM6,\n+\tM7,\n+\tM8,\n+\tM9,\n+\tM10,\n+\tM11,\n+\tM12,\n+\tM13,\n+};\n+\n+enum int_select {\n+\tL0,\n+\tL1,\n+\tL2,\n+\tL3,\n+\tL4,\n+\tL5,\n+\tL6,\n+\tL7,\n+\tL8,\n+\tL9,\n+\tL10,\n+\tL11,\n+\tL12,\n+\tL13,\n+\tL14,\n+\tL15,\n+};\n+\n+enum int_type {\n+\tINT_DIS,\n+\tTRIG_EDGE_LOW,\n+\tTRIG_EDGE_HIGH,\n+\tTRIG_EDGE_BOTH,\n+\tTRIG_LEVEL,\n+};\n+\n+enum glitch_cfg {\n+\tGLITCH_DISABLE,\n+\tEN_EDGE_DETECT,\n+\tEN_RX_DATA,\n+\tEN_EDGE_RX_DATA,\n+};\n+\n+enum mask {\n+\tMASKABLE,\n+\tNON_MASKABLE,\n+};\n+\n+enum community {\n+\tSOUTHWEST = 0x0000,\n+\tNORTH = 0x8000,\n+\tEAST = 0x10000,\n+\tSOUTHEAST = 0x18000,\n+\tVIRTUAL = 0x20000,\n+};\n+\n+enum gpe_config {\n+\tGPE,\n+\tSMI,\n+\tSCI,\n+};\n+\n+enum inv_rx_tx {\n+\tNO_INVERSION = 0,\n+\tINV_RX_ENABLE = 1,\n+\tINV_TX_ENABLE = 2,\n+\tINV_RX_TX_ENABLE = 3,\n+\tINV_RX_DATA = 4,\n+\tINV_TX_DATA = 8,\n+};\n+\n+enum gpio_en {\n+\tNATIVE = 0xff,\n+\tGPIO = 0,\t/* Native, no need to set PAD_VALUE */\n+\tGPO = 1,\t/* GPO, output only in PAD_VALUE */\n+\tGPI = 2,\t/* GPI, input only in PAD_VALUE */\n+\tHI_Z = 3,\n+\tNA_GPO = 0,\n+};\n+\n+enum gpo_d4 {\n+\tLO,\n+\tHI,\n+};\n+\n+enum gpio_func_num {\n+\tF0,\n+\tF1,\n+\tF2,\n+\tF3,\n+};\n+\n+enum int_capable {\n+\t_CAP = 1,\n+\t_NOT_CAP = 0\n+};\n+\n+enum pull_type {\n+\tP_NONE = 0,\t/* Pull None */\n+\tP_20K_L = 1,\t/* Pull Down 20K */\n+\tP_5K_L = 2,\t/* Pull Down 5K */\n+\tP_1K_L = 4,\t/* Pull Down 1K */\n+\tP_20K_H = 9,\t/* Pull Up 20K */\n+\tP_5K_H = 10,\t/* Pull Up 5K */\n+\tP_1K_H = 12\t/* Pull Up 1K */\n+};\n+\n+enum park_mode_enb {\n+\tDISABLE,\t/* Disable */\n+\tENABLE,\t\t/* Enable */\n+};\n+\n+enum voltage {\n+\tVOLT_3_3,\t/* Working on 3.3 Volts */\n+\tVOLT_1_8,\t/* Working on 1.8 Volts */\n+};\n+\n+enum hs_mode {\n+\tDISABLE_HS,\t/* Disable high speed mode */\n+\tENABLE_HS,\t/* Enable high speed mode */\n+};\n+\n+enum odt_up_dn {\n+\tPULL_UP,\t/* On Die Termination Up */\n+\tPULL_DOWN,\t/* On Die Termination Down */\n+};\n+\n+enum odt_en {\n+\tDISABLE_OD,\t/* On Die Termination Disable */\n+\tENABLE_OD,\t/* On Die Termination Enable */\n+};\n+\n+enum bit {\n+\tONE_BIT = 1,\n+\tTWO_BIT = 3,\n+\tTHREE_BIT = 7,\n+\tFOUR_BIT = 15,\n+\tFIVE_BIT = 31,\n+\tSIX_BIT = 63,\n+\tSEVEN_BIT = 127,\n+\tEIGHT_BIT = 255\n+};\n+\n+#define TERMINATOR\t0xffffffff\n+\n+#define GPIO_FAMILY_CONF(family_name, park_mode, hysctl, vp18_mode, hs_mode, \\\n+\todt_up_dn, odt_en, curr_src_str, rcomp, family_no, community_offset) { \\\n+\t.confg = ((((park_mode) != NA) ? park_mode << 26 : 0) | \\\n+\t\t (((hysctl) != NA) ? hysctl << 24 : 0) | \\\n+\t\t (((vp18_mode) != NA) ? vp18_mode << 21 : 0) | \\\n+\t\t (((hs_mode) != NA) ? hs_mode << 19 : 0) | \\\n+\t\t (((odt_up_dn) != NA) ? odt_up_dn << 18 : 0) | \\\n+\t\t (((odt_en) != NA) ? odt_en << 17 : 0) | \\\n+\t\t (curr_src_str)), \\\n+\t.confg_changes = ((((park_mode) != NA) ? ONE_BIT << 26 : 0) | \\\n+\t\t\t (((hysctl) != NA) ? TWO_BIT << 24 : 0) | \\\n+\t\t\t (((vp18_mode) != NA) ? ONE_BIT << 21 : 0) | \\\n+\t\t\t (((hs_mode) != NA) ? ONE_BIT << 19 : 0) | \\\n+\t\t\t (((odt_up_dn) != NA) ? ONE_BIT << 18 : 0) | \\\n+\t\t\t (((odt_en) != NA) ? ONE_BIT << 17 : 0) | \\\n+\t\t\t (THREE_BIT)), \\\n+\t.misc = ((rcomp == ENABLE) ? 1 : 0) , \\\n+\t.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \\\n+\t\t ((family_no != NA) ? (IO_BASE_ADDRESS + community_offset +\\\n+\t\t (0x80 * family_no) + 0x1080) : 0) , \\\n+\t.name = 0 \\\n+}\n+\n+#define GPIO_PAD_CONF(pad_name, mode_select, mode, gpio_config, gpio_state, \\\n+\tgpio_light_mode, int_type, int_sel, term, open_drain, current_source,\\\n+\tint_mask, glitch, inv_rx_tx, wake_mask, wake_mask_bit, gpe, \\\n+\tmmio_offset, community_offset) { \\\n+\t.confg0 = ((((int_sel) != NA) ? (int_sel << 28) : 0) | \\\n+\t\t (((glitch) != NA) ? (glitch << 26) : 0) | \\\n+\t\t (((term) != NA) ? (term << 20) : 0) | \\\n+\t\t (((mode_select) == GPIO) ? ((mode << 16) | (1 << 15)) : \\\n+\t\t ((mode << 16))) | \\\n+\t\t (((gpio_config) != NA) ? (gpio_config << 8) : 0) | \\\n+\t\t (((gpio_light_mode) != NA) ? (gpio_light_mode << 7) : 0) | \\\n+\t\t (((gpio_state) == HIGH) ? 2 : 0)), \\\n+\t.confg0_changes = ((((int_sel) != NA) ? (FOUR_BIT << 28) : 0) | \\\n+\t\t\t (((glitch) != NA) ? (TWO_BIT << 26) : 0) | \\\n+\t\t\t (((term) != NA) ? (FOUR_BIT << 20) : 0) | \\\n+\t\t\t (FIVE_BIT << 15) | \\\n+\t\t\t (((gpio_config) != NA) ? (THREE_BIT << 8) : 0) | \\\n+\t\t\t (((gpio_light_mode) != NA) ? (ONE_BIT << 7) : 0) | \\\n+\t\t\t (((gpio_state) != NA) ? ONE_BIT << 1 : 0)), \\\n+\t.confg1 = ((((current_source) != NA) ? (current_source << 27) : 0) | \\\n+\t\t (((inv_rx_tx) != NA) ? inv_rx_tx << 4 : 0) | \\\n+\t\t (((open_drain) != NA) ? open_drain << 3 : 0) | \\\n+\t\t (((int_type) != NA) ? int_type : 0)), \\\n+\t.confg1_changes = ((((current_source) != NA) ? (ONE_BIT << 27) : 0) | \\\n+\t\t\t (((inv_rx_tx) != NA) ? FOUR_BIT << 4 : 0) | \\\n+\t\t\t (((open_drain) != NA) ? ONE_BIT << 3 : 0) | \\\n+\t\t\t (((int_type) != NA) ? THREE_BIT : 0)), \\\n+\t.community = community_offset, \\\n+\t.mmio_addr = (community_offset == TERMINATOR) ? TERMINATOR : \\\n+\t\t ((mmio_offset != NA) ? (IO_BASE_ADDRESS + \\\n+\t\t community_offset + mmio_offset) : 0), \\\n+\t.name = 0, \\\n+\t.misc = ((((gpe) != NA) ? (gpe << 0) : 0) | \\\n+\t\t (((wake_mask) != NA) ? (wake_mask << 2) : 0) | \\\n+\t\t (((int_mask) != NA) ? (int_mask << 3) : 0)) | \\\n+\t\t (((wake_mask_bit) != NA) ? (wake_mask_bit << 4) : (NA << 4)) \\\n+}\n+\n+#endif /* _BRASWELL_GPIO_H_ */\n","prefixes":["U-Boot","11/13"]}