{"id":801889,"url":"http://patchwork.ozlabs.org/api/1.2/patches/801889/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1502862122-14771-2-git-send-email-bmeng.cn@gmail.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1502862122-14771-2-git-send-email-bmeng.cn@gmail.com>","list_archive_url":null,"date":"2017-08-16T05:41:50","name":"[U-Boot,01/13] x86: tsc: Add Airmont reference clock values","commit_ref":"3df39ef10704e82a61972fe2f71b6ff4466b7724","pull_url":null,"state":"accepted","archived":false,"hash":"1b3b416c61b9fd540d8bd2be25f4940717c13434","submitter":{"id":64981,"url":"http://patchwork.ozlabs.org/api/1.2/people/64981/?format=json","name":"Bin Meng","email":"bmeng.cn@gmail.com"},"delegate":{"id":56520,"url":"http://patchwork.ozlabs.org/api/1.2/users/56520/?format=json","username":"bmeng","first_name":"Bin","last_name":"Meng","email":"bmeng.cn@gmail.com"},"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1502862122-14771-2-git-send-email-bmeng.cn@gmail.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/801889/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/801889/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "},"content":"Per the Intel 64 and IA-32 Architecture Software Developer's Manual,\nadd the reference clock for Intel Atom Processors based on the Airmont\nMicroarchitecture (Braswell).\n\nThis keeps in sync with Linux kernel commit:\n 6fcb41c: x86/tsc_msr: Add Airmont reference clock values\n\nSigned-off-by: Bin Meng \n---\n\n drivers/timer/tsc_timer.c | 17 ++++++++++-------\n 1 file changed, 10 insertions(+), 7 deletions(-)","diff":"diff --git a/drivers/timer/tsc_timer.c b/drivers/timer/tsc_timer.c\nindex 4d1fc9c..77040af 100644\n--- a/drivers/timer/tsc_timer.c\n+++ b/drivers/timer/tsc_timer.c\n@@ -18,7 +18,7 @@\n #include \n #include \n \n-#define MAX_NUM_FREQS\t8\n+#define MAX_NUM_FREQS\t9\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -40,17 +40,20 @@ struct freq_desc {\n \n static struct freq_desc freq_desc_tables[] = {\n \t/* PNW */\n-\t{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 } },\n+\t{ 6, 0x27, 0, { 0, 0, 0, 0, 0, 99840, 0, 83200, 0 } },\n \t/* CLV+ */\n-\t{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },\n+\t{ 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200, 0 } },\n \t/* TNG - Intel Atom processor Z3400 series */\n-\t{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },\n+\t{ 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0, 0 } },\n \t/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */\n-\t{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },\n+\t{ 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0, 0 } },\n \t/* ANN - Intel Atom processor Z3500 series */\n-\t{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } },\n+\t{ 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0, 0 } },\n+\t/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */\n+\t{ 6, 0x4c, 1, { 83300, 100000, 133300, 116700,\n+\t\t\t80000, 93300, 90000, 88900, 87500 } },\n \t/* Ivybridge */\n-\t{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },\n+\t{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0, 0 } },\n };\n \n static int match_cpu(u8 family, u8 model)\n","prefixes":["U-Boot","01/13"]}