{"id":784514,"url":"http://patchwork.ozlabs.org/api/1.2/patches/784514/?format=json","web_url":"http://patchwork.ozlabs.org/project/skiboot/patch/1499251121-19678-5-git-send-email-akshay.adiga@linux.vnet.ibm.com/","project":{"id":44,"url":"http://patchwork.ozlabs.org/api/1.2/projects/44/?format=json","name":"skiboot firmware development","link_name":"skiboot","list_id":"skiboot.lists.ozlabs.org","list_email":"skiboot@lists.ozlabs.org","web_url":"http://github.com/open-power/skiboot","scm_url":"http://github.com/open-power/skiboot","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<1499251121-19678-5-git-send-email-akshay.adiga@linux.vnet.ibm.com>","list_archive_url":null,"date":"2017-07-05T10:38:39","name":"[PATCHv2,4/6] SLW: Configure self-restore for HRMOR","commit_ref":null,"pull_url":null,"state":"superseded","archived":false,"hash":"7fb45f843d0db2b4ec090f339fd5646b671051b0","submitter":{"id":68766,"url":"http://patchwork.ozlabs.org/api/1.2/people/68766/?format=json","name":"Akshay Adiga","email":"akshay.adiga@linux.vnet.ibm.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/skiboot/patch/1499251121-19678-5-git-send-email-akshay.adiga@linux.vnet.ibm.com/mbox/","series":[],"comments":"http://patchwork.ozlabs.org/api/patches/784514/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/784514/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","skiboot@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@bilbo.ozlabs.org","skiboot@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3x2cn55VQzz9s2s\n\tfor ;\n\tWed, 5 Jul 2017 20:39:21 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3x2cn54pn4zDr3b\n\tfor ;\n\tWed, 5 Jul 2017 20:39:21 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3x2cmq3rNtzDqhn\n\tfor ; Wed, 5 Jul 2017 20:39:07 +1000 (AEST)","from pps.filterd (m0098414.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id\n\tv65Ad2Pm036012\n\tfor ; Wed, 5 Jul 2017 06:39:04 -0400","from e23smtp06.au.ibm.com (e23smtp06.au.ibm.com [202.81.31.148])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2bgvqjcv7p-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Wed, 05 Jul 2017 06:39:04 -0400","from localhost\n\tby e23smtp06.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tWed, 5 Jul 2017 20:38:59 +1000","from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139])\n\tby d23relay06.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv65Acxrt5833092\n\tfor ; Wed, 5 Jul 2017 20:38:59 +1000","from d23av04.au.ibm.com (localhost [127.0.0.1])\n\tby d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv65AcvtP024149\n\tfor ; Wed, 5 Jul 2017 20:38:57 +1000","from aksadiga.in.ibm.com (aksadiga.in.ibm.com [9.124.35.223])\n\tby d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tv65Aclu5023862; Wed, 5 Jul 2017 20:38:56 +1000"],"From":"Akshay Adiga ","To":"skiboot@lists.ozlabs.org","Date":"Wed, 5 Jul 2017 16:08:39 +0530","X-Mailer":"git-send-email 2.5.5","In-Reply-To":"<1499251121-19678-1-git-send-email-akshay.adiga@linux.vnet.ibm.com>","References":"<1499251121-19678-1-git-send-email-akshay.adiga@linux.vnet.ibm.com>","X-TM-AS-MML":"disable","x-cbid":"17070510-0040-0000-0000-0000033E7145","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17070510-0041-0000-0000-00000CB99C02","Message-Id":"<1499251121-19678-5-git-send-email-akshay.adiga@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-07-05_07:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1703280000\n\tdefinitions=main-1707050178","Subject":"[Skiboot] [PATCHv2 4/6] SLW: Configure self-restore for HRMOR","X-BeenThere":"skiboot@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Mailing list for skiboot development ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"ego@linux.vnet.ibm.com, shriyak@linux.vnet.ibm.com","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Errors-To":"skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org","Sender":"\"Skiboot\"\n\t"},"content":"Make a stop api call using libpore to restore HRMOR register. HRMOR needs\nto be cleared so that when thread exits stop, they arrives at linux\nsystem_reset vector (0x100).\n\nSigned-off-by: Akshay Adiga \n---\n hw/slw.c | 29 +++++++++++++++++++++++++++++\n 1 file changed, 29 insertions(+)","diff":"diff --git a/hw/slw.c b/hw/slw.c\nindex 4600279..c943d80 100644\n--- a/hw/slw.c\n+++ b/hw/slw.c\n@@ -1145,12 +1145,41 @@ static void slw_patch_regs(struct proc_chip *chip)\n static void slw_init_chip_p9(struct proc_chip *chip)\n {\n \tstruct cpu_thread *c;\n+\tint rc;\n \n \tprlog(PR_DEBUG, \"SLW: Init chip 0x%x\\n\", chip->id);\n \n \t/* At power ON setup inits for power-mgt */\n \tfor_each_available_core_in_chip(c, chip->id)\n \t\tslw_set_overrides_p9(chip, c);\n+\n+\tif (!chip->homer_base) {\n+\t\tlog_simple_error(&e_info(OPAL_RC_SLW_REG),\n+\t\t\t\t \"SLW: HOMER base not set %x\\n\",\n+\t\t\t\t chip->id);\n+\t\treturn;\n+\t}\n+\n+\tprlog(PR_NOTICE, \"SLW: Configuring self-restore for HRMOR\\n\");\n+\n+\t/* Should this be for_each_present_cpu() ? */\n+\tfor_each_available_cpu(c) {\n+\t\tif (c->chip_id != chip->id)\n+\t\t\tcontinue;\n+\n+\t\t/*\n+\t\t * Clear HRMOR. Need to update only for thread\n+\t\t * 0 of each core. Doing it anyway for all threads\n+\t\t */\n+\t\trc = p9_stop_save_cpureg((void *)chip->homer_base,\n+\t\t\t\t\t\tP9_STOP_SPR_HRMOR, 0,\n+\t\t\t\t\t c->pir);\n+\t\tif (rc) {\n+\t\t\tlog_simple_error(&e_info(OPAL_RC_SLW_REG),\n+\t\t\t\t \"SLW: Failed to set HRMOR for CPU %x,RC=0x%x\\n\",\n+\t\t\t\t c->pir, rc);\n+\t\t}\n+\t}\n }\n static void slw_init_chip(struct proc_chip *chip)\n {\n","prefixes":["PATCHv2","4/6"]}