{"id":2235249,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235249/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/c964c8cc4075a5f331a3dd108f103302bcbcc365.1778277334.git.aidan@wolfssl.com/","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/1.2/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2026-05-09T00:04:16","name":"[v3,09/12] tpm: add sandbox TPM SPI emulator","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"0b94c6cbba259a0806718c3fd629893ac3d1b3fa","submitter":{"id":92785,"url":"http://patchwork.ozlabs.org/api/1.2/people/92785/?format=json","name":"Aidan Garske","email":"aidan@wolfssl.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/uboot/patch/c964c8cc4075a5f331a3dd108f103302bcbcc365.1778277334.git.aidan@wolfssl.com/mbox/","series":[{"id":503464,"url":"http://patchwork.ozlabs.org/api/1.2/series/503464/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=503464","date":"2026-05-09T00:04:07","name":"tpm: Add wolfTPM library support for TPM 2.0","version":3,"mbox":"http://patchwork.ozlabs.org/series/503464/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235249/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235249/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=wolfssl-com.20251104.gappssmtp.com\n header.i=@wolfssl-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=tOKYPyES;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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This allows non-flash SPI\n devices (like the TPM emulator) to specify their own emulator\n via device tree phandle.\n\nSigned-off-by: Aidan Garske \n---\n drivers/mtd/spi/sandbox.c | 30 ++-\n drivers/tpm/tpm_spi_sandbox.c | 410 ++++++++++++++++++++++++++++++++++\n 2 files changed, 431 insertions(+), 9 deletions(-)\n create mode 100644 drivers/tpm/tpm_spi_sandbox.c","diff":"diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c\nindex e5ebc3479fb..41bd07817aa 100644\n--- a/drivers/mtd/spi/sandbox.c\n+++ b/drivers/mtd/spi/sandbox.c\n@@ -571,16 +571,28 @@ int sandbox_spi_get_emul(struct sandbox_state *state,\n \n \tinfo = &state->spi[busnum][cs];\n \tif (!info->emul) {\n-\t\t/* Use the same device tree node as the SPI flash device */\n-\t\tdebug(\"%s: busnum=%u, cs=%u: binding SPI flash emulation: \",\n-\t\t __func__, busnum, cs);\n-\t\tret = sandbox_sf_bind_emul(state, busnum, cs, bus,\n-\t\t\t\t\t dev_ofnode(slave), slave->name);\n-\t\tif (ret) {\n-\t\t\tdebug(\"failed (err=%d)\\n\", ret);\n-\t\t\treturn ret;\n+\t\tstruct udevice *emul;\n+\t\tofnode node = dev_ofnode(slave);\n+\n+\t\t/* First check for sandbox,emul phandle property */\n+\t\tret = uclass_get_device_by_phandle(UCLASS_SPI_EMUL, slave,\n+\t\t\t\t\t\t \"sandbox,emul\", &emul);\n+\t\tif (!ret) {\n+\t\t\tdebug(\"%s: busnum=%u, cs=%u: using phandle emulator\\n\",\n+\t\t\t __func__, busnum, cs);\n+\t\t\tinfo->emul = emul;\n+\t\t} else {\n+\t\t\t/* Fall back to SPI flash emulation binding */\n+\t\t\tdebug(\"%s: busnum=%u, cs=%u: binding SPI flash emulation: \",\n+\t\t\t __func__, busnum, cs);\n+\t\t\tret = sandbox_sf_bind_emul(state, busnum, cs, bus,\n+\t\t\t\t\t\t node, slave->name);\n+\t\t\tif (ret) {\n+\t\t\t\tdebug(\"failed (err=%d)\\n\", ret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t\tdebug(\"OK\\n\");\n \t\t}\n-\t\tdebug(\"OK\\n\");\n \t}\n \t*emulp = info->emul;\n \ndiff --git a/drivers/tpm/tpm_spi_sandbox.c b/drivers/tpm/tpm_spi_sandbox.c\nnew file mode 100644\nindex 00000000000..694c5d721f0\n--- /dev/null\n+++ b/drivers/tpm/tpm_spi_sandbox.c\n@@ -0,0 +1,410 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Sandbox TPM SPI Emulator\n+ *\n+ * Copyright (c) 2025 wolfSSL Inc.\n+ * Author: Aidan Garske \n+ *\n+ * Emulates TPM TIS SPI protocol for testing wolfTPM SPI HAL\n+ * without hardware. Wraps the existing sandbox TPM2 state machine.\n+ */\n+\n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+#include \n+\n+/* TIS register addresses (locality 0) */\n+#define TPM_ACCESS_REG\t\t0x0000\n+#define TPM_INT_ENABLE_REG\t0x0008\n+#define TPM_INTF_CAPS_REG\t0x0014\n+#define TPM_STS_REG\t\t0x0018\n+#define TPM_DATA_FIFO_REG\t0x0024\n+#define TPM_DID_VID_REG\t\t0x0F00\n+#define TPM_RID_REG\t\t0x0F04\n+\n+/* TIS access register bits */\n+#define TPM_ACCESS_VALID\t\t0x80\n+#define TPM_ACCESS_ACTIVE_LOCALITY\t0x20\n+#define TPM_ACCESS_REQUEST_PENDING\t0x04\n+#define TPM_ACCESS_REQUEST_USE\t\t0x02\n+\n+/* TIS status register bits */\n+#define TPM_STS_VALID\t\t0x80\n+#define TPM_STS_COMMAND_READY\t0x40\n+#define TPM_STS_GO\t\t0x20\n+#define TPM_STS_DATA_AVAIL\t0x10\n+#define TPM_STS_DATA_EXPECT\t0x08\n+\n+/* Interface capabilities */\n+#define TPM_INTF_CAPS_VALUE\t0x30000697 /* Typical Infineon value */\n+\n+/* Device/Vendor ID - Infineon SLB9670 */\n+#define TPM_DID_VID_VALUE\t0x001D15D1\n+\n+/* Revision ID */\n+#define TPM_RID_VALUE\t\t0x36\n+\n+/* Maximum buffer sizes */\n+#define TPM_CMD_BUF_SIZE\t4096\n+#define TPM_RSP_BUF_SIZE\t4096\n+#define MAX_SPI_FRAMESIZE\t64\n+\n+/* TPM TIS SPI protocol states */\n+enum tpm_spi_state {\n+\tTPM_SPI_IDLE,\n+\tTPM_SPI_HEADER,\t\t/* Receiving 4-byte header */\n+\tTPM_SPI_WAIT_STATE,\t/* Sending wait state bytes */\n+\tTPM_SPI_DATA,\t\t/* Transfer data */\n+};\n+\n+/* TIS state machine */\n+enum tpm_tis_state {\n+\tTIS_IDLE,\n+\tTIS_READY,\t\t/* Ready to receive command */\n+\tTIS_RECEPTION,\t\t/* Receiving command data */\n+\tTIS_EXECUTION,\t\t/* Executing command */\n+\tTIS_COMPLETION,\t\t/* Response available */\n+};\n+\n+struct sandbox_tpm_spi {\n+\t/* SPI protocol state */\n+\tenum tpm_spi_state spi_state;\n+\tu8 header[4];\n+\tint header_pos;\n+\tbool is_read;\n+\tu32 addr;\n+\tint xfer_len;\n+\tint data_pos;\n+\n+\t/* TIS state */\n+\tenum tpm_tis_state tis_state;\n+\tu8 access_reg;\n+\tu32 sts_reg;\n+\tu32 intf_caps;\n+\n+\t/* Command/response buffers */\n+\tu8 cmd_buf[TPM_CMD_BUF_SIZE];\n+\tint cmd_len;\n+\tint cmd_pos;\n+\tu8 rsp_buf[TPM_RSP_BUF_SIZE];\n+\tint rsp_len;\n+\tint rsp_pos;\n+\n+\t/* Burst count for status register */\n+\tu16 burst_count;\n+};\n+\n+/*\n+ * Parse TIS SPI header\n+ * Format: [R/W|len-1][0xD4][addr_hi][addr_lo]\n+ * Bit 7 of byte 0: 1=read, 0=write\n+ * Bits 5:0 of byte 0: transfer length - 1\n+ */\n+static void parse_spi_header(struct sandbox_tpm_spi *priv)\n+{\n+\tpriv->is_read = (priv->header[0] & 0x80) != 0;\n+\tpriv->xfer_len = (priv->header[0] & 0x3F) + 1;\n+\tpriv->addr = (priv->header[2] << 8) | priv->header[3];\n+\tpriv->data_pos = 0;\n+}\n+\n+/*\n+ * Read from TIS register\n+ */\n+static u8 tis_reg_read(struct sandbox_tpm_spi *priv, u32 addr)\n+{\n+\tu32 reg = addr & 0x0FFF; /* Mask off locality bits */\n+\n+\tswitch (reg) {\n+\tcase TPM_ACCESS_REG:\n+\t\treturn priv->access_reg;\n+\n+\tcase TPM_STS_REG:\n+\tcase TPM_STS_REG + 1:\n+\tcase TPM_STS_REG + 2:\n+\tcase TPM_STS_REG + 3: {\n+\t\tint byte_off = reg - TPM_STS_REG;\n+\t\tu32 sts = priv->sts_reg;\n+\n+\t\t/* Update burst count in status */\n+\t\tsts |= ((u32)priv->burst_count << 8);\n+\t\treturn (sts >> (byte_off * 8)) & 0xFF;\n+\t}\n+\n+\tcase TPM_INTF_CAPS_REG:\n+\tcase TPM_INTF_CAPS_REG + 1:\n+\tcase TPM_INTF_CAPS_REG + 2:\n+\tcase TPM_INTF_CAPS_REG + 3: {\n+\t\tint byte_off = reg - TPM_INTF_CAPS_REG;\n+\n+\t\treturn (priv->intf_caps >> (byte_off * 8)) & 0xFF;\n+\t}\n+\n+\tcase TPM_DID_VID_REG:\n+\tcase TPM_DID_VID_REG + 1:\n+\tcase TPM_DID_VID_REG + 2:\n+\tcase TPM_DID_VID_REG + 3: {\n+\t\tint byte_off = reg - TPM_DID_VID_REG;\n+\n+\t\treturn (TPM_DID_VID_VALUE >> (byte_off * 8)) & 0xFF;\n+\t}\n+\n+\tcase TPM_RID_REG:\n+\t\treturn TPM_RID_VALUE;\n+\n+\tdefault:\n+\t\t/*\n+\t\t * Handle FIFO reads - the FIFO can be accessed at any address\n+\t\t * from 0x0024 up to 0x0F00 for multi-byte transfers.\n+\t\t */\n+\t\tif (reg >= TPM_DATA_FIFO_REG && reg < TPM_DID_VID_REG) {\n+\t\t\tif (priv->tis_state == TIS_COMPLETION &&\n+\t\t\t priv->rsp_pos < priv->rsp_len) {\n+\t\t\t\tu8 data = priv->rsp_buf[priv->rsp_pos++];\n+\n+\t\t\t\t/* Update status when all data read */\n+\t\t\t\tif (priv->rsp_pos >= priv->rsp_len) {\n+\t\t\t\t\tpriv->sts_reg &= ~TPM_STS_DATA_AVAIL;\n+\t\t\t\t\tpriv->sts_reg |= TPM_STS_COMMAND_READY;\n+\t\t\t\t\tpriv->tis_state = TIS_READY;\n+\t\t\t\t}\n+\t\t\t\treturn data;\n+\t\t\t}\n+\t\t\treturn 0xFF;\n+\t\t}\n+\t\treturn 0xFF;\n+\t}\n+}\n+\n+/*\n+ * Write to TIS register\n+ */\n+static void tis_reg_write(struct sandbox_tpm_spi *priv, u32 addr, u8 value)\n+{\n+\tu32 reg = addr & 0x0FFF;\n+\n+\tswitch (reg) {\n+\tcase TPM_ACCESS_REG:\n+\t\tif (value & TPM_ACCESS_REQUEST_USE) {\n+\t\t\t/* Request locality */\n+\t\t\tpriv->access_reg |= TPM_ACCESS_ACTIVE_LOCALITY;\n+\t\t\tpriv->access_reg |= TPM_ACCESS_VALID;\n+\t\t}\n+\t\tbreak;\n+\n+\tcase TPM_STS_REG:\n+\t\tif (value & TPM_STS_COMMAND_READY) {\n+\t\t\t/* Abort current command and go to ready state */\n+\t\t\tpriv->tis_state = TIS_READY;\n+\t\t\tpriv->cmd_len = 0;\n+\t\t\tpriv->cmd_pos = 0;\n+\t\t\tpriv->rsp_len = 0;\n+\t\t\tpriv->rsp_pos = 0;\n+\t\t\tpriv->sts_reg = TPM_STS_VALID | TPM_STS_COMMAND_READY;\n+\t\t\tpriv->burst_count = MAX_SPI_FRAMESIZE;\n+\t\t}\n+\t\tif (value & TPM_STS_GO) {\n+\t\t\t/* Execute command */\n+\t\t\tif (priv->tis_state == TIS_RECEPTION &&\n+\t\t\t priv->cmd_len > 0) {\n+\t\t\t\t/*\n+\t\t\t\t * Generate a simple success response.\n+\t\t\t\t * A full implementation would call the\n+\t\t\t\t * sandbox TPM2 state machine here.\n+\t\t\t\t */\n+\t\t\t\tpriv->rsp_buf[0] = 0x80; /* TPM_ST_NO_SESSIONS */\n+\t\t\t\tpriv->rsp_buf[1] = 0x01;\n+\t\t\t\tpriv->rsp_buf[2] = 0x00; /* Response size: 10 */\n+\t\t\t\tpriv->rsp_buf[3] = 0x00;\n+\t\t\t\tpriv->rsp_buf[4] = 0x00;\n+\t\t\t\tpriv->rsp_buf[5] = 0x0A;\n+\t\t\t\tpriv->rsp_buf[6] = 0x00; /* TPM_RC_SUCCESS */\n+\t\t\t\tpriv->rsp_buf[7] = 0x00;\n+\t\t\t\tpriv->rsp_buf[8] = 0x00;\n+\t\t\t\tpriv->rsp_buf[9] = 0x00;\n+\t\t\t\tpriv->rsp_len = 10;\n+\t\t\t\tpriv->rsp_pos = 0;\n+\n+\t\t\t\tpriv->tis_state = TIS_COMPLETION;\n+\t\t\t\tpriv->sts_reg = TPM_STS_VALID |\n+\t\t\t\t\t\tTPM_STS_DATA_AVAIL;\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\n+\tdefault:\n+\t\t/*\n+\t\t * Handle FIFO writes - the FIFO is at 0x0024 but any address\n+\t\t * from 0x0024 up to 0x0F00 can be used for FIFO access when\n+\t\t * doing multi-byte transfers (address auto-increments).\n+\t\t */\n+\t\tif (reg >= TPM_DATA_FIFO_REG && reg < TPM_DID_VID_REG) {\n+\t\t\tif (priv->tis_state == TIS_READY) {\n+\t\t\t\t/* Start receiving command */\n+\t\t\t\tpriv->tis_state = TIS_RECEPTION;\n+\t\t\t\tpriv->cmd_len = 0;\n+\t\t\t\tpriv->cmd_pos = 0;\n+\t\t\t\tpriv->sts_reg = TPM_STS_VALID | TPM_STS_DATA_EXPECT;\n+\t\t\t}\n+\t\t\tif (priv->tis_state == TIS_RECEPTION) {\n+\t\t\t\tif (priv->cmd_len < TPM_CMD_BUF_SIZE) {\n+\t\t\t\t\tpriv->cmd_buf[priv->cmd_len++] = value;\n+\n+\t\t\t\t\t/* Check if we have complete command */\n+\t\t\t\t\tif (priv->cmd_len >= 6) {\n+\t\t\t\t\t\tu32 expected_len;\n+\n+\t\t\t\t\t\texpected_len = (priv->cmd_buf[2] << 24) |\n+\t\t\t\t\t\t\t (priv->cmd_buf[3] << 16) |\n+\t\t\t\t\t\t\t (priv->cmd_buf[4] << 8) |\n+\t\t\t\t\t\t\t priv->cmd_buf[5];\n+\t\t\t\t\t\tif (priv->cmd_len >= expected_len) {\n+\t\t\t\t\t\t\t/* Command complete */\n+\t\t\t\t\t\t\tpriv->sts_reg &=\n+\t\t\t\t\t\t\t\t~TPM_STS_DATA_EXPECT;\n+\t\t\t\t\t\t}\n+\t\t\t\t\t}\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\t\tbreak;\n+\t}\n+}\n+\n+/*\n+ * SPI emulation transfer callback\n+ */\n+static int sandbox_tpm_spi_xfer(struct udevice *dev, unsigned int bitlen,\n+\t\t\t\tconst void *dout, void *din, unsigned long flags)\n+{\n+\tstruct sandbox_tpm_spi *priv = dev_get_priv(dev);\n+\tint bytes = bitlen / 8;\n+\tconst u8 *tx = dout;\n+\tu8 *rx = din;\n+\tint i;\n+\n+\t/* Handle CS assert - reset state machine */\n+\tif (flags & SPI_XFER_BEGIN) {\n+\t\tpriv->spi_state = TPM_SPI_HEADER;\n+\t\tpriv->header_pos = 0;\n+\t}\n+\n+\tfor (i = 0; i < bytes; i++) {\n+\t\tu8 tx_byte = tx ? tx[i] : 0;\n+\t\tu8 rx_byte = 0;\n+\n+\t\tswitch (priv->spi_state) {\n+\t\tcase TPM_SPI_IDLE:\n+\t\t\t/* Should not happen during active transfer */\n+\t\t\trx_byte = 0xFF;\n+\t\t\tbreak;\n+\n+\t\tcase TPM_SPI_HEADER:\n+\t\t\t/* Receive 4-byte header */\n+\t\t\tpriv->header[priv->header_pos++] = tx_byte;\n+\t\t\trx_byte = 0x00;\n+\n+\t\t\tif (priv->header_pos >= 4) {\n+\t\t\t\tparse_spi_header(priv);\n+\t\t\t\tlog_debug(\"TPM SPI: %s len=%d addr=0x%04x\\n\",\n+\t\t\t\t\t priv->is_read ? \"read\" : \"write\",\n+\t\t\t\t\t priv->xfer_len, priv->addr);\n+\t\t\t\t/* Return wait state in last header byte */\n+\t\t\t\trx_byte = 0x01; /* Ready immediately */\n+\t\t\t\tpriv->spi_state = TPM_SPI_DATA;\n+\t\t\t}\n+\t\t\tbreak;\n+\n+\t\tcase TPM_SPI_DATA:\n+\t\t\tif (priv->is_read) {\n+\t\t\t\t/* Read from TPM register */\n+\t\t\t\trx_byte = tis_reg_read(priv,\n+\t\t\t\t\t\t priv->addr + priv->data_pos);\n+\t\t\t} else {\n+\t\t\t\t/* Write to TPM register */\n+\t\t\t\ttis_reg_write(priv, priv->addr + priv->data_pos,\n+\t\t\t\t\t tx_byte);\n+\t\t\t\trx_byte = 0x00;\n+\t\t\t}\n+\t\t\tpriv->data_pos++;\n+\t\t\tbreak;\n+\n+\t\tdefault:\n+\t\t\trx_byte = 0xFF;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (rx)\n+\t\t\trx[i] = rx_byte;\n+\t}\n+\n+\t/* Handle CS deassert - return to idle */\n+\tif (flags & SPI_XFER_END)\n+\t\tpriv->spi_state = TPM_SPI_IDLE;\n+\n+\treturn 0;\n+}\n+\n+static int sandbox_tpm_spi_probe(struct udevice *dev)\n+{\n+\tstruct sandbox_tpm_spi *priv = dev_get_priv(dev);\n+\n+\t/* Initialize TIS state */\n+\tpriv->spi_state = TPM_SPI_IDLE;\n+\tpriv->tis_state = TIS_IDLE;\n+\tpriv->access_reg = TPM_ACCESS_VALID;\n+\tpriv->sts_reg = TPM_STS_VALID;\n+\tpriv->intf_caps = TPM_INTF_CAPS_VALUE;\n+\tpriv->burst_count = MAX_SPI_FRAMESIZE;\n+\tpriv->cmd_len = 0;\n+\tpriv->rsp_len = 0;\n+\n+\tlog_debug(\"TPM SPI sandbox emulator probed\\n\");\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_spi_emul_ops sandbox_tpm_spi_ops = {\n+\t.xfer = sandbox_tpm_spi_xfer,\n+};\n+\n+static const struct udevice_id sandbox_tpm_spi_ids[] = {\n+\t{ .compatible = \"sandbox,tpm-spi-emul\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(sandbox_tpm_spi_emul) = {\n+\t.name = \"sandbox_tpm_spi_emul\",\n+\t.id = UCLASS_SPI_EMUL,\n+\t.of_match = sandbox_tpm_spi_ids,\n+\t.ops = &sandbox_tpm_spi_ops,\n+\t.probe = sandbox_tpm_spi_probe,\n+\t.priv_auto = sizeof(struct sandbox_tpm_spi),\n+};\n+\n+/*\n+ * SPI slave driver for TPM device\n+ * This gets probed when a device with \"sandbox,tpm-spi\" is found in DTS.\n+ * The actual SPI transfers are handled by the emulator above.\n+ */\n+static int sandbox_tpm_spi_slave_probe(struct udevice *dev)\n+{\n+\tlog_debug(\"TPM SPI slave device probed\\n\");\n+\treturn 0;\n+}\n+\n+static const struct udevice_id sandbox_tpm_spi_slave_ids[] = {\n+\t{ .compatible = \"sandbox,tpm-spi\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(sandbox_tpm_spi) = {\n+\t.name = \"sandbox_tpm_spi\",\n+\t.id = UCLASS_SPI_GENERIC,\n+\t.of_match = sandbox_tpm_spi_slave_ids,\n+\t.probe = sandbox_tpm_spi_slave_probe,\n+};\n","prefixes":["v3","09/12"]}