{"id":2235163,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235163/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-3-tdave@nvidia.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508183717.193630-3-tdave@nvidia.com>","list_archive_url":null,"date":"2026-05-08T18:37:11","name":"[RFC,2/8] hw/pci: enumerate PCI bus and program bridge bus numbers","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"9c450aa462da4c858f844896a31188a244d3b962","submitter":{"id":89928,"url":"http://patchwork.ozlabs.org/api/1.2/people/89928/?format=json","name":"Tushar Dave","email":"tdave@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508183717.193630-3-tdave@nvidia.com/mbox/","series":[{"id":503429,"url":"http://patchwork.ozlabs.org/api/1.2/series/503429/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503429","date":"2026-05-08T18:37:09","name":"hw/arm/virt, hw/pci: PCI pre-enumeration and fixed BAR allocation","version":1,"mbox":"http://patchwork.ozlabs.org/series/503429/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235163/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235163/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=CDlF19tL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Walk the hierarchy\nunder the root bus, assign secondary bus numbers in firmware-like\norder (PXB roots first by bus number, then PCI bridges by devfn),\nand program those bridge registers.\n\nNote that SR-IOV bus number allocation (VF offset/stride/NumVFs) is not\nhandled in this commit and requires additional work.\n\nSigned-off-by: Tushar Dave \n---\n hw/pci/meson.build | 1 +\n hw/pci/pci-enumerate.c | 144 +++++++++++++++++++++++++++++++++++++++++\n hw/pci/pci-enumerate.h | 15 +++++\n 3 files changed, 160 insertions(+)\n create mode 100644 hw/pci/pci-enumerate.c\n create mode 100644 hw/pci/pci-enumerate.h","diff":"diff --git a/hw/pci/meson.build b/hw/pci/meson.build\nindex a6cbd89c0a..7e8f5bb87d 100644\n--- a/hw/pci/meson.build\n+++ b/hw/pci/meson.build\n@@ -5,6 +5,7 @@ pci_ss.add(files(\n 'pci.c',\n 'pci_bridge.c',\n 'pci_host.c',\n+ 'pci-enumerate.c',\n 'pci-hmp-cmds.c',\n 'pci-qmp-cmds.c',\n 'pcie_sriov.c',\ndiff --git a/hw/pci/pci-enumerate.c b/hw/pci/pci-enumerate.c\nnew file mode 100644\nindex 0000000000..2c6d25b25d\n--- /dev/null\n+++ b/hw/pci/pci-enumerate.c\n@@ -0,0 +1,144 @@\n+/*\n+ * Copyright (C) 2026 NVIDIA\n+ * Written by Tushar Dave\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/pci/pci.h\"\n+#include \"hw/pci/pci_bridge.h\"\n+#include \"hw/pci/pci_bus.h\"\n+#include \"hw/pci/pci-enumerate.h\"\n+\n+/* Forward declaration */\n+static uint8_t pci_program_bus_numbers(PCIBus *bus, uint8_t current_bus_num,\n+ uint8_t *next_bus_num);\n+\n+static int cmp_bus_by_devfn(gconstpointer a, gconstpointer b)\n+{\n+ PCIBus *bus_a = *(PCIBus * const *)a;\n+ PCIBus *bus_b = *(PCIBus * const *)b;\n+ return (int)bus_a->parent_dev->devfn - (int)bus_b->parent_dev->devfn;\n+}\n+\n+static int cmp_bus_by_num(gconstpointer a, gconstpointer b)\n+{\n+ PCIBus *bus_a = *(PCIBus * const *)a;\n+ PCIBus *bus_b = *(PCIBus * const *)b;\n+ return pci_bus_num(bus_a) - pci_bus_num(bus_b);\n+}\n+\n+/*\n+ * Program one bridge's primary, secondary and subordinate bus numbers\n+ * and recurse. Return the max subordinate bus number.\n+ */\n+static uint8_t pci_program_bridge(PCIDevice *bridge, PCIBus *child_bus,\n+ uint8_t current_bus_num,\n+ uint8_t *next_bus_num)\n+{\n+ uint8_t secondary, max_child;\n+\n+ /* Bus number space exhausted; no bus number to assign. */\n+ if (*next_bus_num == 0) {\n+ return current_bus_num;\n+ }\n+ secondary = *next_bus_num;\n+ (*next_bus_num)++;\n+\n+ pci_default_write_config(bridge, PCI_PRIMARY_BUS, current_bus_num, 1);\n+ pci_default_write_config(bridge, PCI_SECONDARY_BUS, secondary, 1);\n+ /*\n+ * Unlike real hardware, QEMU does not require opening a subordinate\n+ * aperture before scanning downstream devices. Write secondary as\n+ * a placeholder; the final value is set after recursion below.\n+ */\n+ pci_default_write_config(bridge, PCI_SUBORDINATE_BUS, secondary, 1);\n+\n+ max_child = pci_program_bus_numbers(child_bus, secondary, next_bus_num);\n+ pci_default_write_config(bridge, PCI_SUBORDINATE_BUS, max_child, 1);\n+ return max_child;\n+}\n+\n+/*\n+ * Program bus numbers for this bus and all subordinates.\n+ * - current_bus_num: this bus' number (0 for root, or already set for PXB).\n+ * - next_bus_num: next free bus number to assign to a bridge.\n+ *\n+ * Children come from bus->child only. Two kinds:\n+ * 1) PXB (extra root): child has PCI_BUS_IS_ROOT. Has bus number\n+ * already set, recurse only.\n+ * 2) Normal bridge: parent is IS_PCI_BRIDGE. Assign secondary = *next_bus_num,\n+ * program primary, secondary and subordinate bus numbers, and recurse.\n+ *\n+ * Order matches EDK2 PciBusDxe enumeration: process PXB children first\n+ * (sorted by bus number), then bridges (sorted by devfn).\n+ */\n+static uint8_t pci_program_bus_numbers(PCIBus *bus, uint8_t current_bus_num,\n+ uint8_t *next_bus_num)\n+{\n+ PCIBus *child_bus;\n+ GArray *pxb_buses = g_array_new(false, false, sizeof(PCIBus *));\n+ GArray *bridges = g_array_new(false, false, sizeof(PCIBus *));\n+ uint8_t max_subordinate = current_bus_num;\n+ uint8_t child_num;\n+ uint8_t one_max;\n+ guint i;\n+\n+ /* Single pass over bus->child: split into PXB vs bridge */\n+ QLIST_FOREACH(child_bus, &bus->child, sibling) {\n+ if (!child_bus->parent_dev) {\n+ continue;\n+ }\n+ if (pci_bus_is_root(child_bus)) {\n+ /* PXB or similar: bus number already set (e.g. bus_nr=1, 9) */\n+ g_array_append_val(pxb_buses, child_bus);\n+ } else if (IS_PCI_BRIDGE(child_bus->parent_dev)) {\n+ g_array_append_val(bridges, child_bus);\n+ }\n+ }\n+\n+ /* PXB first, sorted by bus number (e.g. 1 before 9) */\n+ if (pxb_buses->len > 1) {\n+ g_array_sort(pxb_buses, cmp_bus_by_num);\n+ }\n+ for (i = 0; i < pxb_buses->len; i++) {\n+ child_bus = g_array_index(pxb_buses, PCIBus *, i);\n+ child_num = (uint8_t)pci_bus_num(child_bus);\n+ if (child_num + 1 > *next_bus_num) {\n+ *next_bus_num = child_num + 1;\n+ }\n+ one_max = pci_program_bus_numbers(child_bus, child_num, next_bus_num);\n+ if (one_max > max_subordinate) {\n+ max_subordinate = one_max;\n+ }\n+ }\n+ g_array_free(pxb_buses, true);\n+\n+ /* Bridges second, sorted by devfn */\n+ if (bridges->len > 1) {\n+ g_array_sort(bridges, cmp_bus_by_devfn);\n+ }\n+ for (i = 0; i < bridges->len; i++) {\n+ child_bus = g_array_index(bridges, PCIBus *, i);\n+ one_max = pci_program_bridge(child_bus->parent_dev, child_bus,\n+ current_bus_num, next_bus_num);\n+ if (one_max > max_subordinate) {\n+ max_subordinate = one_max;\n+ }\n+ }\n+ g_array_free(bridges, true);\n+\n+ return max_subordinate;\n+}\n+\n+void pci_enumerate_bus(PCIBus *root_bus)\n+{\n+ uint8_t next_bus_num;\n+\n+ if (!root_bus) {\n+ return;\n+ }\n+ next_bus_num = 1;\n+ pci_program_bus_numbers(root_bus, 0, &next_bus_num);\n+}\ndiff --git a/hw/pci/pci-enumerate.h b/hw/pci/pci-enumerate.h\nnew file mode 100644\nindex 0000000000..b1e4b989f1\n--- /dev/null\n+++ b/hw/pci/pci-enumerate.h\n@@ -0,0 +1,15 @@\n+/*\n+ * Copyright (C) 2026 NVIDIA\n+ * Written by Tushar Dave\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef HW_PCI_PCI_ENUMERATE_H\n+#define HW_PCI_PCI_ENUMERATE_H\n+\n+#include \"hw/pci/pci_bus.h\"\n+\n+void pci_enumerate_bus(PCIBus *root_bus);\n+\n+#endif\n","prefixes":["RFC","2/8"]}