{"id":2235114,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235114/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-25-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-25-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:25","name":"[v3,25/32] target/mips: add Octeon LA* atomic instructions","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5b32993136e1174435d71cb0148a8ae27f3dd7d2","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-25-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235114/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235114/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Hg6YkWW5;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt6M5nqwz1yJq\n\tfor ; Sat, 09 May 2026 01:18:03 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMuE-0004Kn-2c; Fri, 08 May 2026 11:14:22 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtJ-0002hm-RQ\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:26 -0400","from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtH-0001lr-RB\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:25 -0400","by mail-oa1-x2a.google.com with SMTP id\n 586e51a60fabf-409de4132b5so1295181fac.1\n for ; Fri, 08 May 2026 08:13:23 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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(suggested by\n Philippe Mathieu-Daudé)\n\nChanges v2 -> v3:\n - Drop redundant TARGET_LONG_BITS guards from doubleword atomic paths.\n (suggested by Richard Henderson)\n - Group LA* translator wrappers by argument shape instead of adding one\n wrapper per instruction. (suggested by Richard Henderson)\n---\n target/mips/tcg/octeon.decode | 17 ++++++\n target/mips/tcg/octeon_translate.c | 118 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 135 insertions(+)","diff":"diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 54ca92a654..6f4102044f 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -59,6 +59,23 @@ V3MULU 011100 ..... ..... ..... 00000 010001 @r3\n SAA 011100 ..... ..... 00000 00000 011000 @saa\n SAAD 011100 ..... ..... 00000 00000 011001 @saa\n \n+&la base rd\n+&laa base add rd\n+@la ...... base:5 ..... rd:5 ........... &la\n+@laa ...... base:5 add:5 rd:5 ........... &laa\n+LAI 011100 ..... 00000 ..... 00010 011111 @la\n+LAID 011100 ..... 00000 ..... 00011 011111 @la\n+LAD 011100 ..... 00000 ..... 00110 011111 @la\n+LADD 011100 ..... 00000 ..... 00111 011111 @la\n+LAA 011100 ..... ..... ..... 10010 011111 @laa\n+LAAD 011100 ..... ..... ..... 10011 011111 @laa\n+LAS 011100 ..... 00000 ..... 01010 011111 @la\n+LASD 011100 ..... 00000 ..... 01011 011111 @la\n+LAC 011100 ..... 00000 ..... 01110 011111 @la\n+LACD 011100 ..... 00000 ..... 01111 011111 @la\n+LAW 011100 ..... ..... ..... 10110 011111 @laa\n+LAWD 011100 ..... ..... ..... 10111 011111 @laa\n+\n &zcb base\n ZCB 011100 base:5 00000 00000 11100 011111 &zcb\n ZCBT 011100 base:5 00000 00000 11101 011111 &zcb\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex fe1ddeb973..cdaa926389 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -189,6 +189,112 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)\n return true;\n }\n \n+static bool trans_la_common(DisasContext *ctx, int base, int add_reg, int rd,\n+ int64_t imm, bool dw)\n+{\n+ TCGv_i64 addr = tcg_temp_new_i64();\n+\n+ gen_base_offset_addr(ctx, addr, base, 0);\n+\n+ if (dw) {\n+ TCGv_i64 value = tcg_temp_new_i64();\n+ TCGv_i64 old = tcg_temp_new_i64();\n+ MemOp amo = mo_endian(ctx) | MO_UQ | MO_ALIGN;\n+\n+ if (add_reg >= 0) {\n+ gen_load_gpr(value, add_reg);\n+ } else {\n+ tcg_gen_movi_i64(value, imm);\n+ }\n+\n+ tcg_gen_atomic_fetch_add_i64(old, addr, value, ctx->mem_idx, amo);\n+ gen_store_gpr(old, rd);\n+ } else {\n+ TCGv_i64 old = tcg_temp_new_i64();\n+ TCGv_i32 value32 = tcg_temp_new_i32();\n+ TCGv_i32 old32 = tcg_temp_new_i32();\n+ MemOp amo = mo_endian(ctx) | MO_UL | MO_ALIGN;\n+\n+ if (add_reg < 0) {\n+ tcg_gen_movi_i32(value32, imm);\n+ } else {\n+ TCGv_i64 value = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, add_reg);\n+ tcg_gen_extrl_i64_i32(value32, value);\n+ }\n+\n+ tcg_gen_atomic_fetch_add_i32(old32, addr, value32, ctx->mem_idx, amo);\n+ tcg_gen_ext_i32_i64(old, old32);\n+ gen_store_gpr(old, rd);\n+ }\n+\n+ return true;\n+}\n+\n+static bool trans_law_common(DisasContext *ctx, int base, int add_reg, int rd,\n+ int64_t imm, bool dw)\n+{\n+ TCGv_i64 addr = tcg_temp_new_i64();\n+\n+ gen_base_offset_addr(ctx, addr, base, 0);\n+\n+ if (dw) {\n+ TCGv_i64 value = tcg_temp_new_i64();\n+ TCGv_i64 old = tcg_temp_new_i64();\n+ MemOp amo = mo_endian(ctx) | MO_UQ | MO_ALIGN;\n+\n+ if (add_reg >= 0) {\n+ gen_load_gpr(value, add_reg);\n+ } else {\n+ tcg_gen_movi_i64(value, imm);\n+ }\n+\n+ tcg_gen_atomic_xchg_i64(old, addr, value, ctx->mem_idx, amo);\n+ gen_store_gpr(old, rd);\n+ } else {\n+ TCGv_i64 old = tcg_temp_new_i64();\n+ TCGv_i32 value32 = tcg_temp_new_i32();\n+ TCGv_i32 old32 = tcg_temp_new_i32();\n+ MemOp amo = mo_endian(ctx) | MO_UL | MO_ALIGN;\n+\n+ if (add_reg >= 0) {\n+ TCGv_i64 value = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, add_reg);\n+ tcg_gen_extrl_i64_i32(value32, value);\n+ } else {\n+ tcg_gen_movi_i32(value32, imm);\n+ }\n+\n+ tcg_gen_atomic_xchg_i32(old32, addr, value32, ctx->mem_idx, amo);\n+ tcg_gen_ext_i32_i64(old, old32);\n+ gen_store_gpr(old, rd);\n+ }\n+\n+ return true;\n+}\n+\n+static bool do_lai(DisasContext *ctx, arg_la *a, int64_t imm, bool dw)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, imm, dw);\n+}\n+\n+static bool do_laa(DisasContext *ctx, arg_laa *a, bool dw)\n+{\n+ return trans_la_common(ctx, a->base, a->add, a->rd, 0, dw);\n+}\n+\n+static bool do_las(DisasContext *ctx, arg_la *a, int64_t imm, bool dw)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, imm, dw);\n+}\n+\n+static bool do_law(DisasContext *ctx, arg_laa *a, bool dw)\n+{\n+ return trans_law_common(ctx, a->base, a->add, a->rd, 0, dw);\n+}\n+\n static bool trans_ZCB(DisasContext *ctx, arg_zcb *a)\n {\n TCGv_i64 addr = tcg_temp_new_i64();\n@@ -299,6 +405,18 @@ static bool trans_vmul(DisasContext *ctx, arg_decode_ext_octeon1 *a,\n \n TRANS(SAA, trans_saa, MO_UL);\n TRANS(SAAD, trans_saa, MO_UQ);\n+TRANS(LAI, do_lai, 1, false);\n+TRANS(LAID, do_lai, 1, true);\n+TRANS(LAD, do_lai, -1, false);\n+TRANS(LADD, do_lai, -1, true);\n+TRANS(LAA, do_laa, false);\n+TRANS(LAAD, do_laa, true);\n+TRANS(LAS, do_las, -1, false);\n+TRANS(LASD, do_las, -1, true);\n+TRANS(LAC, do_las, 0, false);\n+TRANS(LACD, do_las, 0, true);\n+TRANS(LAW, do_law, false);\n+TRANS(LAWD, do_law, true);\n TRANS(LBX, trans_lx, MO_SB);\n TRANS(LBUX, trans_lx, MO_UB);\n TRANS(LHX, trans_lx, MO_SW);\n","prefixes":["v3","25/32"]}