{"id":2235110,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235110/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-23-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-23-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:23","name":"[v3,23/32] target/mips: add Octeon V3MULU instruction","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"12f4c7a5783d89c4a7e28e3d40eb9c23fbb2a182","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-23-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235110/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235110/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=oHiyyhN9;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt5t5ncGz1yJq\n\tfor ; Sat, 09 May 2026 01:17:38 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMta-0002p7-3S; Fri, 08 May 2026 11:13:42 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtI-0002hV-Jf\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:26 -0400","from mail-oa1-x33.google.com ([2001:4860:4864:20::33])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtG-0001lH-3l\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:23 -0400","by mail-oa1-x33.google.com with SMTP id\n 586e51a60fabf-404254ffe8aso1780342fac.0\n for ; Fri, 08 May 2026 08:13:21 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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(requested by Richard Henderson)\n---\n target/mips/helper.h | 1 +\n target/mips/tcg/octeon.decode | 1 +\n target/mips/tcg/octeon_translate.c | 1 +\n target/mips/tcg/op_helper.c | 46 ++++++++++++++++++++++++++++++++++++++\n 4 files changed, 49 insertions(+)","diff":"diff --git a/target/mips/helper.h b/target/mips/helper.h\nindex 46ccad95c3..08fda55ae1 100644\n--- a/target/mips/helper.h\n+++ b/target/mips/helper.h\n@@ -26,6 +26,7 @@ DEF_HELPER_3(crc32c, tl, tl, tl, i32)\n DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)\n DEF_HELPER_3(octeon_vmulu, i64, env, i64, i64)\n DEF_HELPER_3(octeon_vmm0, i64, env, i64, i64)\n+DEF_HELPER_3(octeon_v3mulu, i64, env, i64, i64)\n \n /* microMIPS functions */\n DEF_HELPER_4(lwm, void, env, tl, tl, i32)\ndiff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 8a909ffcee..54ca92a654 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -52,6 +52,7 @@ MTM1 011100 rs:5 rt:5 00000 00000 001100 &r2\n MTM2 011100 rs:5 rt:5 00000 00000 001101 &r2\n VMULU 011100 ..... ..... ..... 00000 001111 @r3\n VMM0 011100 ..... ..... ..... 00000 010000 @r3\n+V3MULU 011100 ..... ..... ..... 00000 010001 @r3\n \n &saa base rt\n @saa ...... base:5 rt:5 ................ &saa\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex c1dd03debd..fe1ddeb973 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -314,3 +314,4 @@ TRANS(MTP1, trans_mtp, 1);\n TRANS(MTP2, trans_mtp, 2);\n TRANS(VMULU, trans_vmul, gen_helper_octeon_vmulu);\n TRANS(VMM0, trans_vmul, gen_helper_octeon_vmm0);\n+TRANS(V3MULU, trans_vmul, gen_helper_octeon_v3mulu);\ndiff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c\nindex a1465068af..e4107a304c 100644\n--- a/target/mips/tcg/op_helper.c\n+++ b/target/mips/tcg/op_helper.c\n@@ -192,6 +192,52 @@ uint64_t helper_octeon_vmm0(CPUMIPSState *env, uint64_t rs, uint64_t rt)\n return lo;\n }\n \n+uint64_t helper_octeon_v3mulu(CPUMIPSState *env, uint64_t rs, uint64_t rt)\n+{\n+ uint64_t lo, hi;\n+ uint64_t sum[7] = {};\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[0], rs);\n+ sum[0] = lo;\n+ sum[1] = hi;\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[1], rs);\n+ octeon_add_limb(sum, 7, lo, 1);\n+ octeon_add_limb(sum, 7, hi, 2);\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[2], rs);\n+ octeon_add_limb(sum, 7, lo, 2);\n+ octeon_add_limb(sum, 7, hi, 3);\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[3], rs);\n+ octeon_add_limb(sum, 7, lo, 3);\n+ octeon_add_limb(sum, 7, hi, 4);\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[4], rs);\n+ octeon_add_limb(sum, 7, lo, 4);\n+ octeon_add_limb(sum, 7, hi, 5);\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[5], rs);\n+ octeon_add_limb(sum, 7, lo, 5);\n+ octeon_add_limb(sum, 7, hi, 6);\n+\n+ octeon_add_limb(sum, 7, rt, 0);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[0], 0);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[1], 1);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[2], 2);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[3], 3);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[4], 4);\n+ octeon_add_limb(sum, 7, env->active_tc.octeon.P[5], 5);\n+\n+ env->active_tc.octeon.P[0] = sum[1];\n+ env->active_tc.octeon.P[1] = sum[2];\n+ env->active_tc.octeon.P[2] = sum[3];\n+ env->active_tc.octeon.P[3] = sum[4];\n+ env->active_tc.octeon.P[4] = sum[5];\n+ env->active_tc.octeon.P[5] = sum[6];\n+ return sum[0];\n+}\n+\n /* these crc32 functions are based on target/loongarch/tcg/op_helper.c */\n target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz)\n {\n","prefixes":["v3","23/32"]}