{"id":2235107,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235107/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-21-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-21-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:21","name":"[v3,21/32] target/mips: add Octeon VMULU instruction","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"27207bbee247373d0639a130659c35d98f35d74b","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-21-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235107/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235107/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=IQOdtHd7;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt5F57Ynz1yJq\n\tfor ; Sat, 09 May 2026 01:17:05 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMtm-0002zE-8G; Fri, 08 May 2026 11:14:00 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtG-0002hG-P7\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:24 -0400","from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtE-0001kZ-Jf\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:22 -0400","by mail-oa1-x2e.google.com with SMTP id\n 586e51a60fabf-435153d9b68so1271639fac.3\n for ; Fri, 08 May 2026 08:13:19 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. [71.218.113.237])\n by smtp.gmail.com with ESMTPSA id\n 586e51a60fabf-43557109b7dsm1897904fac.5.2026.05.08.08.13.18\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 08 May 2026 08:13:18 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1778253199; x=1778857999; darn=nongnu.org;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:from:to:cc:subject:date:message-id\n :reply-to; bh=uraQUC7CmqH7WHj/Zvs9bcsKQvF6ASjiwV9ETQK23L8=;\n b=IQOdtHd7PCW5D7GPkWlkafHeHYY/ywWFThRZqrdEm6opG+qNAxriVf/2mn2BdYudxJ\n PqrZMS7gMsEhkgrH0VBHsSUz6pfobsDu3E5u3V/6ML0UMUg/bRdDtykdVrYhldqSrpND\n O+0Ys/eXqTrE1flNd1H0jtUJGsbutzKAssEY6Hg84++zzR1TX1OPuk8B1HHcVu+f7fbN\n EtDk5vto2oeqIQW9pkJmda1r2/4Yh28rjfUeIRylLkw7GG9COS7He85cTIak/FAsrvo+\n jE3wExWGKxqNBzCQOHvMGm5V2tkit/xX6LYug4aHtwXzuTTmGSTSqAbgXCMdNcAxSzSk\n bCqw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1778253199; x=1778857999;\n h=cc:to:in-reply-to:references:message-id:content-transfer-encoding\n :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=uraQUC7CmqH7WHj/Zvs9bcsKQvF6ASjiwV9ETQK23L8=;\n b=HVOEzkZuxw0N5RlNnnxVo+LitJH8Sc+Ba2fZl5pgS6hcyWqh4ynA22nJhNmPEOOR82\n wMySHybb5Efvd1XlU9qOAUz+M1huPKK8zUGRNWQcPX8i8YMBpGRfd2Qlu0/0MyhXGtxz\n 7Y5r5OTC1c5SsK4tqPPCwzyem8GD6ifUXWG6Zoec8r4DbMkdf6ik5Z+gJqCBPcuy2tlG\n xAOvFFLLpW7CMI7AehizRqJnWYltt2Brxgct2AQh/q4A6zHwJeaDlJyQlB3jcfmIj8vL\n lauq4IXjkc+sPOlhLzR8o9j2TkRphlMnS3I//I2Z5OM+Ug26joWkdWOp1tESuvz17Ofc\n n5ug==","X-Gm-Message-State":"AOJu0Ywam3e+KnUCreFaIGNHoRGbaLfEzxz17h6CP0zJcHFNGB6JMHJL\n ovV/FGVBc9rxRAHfeQqO13NIfCOnh9N1zXn10+HMfGrdI/bgby1U7aKzbqpQ5w==","X-Gm-Gg":"Acq92OETfD8aFTdtpl16GfHjMXQjiB33G3d2T/4kvW09a0ec39g+i1fXkabAs4xqJN2\n tTkADgzK1ZXY4GOXmmmxE9fpkXk5Mo7Syi6IJ07VcxPC8+2uvqojVHUtr1dlbM8Nu9x8G+DO9dW\n WP62aA2epxXhxxQXVhBmGqRkkzTWUGW9Y5lR0FZNRoicEvElpYhaGkyNi8v2jSI5Uhj1+kDZVtt\n nTFSHtPeLECf3HmqF8SkzbN2vU7KVzBkpsmPH2fSzZPlQlmVdpP3bW7vaf0az2GrdpNmYvHiZVH\n iEXBkT9evaiSxanH8/LwWn/F+3jPeEpKVghNdGeaoKKQTx0N8QNggPyeUnMMI+ixx6UAuY9YV6e\n OII+GpJrBtSOgBvmTcUVXdVJp2Od/lda0wo4aSkW+CTFidHlDqX7WU1C2EGn+pQ4AfJ6JSHvxa1\n t+vMIhcYoP4u520q0nM0EIa+rzdvKit9IkbuoSCcwnv6OAawJ29XtjZCsflkT4dEzcWsRjjfZAe\n W79vIHmYGSFulOdLTBAAMUIJ4quj8TlEuz3mLVINb0Qo57NqO+G/A6xYtMmvGvtQYB909TAeD4w\n Kr9cobNieFWwNaQhiWU8ST1h/YnvuqgkSTQLUzl1EoxbfVoJTq/zeiEkGhgf8MlSpbnbE2I=","X-Received":"by 2002:a05:6871:797:b0:409:81eb:cf56 with SMTP id\n 586e51a60fabf-434f655e902mr8281485fac.27.1778253198874;\n Fri, 08 May 2026 08:13:18 -0700 (PDT)","From":"James Hilliard ","Date":"Fri, 08 May 2026 09:12:21 -0600","Subject":"[PATCH v3 21/32] target/mips: add Octeon VMULU instruction","MIME-Version":"1.0","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20260508-mips-octeon-missing-insns-v2-v3-21-bcbec96357d9@gmail.com>","References":"\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>","In-Reply-To":"\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= ,\n Aurelien Jarno ,\n Jiaxun Yang ,\n Aleksandar Rikalo , Huacai Chen ,\n James Hilliard , Helge Deller ,\n Pierrick Bouvier ,\n Pierrick Bouvier ","X-Mailer":"b4 0.15.2","Received-SPF":"pass client-ip=2001:4860:4864:20::2e;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x2e.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"VMULU multiplies the active Octeon multiplier state by rs, adds rt and\nqueued partial products, returns the low result, and advances P[0]/P[1]\nwith carry limbs.\n\nAdd helper and translator support for the two-limb accumulator operation.\n\nSigned-off-by: James Hilliard \n---\nChanges v2 -> v3:\n - Split VMULU out of the combined Octeon arithmetic and memory\n instruction patch. (requested by Richard Henderson)\n - Use uadd64_overflow() for multiplier limb carry accumulation.\n (suggested by Richard Henderson)\n---\n target/mips/helper.h | 1 +\n target/mips/tcg/octeon.decode | 1 +\n target/mips/tcg/octeon_translate.c | 17 +++++++++++++++++\n target/mips/tcg/op_helper.c | 32 ++++++++++++++++++++++++++++++++\n 4 files changed, 51 insertions(+)","diff":"diff --git a/target/mips/helper.h b/target/mips/helper.h\nindex e2b83a1d19..f1e78ae329 100644\n--- a/target/mips/helper.h\n+++ b/target/mips/helper.h\n@@ -24,6 +24,7 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl)\n DEF_HELPER_3(crc32, tl, tl, tl, i32)\n DEF_HELPER_3(crc32c, tl, tl, tl, i32)\n DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32)\n+DEF_HELPER_3(octeon_vmulu, i64, env, i64, i64)\n \n /* microMIPS functions */\n DEF_HELPER_4(lwm, void, env, tl, tl, i32)\ndiff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 7de2a8f6ec..1c3dbb4a33 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -50,6 +50,7 @@ MTP1 011100 rs:5 rt:5 00000 00000 001010 &r2\n MTP2 011100 rs:5 rt:5 00000 00000 001011 &r2\n MTM1 011100 rs:5 rt:5 00000 00000 001100 &r2\n MTM2 011100 rs:5 rt:5 00000 00000 001101 &r2\n+VMULU 011100 ..... ..... ..... 00000 001111 @r3\n \n &saa base rt\n @saa ...... base:5 rt:5 ................ &saa\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex 4207f01e85..bcbf73c052 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -13,6 +13,8 @@\n /* Include the auto-generated decoder. */\n #include \"decode-octeon.c.inc\"\n \n+typedef void gen_helper_lmi(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);\n+\n static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)\n {\n TCGv_i64 p;\n@@ -281,6 +283,20 @@ static bool trans_mtp(DisasContext *ctx, arg_r2 *a, unsigned int index)\n return true;\n }\n \n+static bool trans_vmul(DisasContext *ctx, arg_decode_ext_octeon1 *a,\n+ gen_helper_lmi *helper)\n+{\n+ TCGv_i64 rs = tcg_temp_new_i64();\n+ TCGv_i64 rt = tcg_temp_new_i64();\n+ TCGv_i64 rd = tcg_temp_new_i64();\n+\n+ gen_load_gpr(rs, a->rs);\n+ gen_load_gpr(rt, a->rt);\n+ helper(rd, tcg_env, rs, rt);\n+ gen_store_gpr(rd, a->rd);\n+ return true;\n+}\n+\n TRANS(SAA, trans_saa, MO_UL);\n TRANS(SAAD, trans_saa, MO_UQ);\n TRANS(LBX, trans_lx, MO_SB);\n@@ -296,3 +312,4 @@ TRANS(MTM2, trans_mtm, 2);\n TRANS(MTP0, trans_mtp, 0);\n TRANS(MTP1, trans_mtp, 1);\n TRANS(MTP2, trans_mtp, 2);\n+TRANS(VMULU, trans_vmul, gen_helper_octeon_vmulu);\ndiff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c\nindex 4502ae2b5b..ab3fb06a16 100644\n--- a/target/mips/tcg/op_helper.c\n+++ b/target/mips/tcg/op_helper.c\n@@ -144,6 +144,38 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,\n return (int64_t)(int32_t)(uint32_t)tmp5;\n }\n \n+static void octeon_add_limb(uint64_t *sum, int limb_count,\n+ uint64_t value, int limb)\n+{\n+ while (limb < limb_count &&\n+ uadd64_overflow(sum[limb], value, &sum[limb])) {\n+ value = 1;\n+ limb++;\n+ }\n+}\n+\n+uint64_t helper_octeon_vmulu(CPUMIPSState *env, uint64_t rs, uint64_t rt)\n+{\n+ uint64_t lo, hi;\n+ uint64_t sum[3] = {};\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[0], rs);\n+ sum[0] = lo;\n+ sum[1] = hi;\n+\n+ mulu64(&lo, &hi, env->active_tc.octeon.MPL[1], rs);\n+ octeon_add_limb(sum, 3, lo, 1);\n+ octeon_add_limb(sum, 3, hi, 2);\n+\n+ octeon_add_limb(sum, 3, rt, 0);\n+ octeon_add_limb(sum, 3, env->active_tc.octeon.P[0], 0);\n+ octeon_add_limb(sum, 3, env->active_tc.octeon.P[1], 1);\n+\n+ env->active_tc.octeon.P[0] = sum[1];\n+ env->active_tc.octeon.P[1] = sum[2];\n+ return sum[0];\n+}\n+\n /* these crc32 functions are based on target/loongarch/tcg/op_helper.c */\n target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz)\n {\n","prefixes":["v3","21/32"]}