{"id":2235103,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235103/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-2-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-2-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:02","name":"[v3,02/32] linux-user/mips: implement sysmips(MIPS_ATOMIC_SET)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"120660c9bb01a0c10fd9ea23af23ce85d8b4d89a","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-2-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235103/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235103/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=UIJBUCNI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt3j0rX3z1yJq\n\tfor ; Sat, 09 May 2026 01:15:45 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMt3-0002bs-2k; Fri, 08 May 2026 11:13:09 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMsx-0002bT-6X\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:03 -0400","from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMsv-0001bb-Mj\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:02 -0400","by mail-oa1-x2e.google.com with SMTP id\n 586e51a60fabf-40f1a1f77a6so1651350fac.2\n for ; Fri, 08 May 2026 08:13:01 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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Write the return value and error flag\ndirectly and return -QEMU_ESIGRETURN so the common syscall path leaves the\nregisters unchanged.\n\nSigned-off-by: James Hilliard \n---\nChanges v2 -> v3:\n - Split MIPS_ATOMIC_SET out of the combined sysmips/MIPS_FIXADE patch.\n (suggested by Richard Henderson)\n - Always use the explicit MIPS return-register path for successful\n atomic_set results. (suggested by Richard Henderson)\n---\n linux-user/mips/target_syscall.h | 1 +\n linux-user/mips64/target_syscall.h | 1 +\n linux-user/syscall.c | 31 +++++++++++++++++++++++++++++++\n 3 files changed, 33 insertions(+)","diff":"diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h\nindex 3f36c1695a..9206694f4f 100644\n--- a/linux-user/mips/target_syscall.h\n+++ b/linux-user/mips/target_syscall.h\n@@ -11,6 +11,7 @@\n \n #define TARGET_FORCE_SHMLBA\n #define TARGET_SYSMIPS_FLUSH_CACHE 3\n+#define TARGET_SYSMIPS_ATOMIC_SET 2001\n \n static inline abi_ulong target_shmlba(CPUMIPSState *env)\n {\ndiff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h\nindex 20ea7c6ab9..e07687f8ac 100644\n--- a/linux-user/mips64/target_syscall.h\n+++ b/linux-user/mips64/target_syscall.h\n@@ -11,6 +11,7 @@\n \n #define TARGET_FORCE_SHMLBA\n #define TARGET_SYSMIPS_FLUSH_CACHE 3\n+#define TARGET_SYSMIPS_ATOMIC_SET 2001\n \n static inline abi_ulong target_shmlba(CPUMIPSState *env)\n {\ndiff --git a/linux-user/syscall.c b/linux-user/syscall.c\nindex 73f09bb775..3786a34041 100644\n--- a/linux-user/syscall.c\n+++ b/linux-user/syscall.c\n@@ -6631,10 +6631,41 @@ static abi_long do_prctl_syscall_user_dispatch(CPUArchState *env,\n }\n \n #ifdef TARGET_NR_sysmips\n+static abi_long do_sysmips_atomic_set(CPUArchState *env, abi_ulong addr,\n+ abi_long value)\n+{\n+ uint32_t *ptr;\n+ abi_long old;\n+\n+ if (addr & 3) {\n+ return -TARGET_EINVAL;\n+ }\n+\n+ ptr = lock_user(VERIFY_WRITE, addr, sizeof(*ptr), true);\n+ if (!ptr) {\n+ return -TARGET_EINVAL;\n+ }\n+\n+ old = tswap32(qatomic_xchg(ptr, tswap32((uint32_t)value)));\n+ unlock_user(ptr, addr, sizeof(*ptr));\n+\n+ /*\n+ * MIPS uses a separate error flag, but the common linux-user syscall\n+ * path infers that flag from the return value. Successful atomic_set\n+ * results can overlap the target errno range, so write the result\n+ * registers here and ask the CPU loop to leave them alone.\n+ */\n+ env->active_tc.gpr[2] = old;\n+ env->active_tc.gpr[7] = 0;\n+ return -QEMU_ESIGRETURN;\n+}\n+\n static abi_long do_sysmips(CPUArchState *env, abi_long cmd, abi_long arg1,\n abi_long arg2)\n {\n switch (cmd) {\n+ case TARGET_SYSMIPS_ATOMIC_SET:\n+ return do_sysmips_atomic_set(env, arg1, arg2);\n case TARGET_SYSMIPS_FLUSH_CACHE:\n return 0;\n default:\n","prefixes":["v3","02/32"]}