{"id":2235100,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235100/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-1-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-1-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:01","name":"[v3,01/32] linux-user/mips: implement sysmips(MIPS_FLUSH_CACHE)","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"464dbe1736eeaf054f06b32d22d9228d166432ef","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-1-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235100/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235100/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=sFo7pxNZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt3Q1BdGz1yJq\n\tfor ; Sat, 09 May 2026 01:15:30 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMt3-0002bg-1u; Fri, 08 May 2026 11:13:09 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMsv-0002b9-Dx\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:01 -0400","from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMst-0001af-Qm\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:01 -0400","by mail-oa1-x2e.google.com with SMTP id\n 586e51a60fabf-43496e6a964so1603902fac.2\n for ; Fri, 08 May 2026 08:12:58 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","Message-Id":"\n <20260508-mips-octeon-missing-insns-v2-v3-1-bcbec96357d9@gmail.com>","References":"\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>","In-Reply-To":"\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>","To":"qemu-devel@nongnu.org","Cc":"Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= ,\n Aurelien Jarno ,\n Jiaxun Yang ,\n Aleksandar Rikalo , Huacai Chen ,\n James Hilliard , Helge Deller ,\n Pierrick Bouvier ,\n Pierrick Bouvier ","X-Mailer":"b4 0.15.2","Received-SPF":"pass client-ip=2001:4860:4864:20::2e;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x2e.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Add the target sysmips dispatcher and implement MIPS_FLUSH_CACHE as a\nsuccessful no-op for linux-user.\n\nSelf-modifying code is handled by QEMU's normal user-mode translation\ninvalidation machinery, so the target ABI only needs the syscall command\nto be accepted.\n\nSigned-off-by: James Hilliard \n---\nChanges v2 -> v3:\n - Split MIPS_FLUSH_CACHE out of the combined sysmips/MIPS_FIXADE patch.\n (suggested by Richard Henderson)\n---\n linux-user/mips/target_syscall.h | 1 +\n linux-user/mips64/target_syscall.h | 1 +\n linux-user/syscall.c | 17 +++++++++++++++++\n 3 files changed, 19 insertions(+)","diff":"diff --git a/linux-user/mips/target_syscall.h b/linux-user/mips/target_syscall.h\nindex dfcdf320b7..3f36c1695a 100644\n--- a/linux-user/mips/target_syscall.h\n+++ b/linux-user/mips/target_syscall.h\n@@ -10,6 +10,7 @@\n #define TARGET_MCL_ONFAULT 4\n \n #define TARGET_FORCE_SHMLBA\n+#define TARGET_SYSMIPS_FLUSH_CACHE 3\n \n static inline abi_ulong target_shmlba(CPUMIPSState *env)\n {\ndiff --git a/linux-user/mips64/target_syscall.h b/linux-user/mips64/target_syscall.h\nindex 9135bf5e8b..20ea7c6ab9 100644\n--- a/linux-user/mips64/target_syscall.h\n+++ b/linux-user/mips64/target_syscall.h\n@@ -10,6 +10,7 @@\n #define TARGET_MCL_ONFAULT 4\n \n #define TARGET_FORCE_SHMLBA\n+#define TARGET_SYSMIPS_FLUSH_CACHE 3\n \n static inline abi_ulong target_shmlba(CPUMIPSState *env)\n {\ndiff --git a/linux-user/syscall.c b/linux-user/syscall.c\nindex d3d9fffb54..73f09bb775 100644\n--- a/linux-user/syscall.c\n+++ b/linux-user/syscall.c\n@@ -6630,6 +6630,19 @@ static abi_long do_prctl_syscall_user_dispatch(CPUArchState *env,\n }\n }\n \n+#ifdef TARGET_NR_sysmips\n+static abi_long do_sysmips(CPUArchState *env, abi_long cmd, abi_long arg1,\n+ abi_long arg2)\n+{\n+ switch (cmd) {\n+ case TARGET_SYSMIPS_FLUSH_CACHE:\n+ return 0;\n+ default:\n+ return -TARGET_EINVAL;\n+ }\n+}\n+#endif\n+\n static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2,\n abi_long arg3, abi_long arg4, abi_long arg5)\n {\n@@ -12102,6 +12115,10 @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1,\n case TARGET_NR_prctl:\n return do_prctl(cpu_env, arg1, arg2, arg3, arg4, arg5);\n break;\n+#ifdef TARGET_NR_sysmips\n+ case TARGET_NR_sysmips:\n+ return do_sysmips(cpu_env, arg1, arg2, arg3);\n+#endif\n #ifdef TARGET_NR_arch_prctl\n case TARGET_NR_arch_prctl:\n return do_arch_prctl(cpu_env, arg1, arg2);\n","prefixes":["v3","01/32"]}