{"id":2235099,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235099/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-24-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-24-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:24","name":"[v3,24/32] tests/tcg/mips: add Octeon instruction smoke test","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"5dcf79a62e82da8eaefac1b87008bdaf2494c1af","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-24-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235099/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235099/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=e0vuK+iZ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt3M6Kvrz1yJq\n\tfor ; Sat, 09 May 2026 01:15:27 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMu9-0003kT-Ry; Fri, 08 May 2026 11:14:17 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtJ-0002hj-FT\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:26 -0400","from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtH-0001lY-3q\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:25 -0400","by mail-oa1-x2b.google.com with SMTP id\n 586e51a60fabf-42fbf95cca8so1592342fac.0\n for ; Fri, 08 May 2026 08:13:22 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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(requested by Richard Henderson)\n---\n MAINTAINERS | 2 +\n tests/tcg/mips/Makefile.target | 11 ++\n tests/tcg/mips/user/isa/octeon/octeon-insns.c | 145 ++++++++++++++++++++++++++\n tests/tcg/mips64/Makefile.target | 20 ++++\n tests/tcg/mips64el/Makefile.target | 8 ++\n 5 files changed, 186 insertions(+)","diff":"diff --git a/MAINTAINERS b/MAINTAINERS\nindex 9d3d645953..9501aaf36c 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -311,6 +311,8 @@ F: target/mips/\n F: disas/*mips.c\n F: docs/system/cpu-models-mips.rst.inc\n F: tests/tcg/mips/\n+F: tests/tcg/mips64/\n+F: tests/tcg/mips64el/\n \n OpenRISC TCG CPUs\n M: Stafford Horne \ndiff --git a/tests/tcg/mips/Makefile.target b/tests/tcg/mips/Makefile.target\nindex 5d17c1706e..d9dc16f8ec 100644\n--- a/tests/tcg/mips/Makefile.target\n+++ b/tests/tcg/mips/Makefile.target\n@@ -8,6 +8,17 @@ MIPS_SRC=$(SRC_PATH)/tests/tcg/mips\n # Set search path for all sources\n VPATH \t\t+= $(MIPS_SRC)\n \n+ifneq ($(findstring 64,$(TARGET_NAME)),)\n+VPATH += $(MIPS_SRC)/user/isa/octeon\n+\n+MIPS64_TESTS=octeon-insns\n+\n+TESTS += $(MIPS64_TESTS)\n+\n+octeon-insns: CFLAGS+=-mabi=64\n+run-octeon-insns: QEMU_OPTS+=-cpu Octeon68XX\n+endif\n+\n # hello-mips is 32 bit only\n ifeq ($(findstring 64,$(TARGET_NAME)),)\n MIPS_TESTS=hello-mips\ndiff --git a/tests/tcg/mips/user/isa/octeon/octeon-insns.c b/tests/tcg/mips/user/isa/octeon/octeon-insns.c\nnew file mode 100644\nindex 0000000000..e9db93d1b6\n--- /dev/null\n+++ b/tests/tcg/mips/user/isa/octeon/octeon-insns.c\n@@ -0,0 +1,145 @@\n+/*\n+ * Test Octeon-specific user-mode instructions.\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \n+#include \n+\n+static uint64_t octeon_baddu(uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x71095028\\n\\t\" /* baddu $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_dmul(uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x71095003\\n\\t\" /* dmul $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_dpop(uint64_t rs)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \".word 0x7100502d\\n\\t\" /* dpop $10, $8 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs)\n+ : \"$8\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_seq(uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x7109502a\\n\\t\" /* seq $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_sne(uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x7109502b\\n\\t\" /* sne $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_vmulu(uint64_t mpl0, uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[mpl0]\\n\\t\"\n+ \"move $9, $0\\n\\t\"\n+ \".word 0x71090008\\n\\t\" /* mtm0 $8, $9 */\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x7109500f\\n\\t\" /* vmulu $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [mpl0] \"r\" (mpl0), [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+static uint64_t octeon_vmm0(uint64_t mpl0, uint64_t p0,\n+ uint64_t rs, uint64_t rt)\n+{\n+ uint64_t rd;\n+\n+ asm volatile(\n+ \"move $8, %[mpl0]\\n\\t\"\n+ \"move $9, $0\\n\\t\"\n+ \".word 0x71090008\\n\\t\" /* mtm0 $8, $9 */\n+ \"move $8, %[p0]\\n\\t\"\n+ \"move $9, $0\\n\\t\"\n+ \".word 0x71090009\\n\\t\" /* mtp0 $8, $9 */\n+ \"move $8, %[rs]\\n\\t\"\n+ \"move $9, %[rt]\\n\\t\"\n+ \".word 0x71095010\\n\\t\" /* vmm0 $10, $8, $9 */\n+ \"move %[rd], $10\\n\\t\"\n+ : [rd] \"=r\" (rd)\n+ : [mpl0] \"r\" (mpl0), [p0] \"r\" (p0),\n+ [rs] \"r\" (rs), [rt] \"r\" (rt)\n+ : \"$8\", \"$9\", \"$10\");\n+\n+ return rd;\n+}\n+\n+int main(void)\n+{\n+ assert(octeon_baddu(0x123, 0x0f0) == 0x13);\n+ assert(octeon_dmul(0x12345678, 0x10) == 0x123456780);\n+ assert(octeon_dpop(0xf0f0f0f0f0f0f0f0ULL) == 32);\n+ assert(octeon_seq(0xabc, 0xabc) == 1);\n+ assert(octeon_seq(0xabc, 0xdef) == 0);\n+ assert(octeon_sne(0xabc, 0xabc) == 0);\n+ assert(octeon_sne(0xabc, 0xdef) == 1);\n+ assert(octeon_vmulu(5, 7, 11) == 46);\n+ assert(octeon_vmm0(5, 13, 7, 11) == 59);\n+\n+ return 0;\n+}\ndiff --git a/tests/tcg/mips64/Makefile.target b/tests/tcg/mips64/Makefile.target\nnew file mode 100644\nindex 0000000000..042855844a\n--- /dev/null\n+++ b/tests/tcg/mips64/Makefile.target\n@@ -0,0 +1,20 @@\n+# -*- Mode: makefile -*-\n+#\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# MIPS64 - included from tests/tcg/Makefile.target\n+#\n+\n+MIPS64_SRC=$(SRC_PATH)/tests/tcg/mips64\n+MIPS_OCTEON_SRC=$(SRC_PATH)/tests/tcg/mips/user/isa/octeon\n+\n+# Set search path for all sources\n+VPATH \t\t+= $(MIPS64_SRC) $(MIPS_OCTEON_SRC)\n+\n+MIPS64_TESTS=octeon-insns\n+\n+TESTS += $(MIPS64_TESTS)\n+\n+$(MIPS64_TESTS): CFLAGS+=-mabi=64\n+\n+run-octeon-insns: QEMU_OPTS+=-cpu Octeon68XX\ndiff --git a/tests/tcg/mips64el/Makefile.target b/tests/tcg/mips64el/Makefile.target\nnew file mode 100644\nindex 0000000000..dbc5f8dc5f\n--- /dev/null\n+++ b/tests/tcg/mips64el/Makefile.target\n@@ -0,0 +1,8 @@\n+# -*- Mode: makefile -*-\n+#\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# MIPS64 little-endian - included from tests/tcg/Makefile.target\n+#\n+\n+include $(SRC_PATH)/tests/tcg/mips64/Makefile.target\n","prefixes":["v3","24/32"]}