{"id":2235089,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235089/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-15-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-15-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:15","name":"[v3,15/32] target/mips: add Octeon MTM0 instruction","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"42dbac87de0284756c6ece6cc636abe33bb6ec95","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-15-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235089/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235089/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=fN3omTMI;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt2D5Rpzz1yM4\n\tfor ; Sat, 09 May 2026 01:14:28 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMty-0003WC-0L; Fri, 08 May 2026 11:14:06 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtB-0002fl-05\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:18 -0400","from mail-oo1-xc2b.google.com ([2607:f8b0:4864:20::c2b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMt8-0001iH-TU\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:16 -0400","by mail-oo1-xc2b.google.com with SMTP id\n 006d021491bc7-694891f8f62so1110542eaf.2\n for ; Fri, 08 May 2026 08:13:14 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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(requested by Richard Henderson)\n---\n target/mips/tcg/octeon.decode | 2 ++\n target/mips/tcg/octeon_translate.c | 55 ++++++++++++++++++++++++++++++++++++++\n 2 files changed, 57 insertions(+)","diff":"diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 56c54e0973..2dadb13845 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -43,6 +43,8 @@ SEQ 011100 ..... ..... ..... 00000 101010 @r3\n SNE 011100 ..... ..... ..... 00000 101011 @r3\n SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi\n SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi\n+&r2 rs rt\n+MTM0 011100 rs:5 rt:5 00000 00000 001000 &r2\n \n &saa base rt\n @saa ...... base:5 rt:5 ................ &saa\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex f94f765055..186200036e 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -216,6 +216,60 @@ static bool trans_ZCBT(DisasContext *ctx, arg_zcb *a)\n return trans_ZCB(ctx, a);\n }\n \n+static ptrdiff_t octeon_tc_mpl_offset(unsigned int index)\n+{\n+ return offsetof(CPUMIPSState, active_tc.octeon.MPL[index]);\n+}\n+\n+static ptrdiff_t octeon_tc_p_offset(unsigned int index)\n+{\n+ return offsetof(CPUMIPSState, active_tc.octeon.P[index]);\n+}\n+\n+static void octeon_store_tc_field(ptrdiff_t offset, TCGv_i64 value)\n+{\n+ tcg_gen_st_i64(value, tcg_env, offset);\n+}\n+\n+static void octeon_zero_partial_product_state(void)\n+{\n+ TCGv_i64 zero = tcg_constant_i64(0);\n+\n+ for (int i = 0; i < 2 * 3; i++) {\n+ octeon_store_tc_field(octeon_tc_p_offset(i), zero);\n+ }\n+}\n+\n+static void octeon_clear_upper_multiplier_state(void)\n+{\n+ TCGv_i64 zero = tcg_constant_i64(0);\n+\n+ /*\n+ * MTM0 starts a new multiplier chain. Guest code relies on a single\n+ * MTM0 load making the remaining multiplier limbs zero unless later\n+ * MTM1/MTM2 instructions explicitly populate them.\n+ */\n+ octeon_store_tc_field(octeon_tc_mpl_offset(1), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(2), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(4), zero);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(5), zero);\n+}\n+\n+static bool trans_mtm(DisasContext *ctx, arg_r2 *a, unsigned int index)\n+{\n+ TCGv_i64 value = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, a->rs);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(index), value);\n+ gen_load_gpr(value, a->rt);\n+ octeon_store_tc_field(octeon_tc_mpl_offset(index + 3), value);\n+ if (index == 0) {\n+ octeon_clear_upper_multiplier_state();\n+ }\n+ octeon_zero_partial_product_state();\n+ return true;\n+}\n+\n TRANS(SAA, trans_saa, MO_UL);\n TRANS(SAAD, trans_saa, MO_UQ);\n TRANS(LBX, trans_lx, MO_SB);\n@@ -225,3 +279,4 @@ TRANS(LHUX, trans_lx, MO_UW);\n TRANS(LWX, trans_lx, MO_SL);\n TRANS(LWUX, trans_lx, MO_UL);\n TRANS(LDX, trans_lx, MO_UQ);\n+TRANS(MTM0, trans_mtm, 0);\n","prefixes":["v3","15/32"]}