{"id":2235086,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235086/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-13-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-13-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:13","name":"[v3,13/32] target/mips: add Octeon ZCB instruction","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"14535b0a61f50a942e77ef1dc918bb9dff33e911","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-13-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235086/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235086/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=e684avDN;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt2515tsz1yKd\n\tfor ; Sat, 09 May 2026 01:14:21 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMtU-0002ll-AX; Fri, 08 May 2026 11:13:38 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtD-0002gH-Fa\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:20 -0400","from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMtB-0001j2-4b\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:19 -0400","by mail-ot1-x32a.google.com with SMTP id\n 46e09a7af769-7dd73b7c757so1116891a34.0\n for ; Fri, 08 May 2026 08:13:16 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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(requested by Richard Henderson)\n---\n target/mips/tcg/octeon.decode | 3 +++\n target/mips/tcg/octeon_translate.c | 24 ++++++++++++++++++++++++\n 2 files changed, 27 insertions(+)","diff":"diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex d77717cd50..d8a1bfce77 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -49,6 +49,9 @@ SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi\n SAA 011100 ..... ..... 00000 00000 011000 @saa\n SAAD 011100 ..... ..... 00000 00000 011001 @saa\n \n+&zcb base\n+ZCB 011100 base:5 00000 00000 11100 011111 &zcb\n+\n &lx base index rd\n @lx ...... base:5 index:5 rd:5 ...... ..... &lx\n LWX 011111 ..... ..... ..... 00000 001010 @lx\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex 104822a64a..c2a3eae134 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -187,6 +187,30 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)\n return true;\n }\n \n+static bool trans_ZCB(DisasContext *ctx, arg_zcb *a)\n+{\n+ TCGv_i64 addr = tcg_temp_new_i64();\n+ TCGv_i64 line = tcg_temp_new_i64();\n+ TCGv_i64 zero = tcg_constant_i64(0);\n+\n+ gen_base_offset_addr(ctx, addr, a->base, 0);\n+\n+ /*\n+ * QEMU models ZCB/ZCBT as zeroing the containing 128-byte cache line\n+ * in guest memory.\n+ */\n+ tcg_gen_andi_i64(line, addr, ~0x7fULL);\n+\n+ for (int i = 0; i < 16; i++) {\n+ TCGv_i64 slot = tcg_temp_new_i64();\n+\n+ tcg_gen_addi_i64(slot, line, i * 8);\n+ tcg_gen_qemu_st_i64(zero, slot, ctx->mem_idx, mo_endian(ctx) | MO_UQ);\n+ }\n+\n+ return true;\n+}\n+\n TRANS(SAA, trans_saa, MO_UL);\n TRANS(SAAD, trans_saa, MO_UQ);\n TRANS(LBX, trans_lx, MO_SB);\n","prefixes":["v3","13/32"]}