{"id":2235084,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2235084/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-4-bcbec96357d9@gmail.com/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260508-mips-octeon-missing-insns-v2-v3-4-bcbec96357d9@gmail.com>","list_archive_url":null,"date":"2026-05-08T15:12:04","name":"[v3,04/32] target/mips: fix Octeon arithmetic destination handling","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"d992aa24f487b002d604fb5fa1b91780949aefb7","submitter":{"id":66301,"url":"http://patchwork.ozlabs.org/api/1.2/people/66301/?format=json","name":"James Hilliard","email":"james.hilliard1@gmail.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-4-bcbec96357d9@gmail.com/mbox/","series":[{"id":503407,"url":"http://patchwork.ozlabs.org/api/1.2/series/503407/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407","date":"2026-05-08T15:12:00","name":"target/mips: add missing Octeon user-mode support","version":3,"mbox":"http://patchwork.ozlabs.org/series/503407/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2235084/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2235084/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=Zd8l2qDy;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt1Y71KGz1yKd\n\tfor ; Sat, 09 May 2026 01:13:53 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wLMtQ-0002jc-Bu; Fri, 08 May 2026 11:13:34 -0400","from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from )\n id 1wLMt0-0002c1-MW\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:08 -0400","from mail-oo1-xc2d.google.com ([2607:f8b0:4864:20::c2d])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from )\n id 1wLMsx-0001cH-IO\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:06 -0400","by mail-oo1-xc2d.google.com with SMTP id\n 006d021491bc7-685017d0fbcso1205425eaf.3\n for ; Fri, 08 May 2026 08:13:03 -0700 (PDT)","from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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Route writes through\ngen_store_gpr() so rd == $zero is handled consistently.\n\nSigned-off-by: James Hilliard \n---\nChanges v1 -> v2:\n - Split the BADDU/DMUL destination handling fix out of the Octeon\n arithmetic instruction patch. (suggested by Philippe Mathieu-Daudé)\n\nChanges v2 -> v3:\n - Remove the rd == $zero fast paths and let gen_store_gpr() discard\n writes to $zero. (suggested by Richard Henderson)\n---\n target/mips/tcg/octeon_translate.c | 16 ++++------------\n 1 file changed, 4 insertions(+), 12 deletions(-)","diff":"diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex e1f52d444a..4dd7626835 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -45,18 +45,14 @@ static bool trans_BADDU(DisasContext *ctx, arg_BADDU *a)\n {\n TCGv_i64 t0, t1;\n \n- if (a->rt == 0) {\n- /* nop */\n- return true;\n- }\n-\n t0 = tcg_temp_new_i64();\n t1 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n tcg_gen_add_i64(t0, t0, t1);\n- tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff);\n+ tcg_gen_andi_i64(t0, t0, 0xff);\n+ gen_store_gpr(t0, a->rd);\n return true;\n }\n \n@@ -64,17 +60,13 @@ static bool trans_DMUL(DisasContext *ctx, arg_DMUL *a)\n {\n TCGv_i64 t0, t1;\n \n- if (a->rt == 0) {\n- /* nop */\n- return true;\n- }\n-\n t0 = tcg_temp_new_i64();\n t1 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n- tcg_gen_mul_i64(cpu_gpr[a->rd], t0, t1);\n+ tcg_gen_mul_i64(t0, t0, t1);\n+ gen_store_gpr(t0, a->rd);\n return true;\n }\n \n","prefixes":["v3","04/32"]}