{"id":2234700,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2234700/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-57-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260507234413.643512-57-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-05-07T23:44:09","name":"[v4,56/60] target/arm: Implement FMMLA (FP8 to FP32) for SVE","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"866547dc866ec40ee2e7381edca959b1b99f4d89","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-57-richard.henderson@linaro.org/mbox/","series":[{"id":503296,"url":"http://patchwork.ozlabs.org/api/1.2/series/503296/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296","date":"2026-05-07T23:43:14","name":"target/arm: Implement FEAT_FP8","version":4,"mbox":"http://patchwork.ozlabs.org/series/503296/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2234700/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2234700/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=fUWPdmvn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-oa1-x32.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/translate-sve.c | 16 ++++++++++++++++\n target/arm/tcg/sve.decode | 2 ++\n 3 files changed, 23 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 1f1c090ef5..0aaf08eba9 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1687,6 +1687,11 @@ static inline bool isar_feature_aa64_sve_bf16(const ARMISARegisters *id)\n return isar_feature_aa64_sve(id) && isar_feature_aa64_sme_sve_bf16(id);\n }\n \n+static inline bool isar_feature_aa64_sve2_f8mm8(const ARMISARegisters *id)\n+{\n+ return isar_feature_aa64_sve2(id) && isar_feature_aa64_f8mm8(id);\n+}\n+\n static inline bool\n isar_feature_aa64_sme2_or_sve2_faminmax(const ARMISARegisters *id)\n {\ndiff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c\nindex 8d622f9a1c..5bda5f6c01 100644\n--- a/target/arm/tcg/translate-sve.c\n+++ b/target/arm/tcg/translate-sve.c\n@@ -8442,3 +8442,19 @@ static bool do_f8dp2(DisasContext *s, gen_helper_gvec_3_ptr *fn,\n TRANS(FDOT_hb, do_f8dp2, gen_helper_gvec_fdot_hb, a->rd, a->rn, a->rm, 0)\n TRANS(FDOT_idx_hb, do_f8dp2, gen_helper_gvec_fdot_idx_hb,\n a->rd, a->rn, a->rm, a->index)\n+\n+static bool do_fmmla_fp8(DisasContext *s, arg_rrrr_esz *a,\n+ gen_helper_gvec_3_ptr *fn)\n+{\n+ if (fpmr_access_check(s) && sve_access_check(s)) {\n+ unsigned vsz = vec_full_reg_size(s);\n+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, a->rd),\n+ vec_full_reg_offset(s, a->rn),\n+ vec_full_reg_offset(s, a->rm),\n+ tcg_env, vsz, vsz, 0, fn);\n+ }\n+ return true;\n+}\n+\n+TRANS_FEAT_NONSTREAMING(FMMLA_sb, aa64_sve2_f8mm8, do_fmmla_fp8, a,\n+ gen_helper_gvec_fmmla_sb)\ndiff --git a/target/arm/tcg/sve.decode b/target/arm/tcg/sve.decode\nindex 26b3c7697a..6610432528 100644\n--- a/target/arm/tcg/sve.decode\n+++ b/target/arm/tcg/sve.decode\n@@ -1808,6 +1808,8 @@ BFMMLA 01100100 01 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=1\n FMMLA_s 01100100 10 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=2\n FMMLA_d 01100100 11 1 ..... 111 001 ..... ..... @rda_rn_rm_ex esz=3\n \n+FMMLA_sb 01100100 00 1 ..... 111 000 ..... ..... @rda_rn_rm_ex esz=2\n+\n ### SVE2 Memory Gather Load Group\n \n # SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets)\n","prefixes":["v4","56/60"]}