{"id":2234669,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2234669/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-9-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260507234413.643512-9-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-05-07T23:43:21","name":"[v4,08/60] target/arm: Introduce FPMR","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"2cc6533c169c1b1f36aa58549a030c72eb0f9cc8","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-9-richard.henderson@linaro.org/mbox/","series":[{"id":503296,"url":"http://patchwork.ozlabs.org/api/1.2/series/503296/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296","date":"2026-05-07T23:43:14","name":"target/arm: Implement FEAT_FP8","version":4,"mbox":"http://patchwork.ozlabs.org/series/503296/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2234669/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2234669/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google 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","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org","Subject":"[PATCH v4 08/60] target/arm: Introduce FPMR","Date":"Thu, 7 May 2026 18:43:21 -0500","Message-ID":"<20260507234413.643512-9-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260507234413.643512-1-richard.henderson@linaro.org>","References":"<20260507234413.643512-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::32d;\n envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Introduce the special register FPMR and its fields.\nMigrate it when present.\n\nSigned-off-by: Richard Henderson \n---\n target/arm/cpregs.h | 5 +++++\n target/arm/cpu-features.h | 5 +++++\n target/arm/cpu.h | 1 +\n target/arm/internals.h | 9 +++++++++\n target/arm/helper.c | 12 +++++++++++-\n target/arm/machine.c | 20 ++++++++++++++++++++\n 6 files changed, 51 insertions(+), 1 deletion(-)","diff":"diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h\nindex f5ec7484c1..391c0e322b 100644\n--- a/target/arm/cpregs.h\n+++ b/target/arm/cpregs.h\n@@ -149,6 +149,11 @@ enum {\n * should not trap to EL2 when HCR_EL2.NV is set.\n */\n ARM_CP_NV_NO_TRAP = 1 << 22,\n+ /*\n+ * Flag: Access check for this sysreg is constrained by the\n+ * ARM pseudocode function CheckFPMREnabled().\n+ */\n+ ARM_CP_FPMR = 1 << 23,\n };\n \n /*\ndiff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 4ce661d7fe..4ab2a51c99 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1186,6 +1186,11 @@ static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) != 0;\n }\n \n+static inline bool isar_feature_aa64_fpmr(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64PFR2, FPMR) != 0;\n+}\n+\n static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id)\n {\n return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >= 1;\ndiff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex aeba70e6fc..c6f1f1a688 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -691,6 +691,7 @@ typedef struct CPUArchState {\n */\n uint64_t fpsr;\n uint64_t fpcr;\n+ uint64_t fpmr;\n \n uint32_t xregs[16];\n \ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 6376ae1ca3..08024943c3 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -292,6 +292,15 @@ FIELD(CNTHCTL, EVNTIS, 17, 1)\n FIELD(CNTHCTL, CNTVMASK, 18, 1)\n FIELD(CNTHCTL, CNTPMASK, 19, 1)\n \n+FIELD(FPMR, F8S1, 0, 3)\n+FIELD(FPMR, F8S2, 3, 3)\n+FIELD(FPMR, F8D, 6, 3)\n+FIELD(FPMR, OSM, 14, 1)\n+FIELD(FPMR, OSC, 15, 1)\n+FIELD(FPMR, LSCALE, 16, 7)\n+FIELD(FPMR, NSCALE, 24, 8)\n+FIELD(FPMR, LSCALE2, 32, 6)\n+\n /* We use a few fake FSR values for internal purposes in M profile.\n * M profile cores don't have A/R format FSRs, but currently our\n * get_phys_addr() code assumes A/R profile and reports failures via\ndiff --git a/target/arm/helper.c b/target/arm/helper.c\nindex 66813bb298..304db1a479 100644\n--- a/target/arm/helper.c\n+++ b/target/arm/helper.c\n@@ -6209,6 +6209,14 @@ static const ARMCPRegInfo aie_reginfo[] = {\n .type = ARM_CP_CONST, .resetvalue = 0 },\n };\n \n+static const ARMCPRegInfo fpmr_reginfo[] = {\n+ { .name = \"FPMR\", .state = ARM_CP_STATE_AA64,\n+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 4, .opc2 = 2,\n+ .access = PL0_RW, .type = ARM_CP_FPU | ARM_CP_FPMR,\n+ .fieldoffset = offsetof(CPUARMState, vfp.fpmr),\n+ }\n+};\n+\n void register_cp_regs_for_features(ARMCPU *cpu)\n {\n /* Register all the coprocessor registers based on feature bits */\n@@ -7481,10 +7489,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)\n define_arm_cp_regs(cpu, mec_mte_reginfo);\n }\n }\n-\n if (cpu_isar_feature(aa64_aie, cpu)) {\n define_arm_cp_regs(cpu, aie_reginfo);\n }\n+ if (cpu_isar_feature(aa64_fpmr, cpu)) {\n+ define_arm_cp_regs(cpu, fpmr_reginfo);\n+ }\n \n if (cpu_isar_feature(any_predinv, cpu)) {\n define_arm_cp_regs(cpu, predinv_reginfo);\ndiff --git a/target/arm/machine.c b/target/arm/machine.c\nindex 8dc766d322..58f8dfd53c 100644\n--- a/target/arm/machine.c\n+++ b/target/arm/machine.c\n@@ -960,6 +960,25 @@ static const VMStateDescription vmstate_syndrome64 = {\n },\n };\n \n+static bool fpmr_needed(void *opaque)\n+{\n+ ARMCPU *cpu = opaque;\n+\n+ return arm_feature(&cpu->env, ARM_FEATURE_AARCH64)\n+ && cpu_isar_feature(aa64_fpmr, cpu);\n+}\n+\n+static const VMStateDescription vmstate_fpmr = {\n+ .name = \"cpu/fpmr\",\n+ .version_id = 1,\n+ .minimum_version_id = 1,\n+ .needed = fpmr_needed,\n+ .fields = (const VMStateField[]) {\n+ VMSTATE_UINT64(env.vfp.fpmr, ARMCPU),\n+ VMSTATE_END_OF_LIST()\n+ },\n+};\n+\n static int cpu_pre_save(void *opaque)\n {\n ARMCPU *cpu = opaque;\n@@ -1323,6 +1342,7 @@ const VMStateDescription vmstate_arm_cpu = {\n &vmstate_syndrome64,\n &vmstate_pstate64,\n &vmstate_event,\n+ &vmstate_fpmr,\n NULL\n }\n };\n","prefixes":["v4","08/60"]}