{"id":2234636,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2234636/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-3-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260507234413.643512-3-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-05-07T23:43:15","name":"[v4,02/60] target/arm: Implement FEAT_FAMINMAX for AdvSIMD","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"ee9232df29455b761935f876ced05769c865caad","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507234413.643512-3-richard.henderson@linaro.org/mbox/","series":[{"id":503296,"url":"http://patchwork.ozlabs.org/api/1.2/series/503296/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503296","date":"2026-05-07T23:43:14","name":"target/arm: Implement FEAT_FP8","version":4,"mbox":"http://patchwork.ozlabs.org/series/503296/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2234636/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2234636/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google 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","To":"qemu-devel@nongnu.org","Cc":"qemu-arm@nongnu.org","Subject":"[PATCH v4 02/60] target/arm: Implement FEAT_FAMINMAX for AdvSIMD","Date":"Thu, 7 May 2026 18:43:15 -0500","Message-ID":"<20260507234413.643512-3-richard.henderson@linaro.org>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260507234413.643512-1-richard.henderson@linaro.org>","References":"<20260507234413.643512-1-richard.henderson@linaro.org>","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::32d;\n envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Signed-off-by: Richard Henderson \n---\n target/arm/cpu-features.h | 5 +++++\n target/arm/tcg/helper-a64-defs.h | 7 +++++++\n target/arm/tcg/vec_internal.h | 7 +++++++\n target/arm/tcg/translate-a64.c | 14 +++++++++++++\n target/arm/tcg/vec_helper64.c | 35 ++++++++++++++++++++++++++++++++\n target/arm/tcg/a64.decode | 5 +++++\n 6 files changed, 73 insertions(+)","diff":"diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h\nindex 252044b057..21d0be73cd 100644\n--- a/target/arm/cpu-features.h\n+++ b/target/arm/cpu-features.h\n@@ -1061,6 +1061,11 @@ static inline bool isar_feature_aa64_ats1a(const ARMISARegisters *id)\n return FIELD_EX64_IDREG(id, ID_AA64ISAR2, ATS1A);\n }\n \n+static inline bool isar_feature_aa64_faminmax(const ARMISARegisters *id)\n+{\n+ return FIELD_EX64_IDREG(id, ID_AA64ISAR3, FAMINMAX) != 0;\n+}\n+\n static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id)\n {\n /* We always set the AdvSIMD and FP fields identically. */\ndiff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h\nindex 3c3c5dddb7..215df1201b 100644\n--- a/target/arm/tcg/helper-a64-defs.h\n+++ b/target/arm/tcg/helper-a64-defs.h\n@@ -145,6 +145,13 @@ DEF_HELPER_FLAGS_5(gvec_fmulx_idx_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst,\n DEF_HELPER_FLAGS_5(gvec_fmulx_idx_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n DEF_HELPER_FLAGS_5(gvec_fmulx_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n \n+DEF_HELPER_FLAGS_5(gvec_famax_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_famin_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_famax_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+\n #ifndef CONFIG_USER_ONLY\n DEF_HELPER_2(exception_return, void, env, i64)\n #endif\ndiff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h\nindex c7ccb28b18..cc2691b2f6 100644\n--- a/target/arm/tcg/vec_internal.h\n+++ b/target/arm/tcg/vec_internal.h\n@@ -338,6 +338,13 @@ bfloat16 helper_sme2_ah_fmin_b16(bfloat16 a, bfloat16 b, float_status *fpst);\n float32 sve_f16_to_f32(float16 f, float_status *fpst);\n float16 sve_f32_to_f16(float32 f, float_status *fpst);\n \n+float16 float16_famax(float16, float16, float_status *);\n+float16 float16_famin(float16, float16, float_status *);\n+float32 float32_famax(float32, float32, float_status *);\n+float32 float32_famin(float32, float32, float_status *);\n+float64 float64_famax(float64, float64, float_status *);\n+float64 float64_famin(float64, float64, float_status *);\n+\n /*\n * Decode helper functions for predicate as counter.\n */\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 9a27c4c6ec..3c6559964b 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -6478,6 +6478,20 @@ static gen_helper_gvec_3_ptr * const f_vector_fminnmp[3] = {\n };\n TRANS(FMINNMP_v, do_fp3_vector, a, 0, f_vector_fminnmp)\n \n+static gen_helper_gvec_3_ptr * const f_vector_famax[3] = {\n+ gen_helper_gvec_famax_h,\n+ gen_helper_gvec_famax_s,\n+ gen_helper_gvec_famax_d,\n+};\n+TRANS_FEAT(FAMAX, aa64_faminmax, do_fp3_vector, a, 0, f_vector_famax)\n+\n+static gen_helper_gvec_3_ptr * const f_vector_famin[3] = {\n+ gen_helper_gvec_famin_h,\n+ gen_helper_gvec_famin_s,\n+ gen_helper_gvec_famin_d,\n+};\n+TRANS_FEAT(FAMIN, aa64_faminmax, do_fp3_vector, a, 0, f_vector_famin)\n+\n static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)\n {\n if (fp_access_check(s)) {\ndiff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c\nindex 249a257177..b5ad67b5e0 100644\n--- a/target/arm/tcg/vec_helper64.c\n+++ b/target/arm/tcg/vec_helper64.c\n@@ -140,3 +140,38 @@ void HELPER(simd_tblx)(void *vd, void *vm, CPUARMState *env, uint32_t desc)\n memcpy(vd, &result, 16);\n clear_tail(vd, oprsz, simd_maxsz(desc));\n }\n+\n+#define DO_FAMINMAX(NAME, TYPE, FN) \\\n+TYPE TYPE##_##NAME(TYPE a, TYPE b, float_status *s) \\\n+{ \\\n+ bool save_fz = get_flush_to_zero(s); \\\n+ bool save_fiz = get_flush_inputs_to_zero(s); \\\n+ int new_flags, save_flags = get_float_exception_flags(s); \\\n+ \\\n+ set_flush_to_zero(0, s); \\\n+ set_flush_inputs_to_zero(0, s); \\\n+ TYPE r = TYPE##_##FN(TYPE##_abs(a), TYPE##_abs(b), s); \\\n+ \\\n+ set_flush_to_zero(save_fz, s); \\\n+ set_flush_inputs_to_zero(save_fiz, s); \\\n+ new_flags = get_float_exception_flags(s); \\\n+ new_flags = (save_flags & float_flag_input_denormal_used) \\\n+ | (new_flags & ~float_flag_input_denormal_used); \\\n+ set_float_exception_flags(new_flags, s); \\\n+ \\\n+ return r; \\\n+}\n+\n+DO_FAMINMAX(famax, float16, max)\n+DO_FAMINMAX(famin, float16, min)\n+DO_FAMINMAX(famax, float32, max)\n+DO_FAMINMAX(famin, float32, min)\n+DO_FAMINMAX(famax, float64, max)\n+DO_FAMINMAX(famin, float64, min)\n+\n+DO_3OP(gvec_famax_h, float16_famax, float16)\n+DO_3OP(gvec_famin_h, float16_famin, float16)\n+DO_3OP(gvec_famax_s, float32_famax, float32)\n+DO_3OP(gvec_famin_s, float32_famin, float32)\n+DO_3OP(gvec_famax_d, float64_famax, float64)\n+DO_3OP(gvec_famin_d, float64_famin, float64)\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 01b1b3e38b..666a293540 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1193,6 +1193,11 @@ RSUBHN 0.10 1110 ..1 ..... 01100 0 ..... ..... @qrrr_e\n PMULL_p8 0.00 1110 001 ..... 11100 0 ..... ..... @qrrr_b\n PMULL_p64 0.00 1110 111 ..... 11100 0 ..... ..... @qrrr_b\n \n+FAMAX 0.00 1110 110 ..... 00011 1 ..... ..... @qrrr_h\n+FAMAX 0.00 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd\n+FAMIN 0.10 1110 110 ..... 00011 1 ..... ..... @qrrr_h\n+FAMIN 0.10 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd\n+\n ### Advanced SIMD scalar x indexed element\n \n FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h\n","prefixes":["v4","02/60"]}