{"id":2234617,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2234617/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507221717.486023-5-richard.henderson@linaro.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/1.2/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260507221717.486023-5-richard.henderson@linaro.org>","list_archive_url":null,"date":"2026-05-07T22:17:03","name":"[04/18] fpu: Introduce FloatSNaNRule","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"fad32cc778912aacf5944d4776be951ad18dad85","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/1.2/people/72104/?format=json","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20260507221717.486023-5-richard.henderson@linaro.org/mbox/","series":[{"id":503289,"url":"http://patchwork.ozlabs.org/api/1.2/series/503289/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503289","date":"2026-05-07T22:16:59","name":"fpu: Compress float_status","version":1,"mbox":"http://patchwork.ozlabs.org/series/503289/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2234617/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2234617/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=RbDqyvQz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-oa1-x34.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"},"content":"Merge snan_bit_is_one and no_signaling_nans into one control.\n\nSigned-off-by: Richard Henderson \n---\n include/fpu/softfloat-helpers.h | 14 ++---\n include/fpu/softfloat-types.h | 25 ++++++---\n target/mips/fpu_helper.h | 3 +-\n target/hppa/fpu_helper.c | 2 +-\n target/mips/msa.c | 4 +-\n target/sh4/cpu.c | 2 +-\n target/xtensa/cpu.c | 3 +-\n fpu/softfloat-specialize.c.inc | 95 ++++++++++++---------------------\n 8 files changed, 66 insertions(+), 82 deletions(-)","diff":"diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h\nindex 745a49f07a..95edd22842 100644\n--- a/include/fpu/softfloat-helpers.h\n+++ b/include/fpu/softfloat-helpers.h\n@@ -127,14 +127,9 @@ static inline void set_default_nan_mode(bool val, float_status *status)\n status->default_nan_mode = val;\n }\n \n-static inline void set_snan_bit_is_one(bool val, float_status *status)\n+static inline void set_snan_rule(FloatSNaNRule val, float_status *status)\n {\n- status->snan_bit_is_one = val;\n-}\n-\n-static inline void set_no_signaling_nans(bool val, float_status *status)\n-{\n- status->no_signaling_nans = val;\n+ status->float_snan_rule = val;\n }\n \n static inline bool get_float_detect_tininess(const float_status *status)\n@@ -203,6 +198,11 @@ static inline bool get_default_nan_mode(const float_status *status)\n return status->default_nan_mode;\n }\n \n+static inline FloatSNaNRule get_snan_rule(float_status *status)\n+{\n+ return status->float_snan_rule;\n+}\n+\n static inline FloatFTZDetection get_float_ftz_detection(const float_status *status)\n {\n return status->ftz_detection;\ndiff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h\nindex 5048faa76f..b8ce8ff78e 100644\n--- a/include/fpu/softfloat-types.h\n+++ b/include/fpu/softfloat-types.h\n@@ -192,6 +192,23 @@ typedef enum __attribute__((__packed__)) {\n floatx80_precision_s,\n } FloatX80RoundPrec;\n \n+/*\n+ * Define how the architecture discriminates signaling NaNs.\n+ * This done with the most significant bit of the fraction.\n+ *\n+ * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008\n+ * the msb must be 0. But setting the msb to 1 got baked into HPPA, SH4,\n+ * and pre-2008 MIPS.\n+ *\n+ * Further, some architectures (or modes of architectures) do not detect\n+ * signaling NaNs at all.\n+ */\n+typedef enum __attribute__((__packed__)) {\n+ float_snan_bit_is_zero = 0,\n+ float_snan_bit_is_one = 1,\n+ float_snan_never,\n+} FloatSNaNRule;\n+\n /*\n * 2-input NaN propagation rule. Individual architectures have\n * different rules for which input NaN is propagated to the output\n@@ -394,6 +411,7 @@ typedef struct float_status {\n Float2NaNPropRule float_2nan_prop_rule;\n Float3NaNPropRule float_3nan_prop_rule;\n FloatInfZeroNaNRule float_infzeronan_rule;\n+ FloatSNaNRule float_snan_rule;\n bool tininess_before_rounding;\n /* should denormalised results go to zero and set output_denormal_flushed? */\n bool flush_to_zero;\n@@ -412,13 +430,6 @@ typedef struct float_status {\n * create a default NaN.\n */\n uint8_t default_nan_pattern;\n- /*\n- * The flags below are not used on all specializations and may\n- * constant fold away (see snan_bit_is_one()/no_signalling_nans() in\n- * softfloat-specialize.inc.c)\n- */\n- bool snan_bit_is_one;\n- bool no_signaling_nans;\n /* should overflowed results subtract re_bias to its exponent? */\n bool rebias_overflow;\n /* should underflowed results add re_bias to its exponent? */\ndiff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h\nindex 08fb409390..cf667c6637 100644\n--- a/target/mips/fpu_helper.h\n+++ b/target/mips/fpu_helper.h\n@@ -35,7 +35,8 @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)\n * With nan2008, SNaNs are silenced in the usual way.\n * Before that, SNaNs are not silenced; default nans are produced.\n */\n- set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);\n+ set_snan_rule(nan2008 ? float_snan_bit_is_zero : float_snan_bit_is_one,\n+ &env->active_fpu.fp_status);\n set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);\n /*\n * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)\ndiff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c\nindex 2d272730f6..cdbebcfeb3 100644\n--- a/target/hppa/fpu_helper.c\n+++ b/target/hppa/fpu_helper.c\n@@ -66,7 +66,7 @@ void HELPER(loaded_fr0)(CPUHPPAState *env)\n set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);\n /* Default NaN: sign bit clear, msb-1 frac bit set */\n set_float_default_nan_pattern(0b00100000, &env->fp_status);\n- set_snan_bit_is_one(true, &env->fp_status);\n+ set_snan_rule(float_snan_bit_is_one, &env->fp_status);\n /*\n * \"PA-RISC 2.0 Architecture\" says it is IMPDEF whether the flushing\n * enabled by FPSR.D happens before or after rounding. We pick \"before\"\ndiff --git a/target/mips/msa.c b/target/mips/msa.c\nindex 32c6acbcc5..53fbce10d3 100644\n--- a/target/mips/msa.c\n+++ b/target/mips/msa.c\n@@ -84,8 +84,8 @@ void msa_reset(CPUMIPSState *env)\n /* clear float_status nan mode */\n set_default_nan_mode(0, &env->active_tc.msa_fp_status);\n \n- /* set proper signanling bit meaning (\"1\" means \"quiet\") */\n- set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);\n+ /* set proper signanling bit meaning */\n+ set_snan_rule(float_snan_bit_is_zero, &env->active_tc.msa_fp_status);\n \n /* Inf * 0 + NaN returns the input NaN */\n set_float_infzeronan_rule(float_infzeronan_dnan_never,\ndiff --git a/target/sh4/cpu.c b/target/sh4/cpu.c\nindex e2bde45761..0f40acea00 100644\n--- a/target/sh4/cpu.c\n+++ b/target/sh4/cpu.c\n@@ -151,7 +151,7 @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)\n set_flush_to_zero(1, &env->fp_status);\n #endif\n set_default_nan_mode(1, &env->fp_status);\n- set_snan_bit_is_one(true, &env->fp_status);\n+ set_snan_rule(float_snan_bit_is_one, &env->fp_status);\n /* sign bit clear, set all frac bits other than msb */\n set_float_default_nan_pattern(0b00111111, &env->fp_status);\n /*\ndiff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c\nindex 31429ec2f8..e6cd0e160d 100644\n--- a/target/xtensa/cpu.c\n+++ b/target/xtensa/cpu.c\n@@ -209,7 +209,8 @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)\n #endif\n /* For inf * 0 + NaN, return the input NaN */\n set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);\n- set_no_signaling_nans(!dfpu, &env->fp_status);\n+ set_snan_rule(dfpu ? float_snan_bit_is_zero : float_snan_never,\n+ &env->fp_status);\n /* Default NaN value: sign bit clear, set frac msb */\n set_float_default_nan_pattern(0b01000000, &env->fp_status);\n xtensa_use_first_nan(env, !dfpu);\ndiff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc\nindex 485f082cf8..29a2fdeb9b 100644\n--- a/fpu/softfloat-specialize.c.inc\n+++ b/fpu/softfloat-specialize.c.inc\n@@ -79,39 +79,29 @@ this code that are retained.\n * version 2 or later. See the COPYING file in the top-level directory.\n */\n \n-/*\n- * Define whether architecture deviates from IEEE in not supporting\n- * signaling NaNs (so all NaNs are treated as quiet).\n- */\n-static inline bool no_signaling_nans(float_status *status)\n-{\n- return status->no_signaling_nans;\n-}\n-\n-/* Define how the architecture discriminates signaling NaNs.\n- * This done with the most significant bit of the fraction.\n- * In IEEE 754-1985 this was implementation defined, but in IEEE 754-2008\n- * the msb must be zero. MIPS is (so far) unique in supporting both the\n- * 2008 revision and backward compatibility with their original choice.\n- */\n-static inline bool snan_bit_is_one(float_status *status)\n-{\n- return status->snan_bit_is_one;\n-}\n-\n /*----------------------------------------------------------------------------\n | For the deconstructed floating-point with fraction FRAC, return true\n | if the fraction represents a signalling NaN; otherwise false.\n *----------------------------------------------------------------------------*/\n \n+static bool frac_msb_is_snan(bool msb, float_status *status)\n+{\n+ FloatSNaNRule rule = get_snan_rule(status);\n+\n+ switch (rule) {\n+ case float_snan_never:\n+ return false;\n+ case float_snan_bit_is_one:\n+ case float_snan_bit_is_zero:\n+ return msb == rule;\n+ }\n+ g_assert_not_reached();\n+}\n+\n static bool parts_is_snan_frac(uint64_t frac, float_status *status)\n {\n- if (no_signaling_nans(status)) {\n- return false;\n- } else {\n- bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);\n- return msb == snan_bit_is_one(status);\n- }\n+ bool msb = extract64(frac, DECOMPOSED_BINARY_POINT - 1, 1);\n+ return frac_msb_is_snan(msb, status);\n }\n \n /*----------------------------------------------------------------------------\n@@ -167,14 +157,19 @@ FloatParts128 parts128_default_nan(float_status *status)\n \n static uint64_t parts_silence_nan_frac(uint64_t frac, float_status *status)\n {\n- g_assert(!no_signaling_nans(status));\n+ FloatSNaNRule rule = get_snan_rule(status);\n \n- /* The only snan_bit_is_one target without default_nan_mode is HPPA. */\n- if (snan_bit_is_one(status)) {\n+ switch (rule) {\n+ case float_snan_bit_is_zero:\n+ frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);\n+ break;\n+ case float_snan_bit_is_one:\n+ /* The only snan_bit_is_one target without default_nan_mode is HPPA. */\n frac &= ~(1ULL << (DECOMPOSED_BINARY_POINT - 1));\n frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 2);\n- } else {\n- frac |= 1ULL << (DECOMPOSED_BINARY_POINT - 1);\n+ break;\n+ default:\n+ g_assert_not_reached();\n }\n return frac;\n }\n@@ -238,11 +233,7 @@ floatx80 floatx80_default_inf(bool zSign, float_status *status)\n \n static bool float16_nan_is_snan(float16 a, float_status *status)\n {\n- if (no_signaling_nans(status)) {\n- return false;\n- }\n- bool frac_msb_is_one = (a >> 9) & 1;\n- return frac_msb_is_one == snan_bit_is_one(status);\n+ return frac_msb_is_snan((a >> 9) & 1, status);\n }\n \n /*----------------------------------------------------------------------------\n@@ -271,11 +262,7 @@ bool float16_is_signaling_nan(float16 a_, float_status *status)\n \n static bool bfloat16_nan_is_snan(bfloat16 a, float_status *status)\n {\n- if (no_signaling_nans(status)) {\n- return false;\n- }\n- bool frac_msb_is_one = (a >> 6) & 1;\n- return frac_msb_is_one == snan_bit_is_one(status);\n+ return frac_msb_is_snan((a >> 6) & 1, status);\n }\n \n /*----------------------------------------------------------------------------\n@@ -302,11 +289,7 @@ bool bfloat16_is_signaling_nan(bfloat16 a_, float_status *status)\n \n static bool float32_nan_is_snan(float32 a, float_status *status)\n {\n- if (no_signaling_nans(status)) {\n- return false;\n- }\n- bool frac_msb_is_one = (a >> 22) & 1;\n- return frac_msb_is_one == snan_bit_is_one(status);\n+ return frac_msb_is_snan((a >> 22) & 1, status);\n }\n \n /*----------------------------------------------------------------------------\n@@ -335,11 +318,7 @@ bool float32_is_signaling_nan(float32 a_, float_status *status)\n \n static bool float64_nan_is_snan(float64 a, float_status *status)\n {\n- if (no_signaling_nans(status)) {\n- return false;\n- }\n- bool frac_msb_is_one = (a >> 51) & 1;\n- return frac_msb_is_one == snan_bit_is_one(status);\n+ return frac_msb_is_snan((a >> 51) & 1, status);\n }\n \n /*----------------------------------------------------------------------------\n@@ -370,11 +349,7 @@ bool float64_is_signaling_nan(float64 a_, float_status *status)\n \n static bool floatx80_nan_is_snan(floatx80 a, float_status *status)\n {\n- if (no_signaling_nans(status)) {\n- return false;\n- }\n- bool frac_msb_is_one = (a.low >> 62) & 1;\n- return frac_msb_is_one == snan_bit_is_one(status);\n+ return frac_msb_is_snan((a.low >> 62) & 1, status);\n }\n \n /*----------------------------------------------------------------------------\n@@ -405,7 +380,7 @@ bool floatx80_is_signaling_nan(floatx80 a, float_status *status)\n floatx80 floatx80_silence_nan(floatx80 a, float_status *status)\n {\n /* None of the targets that have snan_bit_is_one use floatx80. */\n- assert(!snan_bit_is_one(status));\n+ assert(get_snan_rule(status) == float_snan_bit_is_zero);\n a.low |= UINT64_C(0xC000000000000000);\n return a;\n }\n@@ -416,11 +391,7 @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)\n \n static bool float128_nan_is_snan(float128 a, float_status *status)\n {\n- if (no_signaling_nans(status)) {\n- return false;\n- }\n- bool frac_msb_is_one = (a.high >> 47) & 1;\n- return frac_msb_is_one == snan_bit_is_one(status);\n+ return frac_msb_is_snan((a.high >> 47) & 1, status);\n }\n \n /*----------------------------------------------------------------------------\n","prefixes":["04/18"]}