{"id":2234297,"url":"http://patchwork.ozlabs.org/api/1.2/patches/2234297/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260507154557.2082697-2-kkartik@nvidia.com/","project":{"id":21,"url":"http://patchwork.ozlabs.org/api/1.2/projects/21/?format=json","name":"Linux Tegra Development","link_name":"linux-tegra","list_id":"linux-tegra.vger.kernel.org","list_email":"linux-tegra@vger.kernel.org","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20260507154557.2082697-2-kkartik@nvidia.com>","list_archive_url":null,"date":"2026-05-07T15:45:54","name":"[1/4] clocksource/drivers/timer-tegra186: Fix support for multiple watchdog instances","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"dff15e421512c2dccde77b9cc2780d8c08fc9021","submitter":{"id":83016,"url":"http://patchwork.ozlabs.org/api/1.2/people/83016/?format=json","name":"Kartik Rajput","email":"kkartik@nvidia.com"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/linux-tegra/patch/20260507154557.2082697-2-kkartik@nvidia.com/mbox/","series":[{"id":503205,"url":"http://patchwork.ozlabs.org/api/1.2/series/503205/?format=json","web_url":"http://patchwork.ozlabs.org/project/linux-tegra/list/?series=503205","date":"2026-05-07T15:45:55","name":"Add support for Kernel WDT","version":1,"mbox":"http://patchwork.ozlabs.org/series/503205/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/2234297/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/2234297/checks/","tags":{},"related":[],"headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=f4foOIos;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;","Received-SPF":"Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.118.232 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.118.232; helo=mail.nvidia.com; pr=C","From":"Kartik Rajput ","To":", , ,\n\t, , ,\n\t, ,\n\t, ","CC":"","Subject":"[PATCH 1/4] clocksource/drivers/timer-tegra186: Fix support for\n multiple watchdog instances","Date":"Thu, 7 May 2026 21:15:54 +0530","Message-ID":"<20260507154557.2082697-2-kkartik@nvidia.com>","X-Mailer":"git-send-email 2.43.0","In-Reply-To":"<20260507154557.2082697-1-kkartik@nvidia.com>","References":"<20260507154557.2082697-1-kkartik@nvidia.com>","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","Content-Type":"text/plain","X-NV-OnPremToCloud":"ExternallySecured","X-EOPAttributedMessage":"0","X-MS-PublicTrafficType":"Email","X-MS-TrafficTypeDiagnostic":"BL02EPF0001A0FB:EE_|PH7PR12MB7212:EE_","X-MS-Office365-Filtering-Correlation-Id":"090e7576-f8a9-47ed-1e6e-08deac4fdafe","X-MS-Exchange-SenderADCheck":"1","X-MS-Exchange-AntiSpam-Relay":"0","X-Microsoft-Antispam":"\n\tBCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|921020|18002099003|22082099003|56012099003;","X-Microsoft-Antispam-Message-Info":"\n\tlXodxVUngW+BS2+z+6eKflEb1Xagi0jqQCxU4/jOQDbkOGeZGUbXeCEPO/0U6CbfzACTyf1xdEQdiWnDLfhUV2s2dRoPBzcvmXfpAmOhwEVdXQABDkAhs1A9SS5I+xzJna0R64S6/+VynoNP5VceJ+Ic5oR3vLPhVQT07NveEECJK71b9LiCFq6DuG0/X81RIYmXi1xVKiKS6IEbGEJJVpIwRFgur67KWiGW17YGwqqd432GiqIUr2pBcBJQS0KfhzRFUYzBn8pxxoieQHPbgG/69miCkSd0PJ6uPoR91LL+u/rFsY4oSDka+bNiiHF52woPfrHb2zS6e59cjRVn62I2ZOBp4e+UmZyweTPBwoF2tsZ+m6jzehSH72NQ1VU/VS2DFi2dBw0hXVT4GXawM09EFJZfkXtM1zBI3fL7NzgU3RCHOW4u+Owlz0MdrReTpD0YLL+DfUMvIu3lDKJpcU9ldybCoOILS6i4HC9xFUxTOeGpQPWltRPJFMuiVovJ7MnzunKRTjjgL+2tSFyTb99/7jW71rSXZIddDWqbLG0DOacOSSAQvBLHQWE2U6HdGZATr4hv9lF1XVey6pjhqTJOp6kaMQePUdMAfa6ACKyqqMr8bI2D+YnHjyWsn/DQ5mF1d04wi3L55fz+fh7SX+vw1/oTLmBcn9i/Ofk3KpqVKns1n1Oe6t7h5iG2bJ1vDwky61nxuyYJn8nksZN1roVpfERznMHwwb4r/wTZW7CE4ibWYX0U9m0NSytMZgo2q9nNc1t2kU8CAYcopRPXEw==","X-Forefront-Antispam-Report":"\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(1800799024)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;","X-MS-Exchange-AntiSpam-MessageData-ChunkCount":"1","X-MS-Exchange-AntiSpam-MessageData-0":"\n\tNrxJZxwTX0oHysKpoZnhdRPW9s33CXHk/kuO5IAHoOneuB4cv/mXgbFV1wft8q45IfC2nznrSWREf9m43QTkDbeJFQGFTVrjCGnRYbFkyo46VddbffoRUgaq5aW2jeVYSTKnayMrFpmlLJeiGJxasKdqK2eFkRcaDEIjt0vSR3uBVZh8/xZesE8fry0kkulNC7uYdO5KnmsguJpVyFqgg17oqzqYYkvqed60No6pefLQZ3Pn+DcuHRsWvU5P9pqG5v9lR4ridoKTkJieznTWwcp3xuFlBt6i7JWK57b+A3qEVT3faTCnPKoy+Y6Krp3/SyWXWuHOKydFOlV4JXxZaJkvSdnLz/Vd7Tl8tLR0vuwmtUGK/fvQJdneOmeuLiSx9o+rg+EQfO7xJ1nIQ4qNJb28Lkj6b7QCwOjN5WqTuSgwU1Saw56mTLOYEUlYyt6C","X-OriginatorOrg":"Nvidia.com","X-MS-Exchange-CrossTenant-OriginalArrivalTime":"07 May 2026 15:46:50.7910\n (UTC)","X-MS-Exchange-CrossTenant-Network-Message-Id":"\n 090e7576-f8a9-47ed-1e6e-08deac4fdafe","X-MS-Exchange-CrossTenant-Id":"43083d15-7273-40c1-b7db-39efd9ccc17a","X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp":"\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n\tBL02EPF0001A0FB.namprd03.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-MS-Exchange-Transport-CrossTenantHeadersStamped":"PH7PR12MB7212"},"content":"Tegra SoCs support multiple watchdogs; currently only one (WDT0) is\nused. When multiple watchdogs are registered, tegra186_wdt_enable()\noverwrites the TKEIE(x) register, discarding any existing watchdog\ninterrupt enable bits. As a result, enabling one watchdog inadvertently\ndisables interrupts for the others.\n\nFix this by preserving the existing TKEIE(x) value and updating it\nusing a read-modify-write sequence.\n\nFixes: 42cee19a9f83 (\"clocksource: Add Tegra186 timers support\")\nCc: stable@vger.kernel.org\nSigned-off-by: Kartik Rajput \n---\n drivers/clocksource/timer-tegra186.c | 3 ++-\n 1 file changed, 2 insertions(+), 1 deletion(-)","diff":"diff --git a/drivers/clocksource/timer-tegra186.c b/drivers/clocksource/timer-tegra186.c\nindex 355558893e5f..bfe16d2d5104 100644\n--- a/drivers/clocksource/timer-tegra186.c\n+++ b/drivers/clocksource/timer-tegra186.c\n@@ -149,7 +149,8 @@ static void tegra186_wdt_enable(struct tegra186_wdt *wdt)\n \tu32 value;\n \n \t/* unmask hardware IRQ, this may have been lost across powergate */\n-\tvalue = TKEIE_WDT_MASK(wdt->index, 1);\n+\tvalue = readl(tegra->regs + TKEIE(wdt->tmr->hwirq));\n+\tvalue |= TKEIE_WDT_MASK(wdt->index, 1);\n \twritel(value, tegra->regs + TKEIE(wdt->tmr->hwirq));\n \n \t/* clear interrupt */\n","prefixes":["1/4"]}